TWI438881B - Package structure and its manufacturing method - Google Patents

Description

Package structure and its manufacturing method

The invention relates to a package structure and a preparation method thereof, in particular to a package structure with a thinning advantage and a preparation method thereof.

With the booming development of the electronics industry, electronic products tend to be thin and light in size, and the specifications still need to comply with the JEDEC (Joint Electronic Device Engineering Council) specification, so the packaging method is very important. For example, a wafer with a Dynamic Random Access Memory (DRAM) is developed to be smaller than 40 nm, and the size of the wafer is smaller and smaller, but the packaged area still needs to be the same, so that the package structure is used to connect the circuit board (PCB). The ball pitch is maintained at 0.8 mm to meet JEDEC standards, so the diffusion type wafer size package is a packaging method that can be used. Among them, the third-generation Double Synchronous Dynamic Random Access Memory (DDR3 SDRAM) is a computer memory specification, and its common packaging method is Window BGA.

Please refer to FIG. 1 , which is a cross-sectional view of a conventional memory package structure. As shown in FIG. 1 , the package structure 1 provides a package substrate 10 having an opening 100 , and a semiconductor wafer 11 is disposed on the lower surface 10 b of the package substrate 10 with its active surface 11 a to cover the opening 100 . One end of the electrode pad 110 of the semiconductor wafer 11 is located in the opening 100; then, the electrode pad 110 and the package substrate are electrically connected by the gold wire 12 10, the wire pad 101 of the upper surface 10a, and the protective material 14 is disposed in the opening 100 to cover the gold wire 12; then, the encapsulant 13 is disposed on the lower surface 10b of the package substrate 10 and encapsulates the semiconductor The non-active surface 11b and the side surface of the wafer 11 are formed. Finally, solder balls 16 are formed on the ball pad 102 of the upper surface 10a of the package substrate 10 to connect the circuit board. The overall height of the package structure 1 (including the solder balls 16) is 1.1 to 1.2 mm.

However, in the prior art, the gold wire 12 is required to be used as the component of the electrical connection. Therefore, the package colloid 13 needs to consider the height of the gold wire 12 during packaging, so that it is difficult to reduce the height of the overall structure, resulting in the gold wire 12 becoming A factor that hinders the memory from becoming thinner.

Furthermore, the bandwidth requirement of the memory increases, and the gold wire 12 serves as an electrical conduction path, because the gold wire 12 needs to have a certain length, so that the electrical conduction path often affects the electrical effect due to its long path. For example, the quality of the inductor and capacitor makes it difficult to meet the requirements of high-bandwidth memory.

Moreover, the use of gold as a wire leads to an increase in manufacturing costs.

Therefore, how to overcome the various problems in the above-mentioned prior art has become a problem that is currently being solved.

In view of the above-mentioned various deficiencies of the prior art, the present invention provides a package structure for embedding a wafer, comprising: a semiconductor wafer having opposite active and non-active surfaces, and having a bonding head bump on the active surface An electrode pad; a dielectric layer covering the active surface and the side surface of the semiconductor wafer and the stud bump, and exposing an inactive surface of the semiconductor wafer; the circuit layer is disposed on the dielectric layer, and Conductive blind holes provided in the dielectric layer are electrically The stud bump is connected to the stud bump; and an insulating protective layer is disposed on the dielectric layer and the circuit layer, and has an opening to expose a portion of the surface of the circuit layer.

The invention further provides a package structure for embedding a wafer, so that the circuit layer is directly electrically connected to the nail head bump without using a conductive blind hole.

According to the foregoing two package structures, the circuit layer may have a line and an electrical contact pad, and the surface of the dielectric layer has a line groove, so that the line is disposed in the line groove, so that the line is embedded in the dielectric And a layer of the electrical contact pad disposed on the surface of the dielectric layer such that a portion of the bottom surface of the electrical contact pad follows a portion of the top surface of the line. Alternatively, the circuit and the electrical contact pads are disposed in the circuit trench such that the circuit and the electrical contact pads are embedded in the dielectric layer.

As can be seen from the above, the package structure of the present invention is mainly packaged by embedding to embed the semiconductor wafer in the dielectric layer, and then using the stud bumps on the electrode pads of the semiconductor wafer as transmission signals. The component is used to shorten the distance of the signal transmission without using the gold wire of the prior art as the electrical conduction path, so that the overall structural height of the package structure can be reduced, and the thinning is achieved, and the nail head is The conduction path of the bump is much shorter than the gold wire of the prior art, which can improve the electrical effect.

In addition, according to the various package structure aspects of the present invention described above, the present invention provides a method for manufacturing each of the package structures, and the specific technical details thereof will be described later.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It should be noted that the structure, proportion and size depicted in the drawings of this specification And the like, which are used for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the invention, and thus do not have technical significance, any structural modification, The change of the proportional relationship or the adjustment of the size should be within the scope of the technical content disclosed by the present invention without affecting the effects and the achievable effects of the present invention. In the meantime, the terms "upper", "lower", "top", "bottom" and "one" are used in this specification for convenience of description and are not intended to limit the invention. The scope, the change or adjustment of the relative relationship, is also considered to be within the scope of the invention.

First embodiment

Please refer to FIGS. 2A to 2H, which are cross-sectional views showing the manufacturing method of the package structure of the present invention.

As shown in FIG. 2A, a semiconductor wafer 20 having a side surface 20c, an opposite active surface 20a and an inactive surface 20b is provided. The semiconductor wafer 20 is, for example, a memory wafer, and the active surface 20a of the semiconductor wafer 20 has A plurality of electrode pads 200. In this embodiment, the active surface 20a of the semiconductor wafer 20 has a first protective layer 201 and a second protective layer 202, and the first and second protective layers 201, 202 are formed with a plurality of small holes to expose the respective The material of the electrode pad 200 and the second protective layer 202 may be polyimide.

As shown in FIG. 2B, a stud bump 21 is formed on each of the electrode pads 200. In this embodiment, the stud bumps 21 are made of gold or copper, and may also be formed on each of the stud bumps 21 as shown in FIG. 2B'. Surface treatment layer 210 of Pd/Cu, Ti/W/Cu or Organic Solderability Preservative (OSP).

As shown in FIGS. 2C and 2D, a carrier 22 having an adhesive layer 221 is provided, and a first dielectric plate 23a having a through opening 230a is formed on the adhesive layer 221, and the adhesive layer 221 is covered thereon. The lower side of the opening 230a.

Next, the semiconductor wafer 20 is received in the opening 230a of the first dielectric plate 23a, and the non-active surface 20b of the semiconductor wafer 20 is bonded to the adhesive layer 221 of the carrier plate 22.

And pressing a second dielectric plate 23b on the first dielectric plate 23a and the semiconductor wafer 20 to bond the first and second dielectric plates 23a, 23b into a dielectric layer 23 to cover the semiconductor wafer. The action surface 20a and the side surface 20c of the 20, and the nail head bump 21.

As shown in FIG. 2E, a plurality of blind vias 230 are formed on the dielectric layer 23 to correspondingly expose the respective stud bumps 21.

As shown in FIG. 2F, a circuit layer 24 is formed on the dielectric layer 23, and the circuit layer 24 has a plurality of lines 24a, a plurality of electrical contact pads 241 electrically connected to the line 24a, and a blind hole formed therein. The conductive blind vias 240 are electrically connected to the stud bumps 21 and the circuit layer 24 by the conductive vias 240.

As shown in FIG. 2G, an insulating protective layer 25 is formed on the dielectric layer 23 and the circuit layer 24. The insulating protective layer 25 is formed with a plurality of openings 250, so that the electrical contact pads 241 are exposed to each other. The opening 250.

Then, the carrier board 22 and the adhesive layer 221 are removed, and the half is exposed. The non-active surface 20b of the conductor wafer 20.

As shown in FIG. 2H, a heat sink 26 may be disposed on the exposed non-active surface 20b of the semiconductor wafer 20 as needed.

The method for fabricating the package structure of the present invention is to embed the semiconductor wafer 20 in the dielectric layer 23, and then use the stud bump 21 as a component for transmitting signals to shorten the distance of signal transmission instead of using conventional techniques. The gold wire is used as an electrical conduction path, so the invention can not only reduce the overall structural height of the package structure, but also improve the electrical efficiency because the conduction path of the nail head bump 21 is much shorter than the gold wire of the prior art. For example, the quality of the inductor and capacitor to facilitate the increase in the bandwidth of the memory.

Further, in the manufacturing method of the present invention, since the wire bonding method is not required, the use of the gold material can be reduced, and the manufacturing cost can be reduced.

Second embodiment

Please refer to FIG. 3A to FIG. 3F. The difference between this embodiment and the first embodiment is mainly in the formation of the circuit layer. The related processes of other package structures are substantially the same, and therefore will not be described again.

As shown in FIG. 3A, as in the structure of FIG. 2D, a dielectric layer 33 is formed on the carrier 22 and the semiconductor wafer 20 to cover each of the stud bumps 21.

As shown in FIG. 3B, a plurality of line grooves 331 are formed on the surface of the dielectric layer 33, so that the blind holes 330 communicate with the bottom portion 331a of the line groove 331.

As shown in FIG. 3C, a line 34a is formed in the line trench 331 so that the line 34a is embedded in the dielectric layer 33, and the top surface of the line 34a is exposed on the surface of the dielectric layer 33, and at the same time Forming a conductive blind hole in the blind hole 330 340.

In this embodiment, the line 34a and the conductive blind hole 340 may have a connection pad 34b as shown in FIG. 3C(a); or the line 34a' may be directly formed on the end surface of the conductive blind hole 340. There is no connection pad, as shown in Figure 3C(b).

As shown in FIGS. 3D and 3D', a plurality of electrical contact pads 341 are formed on the surface of the dielectric layer 33 such that a portion of the bottom surface of the electrical contact pads 341 follows a portion of the top surface of the line 34a to form the circuit layer 34. .

As shown in FIG. 3E, an insulating protective layer 25 is formed on the dielectric layer 33 and the circuit layer 34. The insulating protective layer 25 has a plurality of openings 250, so that the electrical contact pads 341 are correspondingly exposed to the openings. 250.

Next, the carrier 22 and the adhesive layer 221 are removed, and the non-active surface 20b of the semiconductor wafer 20 is exposed.

As shown in FIG. 3F, a heat sink 26 may be disposed on the exposed non-active surface 20b for heat dissipation of the semiconductor wafer 20 as needed.

Third embodiment

Please refer to FIG. 4A to FIG. 4D. The difference between this embodiment and the second embodiment is mainly in the formation of the electrical contact pads. The related processes of other package structures are substantially the same, and therefore will not be described again.

As shown in FIG. 4A, a line groove 431 is formed on the surface of the dielectric layer 43 so that the blind hole 430 communicates with the bottom portion 431a of the line groove 431.

As shown in FIGS. 4B and 4B', a conductive via hole 440 is formed in the blind via 430, and a line 44a and an electrical contact pad 441 are formed in the line trench 431 to form the circuit layer 44, so that the line 44a and Electrical contact pad 441 The top surface of the line 44a and the top surface of the electrical contact pad 441 are exposed on the surface of the dielectric layer 43.

As shown in FIG. 4C, an insulating protective layer 25 is formed on the dielectric layer 43 and the wiring layer 44. The insulating protective layer 25 has a plurality of openings 250, so that each of the electrical contact pads 441 is exposed to each of the openings. 250.

Next, the carrier 22 and the adhesive layer 221 are removed, and the non-active surface 20b of the semiconductor wafer 20 is exposed.

As shown in FIG. 4D, a heat sink 26 may be disposed on the exposed non-active surface 20b for heat dissipation of the semiconductor wafer 20 as needed.

According to the method of the first to third embodiments, the present invention can be fabricated into a package structure comprising: a semiconductor wafer 20 having an opposite active surface 20a and a non-active surface 20b, and a nail disposed on the semiconductor wafer 20. a bump 21, a dielectric layer 23, 33, 43 covering the head bump 21, circuit layers 24, 34, 44 disposed on the dielectric layer 23, 33, 43 and a dielectric layer Layers 23, 33, 43 and insulating protective layer 25 on circuit layers 24, 34, 44.

The active surface 20a of the semiconductor wafer 20 has a plurality of electrode pads 200 for bonding the stud bumps 21.

The dielectric layers 23, 33, 43 also cover the active surface 20a and the side surface 20c of the semiconductor wafer 20, and expose the non-active surface 20b.

The circuit layers 24, 34, 44 have a plurality of lines 24a, 34a, 44a, electrical contact pads 241, 341, 441 electrically connected to the lines 24a, 34a, 44a, and in the dielectric layers 23, 33, 43 The conductive blind holes 240, 340, 440 of the nail head bumps 21 are electrically connected.

The insulating protective layer 25 has a plurality of openings 250 for each of the electricity The contact pads 241, 341, 441 are correspondingly exposed to the openings 250.

Fourth embodiment

Please refer to FIG. 5A to FIG. 5C. The difference between this embodiment and the first embodiment is mainly that the circuit layer does not have conductive blind holes, and the related processes of other package structures are substantially the same, and therefore will not be described again.

As shown in FIG. 5A, the process of the 2D drawing is continued, that is, a dielectric layer 53 is formed by pressing, and the surface of the dielectric layer 53 is lower than the top surface of the stud bump 21, and the nail head is exposed. Part of the surface of the bump 21.

As shown in FIG. 5B, a wiring layer 54 is formed on the dielectric layer 53 and the stud bump 21 to electrically connect the stud bump 21, and the circuit layer 54 has a plurality of lines 54a and a plurality of electrical properties. The electrical contact pads 541 of the line 54a are connected.

As shown in FIG. 5C, an insulating protective layer 25 is formed on the dielectric layer 53 and the wiring layer 54. The insulating protective layer 25 has a plurality of openings 250, so that the electrical contact pads 541 are correspondingly exposed to the openings. 250. Next, the carrier 22 and the adhesive layer 221 are removed, and the non-active surface 20b of the semiconductor wafer 20 is exposed.

Fifth embodiment

Please refer to FIG. 6A to FIG. 6D. The difference between this embodiment and the fourth embodiment is mainly in the formation of the circuit layer. The related processes of other package structures are substantially the same, and therefore will not be described again.

As shown in FIG. 6A, a plurality of line grooves 631 are formed on the dielectric layer 63. The surface of the bottom portion 631a of the line groove 631 is lower than the top surface of the stud bump 21, and the portion of the stud bump 21 is exposed. surface.

As shown in FIG. 6B, a line 64a is formed in the line groove 631, and the line 64a is embedded in the dielectric layer 63 and electrically connected to the nail head bump 21, and the top surface of the line 64a is exposed to the line 64a. The surface of the dielectric layer 63.

As shown in FIG. 6C, an electrical contact pad 641 is formed on the surface of the dielectric layer 63 such that a portion of the bottom surface of the electrical contact pad 641 follows a portion of the top surface of the line 64a to form a circuit layer 64 (refer to The circuit layer 34 of the second embodiment differs only in the presence or absence of the conductive blind via).

As shown in FIG. 6D, an insulating protective layer 25 is formed on the dielectric layer 63 and the circuit layer 64. The insulating protective layer 25 has a plurality of openings 250, so that the electrical contact pads 641 are correspondingly exposed to the openings. 250. Next, the carrier 22 and the adhesive layer 221 are removed, and the non-active surface 20b of the semiconductor wafer 20 is exposed.

Sixth embodiment

Please refer to FIGS. 7A-7C. The difference between this embodiment and the fifth embodiment lies mainly in the formation of the electrical contact pads. The related processes of other package structures are substantially the same, and therefore will not be described again.

As shown in FIG. 7A, a plurality of line grooves 731 are formed on the dielectric layer 73. The surface of the bottom portion 731a of the line groove 731 is lower than the top surface of the nail head bump 21, and the nail head bump 21 is exposed. Part of the surface.

As shown in FIG. 7B, a wiring 74a and an electrical contact pad 741 are formed in the wiring trench 731 to form a wiring layer 74, and the wiring layer 74 is embedded in the dielectric layer 73, and the top surface of the wiring 74a is formed. The top surface of the electrical contact pad 741 is exposed on the surface of the dielectric layer 73.

Formed on the dielectric layer 73 and the wiring layer 74 as shown in FIG. 7C The insulating protective layer 25 has a plurality of openings 250, so that the electrical contact pads 741 are correspondingly exposed to the openings 250. Next, the carrier 22 and the adhesive layer 221 are removed, and the non-active surface 20b of the semiconductor wafer 20 is exposed.

According to the method of the fourth to sixth embodiments, the present invention can be fabricated into another package structure, comprising: a semiconductor wafer 20 having an opposite active surface 20a and an inactive surface 20b, disposed on the semiconductor wafer 20. a stud bump 21, dielectric layers 53, 63, 73 covering the stud bumps 21, circuit layers 54, 64, 74 disposed on the dielectric layers 53, 63, 73, and The electrical layers 53, 63, 73 and the insulating protective layer 25 on the wiring layers 54, 64, 74.

The active surface 20a of the semiconductor wafer 20 has a plurality of electrode pads 200 for bonding the stud bumps 21.

The dielectric layers 53, 63, 73 also cover the active surface 20a and the side surface 20c of the semiconductor wafer 20, and expose the non-active surface 20b.

The circuit layers 54, 64, 74 have a plurality of lines 54a, 64a, 74a, and electrical contact pads 541, 641, 741 electrically coupled to the lines 54a, 64a, 74a.

The insulating protective layer 25 has a plurality of openings 250, so that the electrical contact pads 541, 641, 741 are correspondingly exposed to the openings 250.

In summary, the package structure of the present invention is formed by embedding the semiconductor wafer in the carrier plate and electrically connecting the circuit layer and the semiconductor wafer with the stud bumps, thereby not only reducing the package structure. The overall structure height is achieved, and the purpose of thinning is achieved, and the electrical effect is improved by shortening the distance of signal transmission.

Furthermore, in the manufacturing method of the present invention, since the wire bonding method is not required, the material cost can be reduced.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

1‧‧‧Package structure

10‧‧‧Package substrate

10a‧‧‧ upper surface

10b‧‧‧ lower surface

100,230a‧‧‧ openings

101‧‧‧Line mat

102‧‧‧Ball mat

11,20‧‧‧Semiconductor wafer

11a, 20a‧‧‧ action surface

11b, 20b‧‧‧ non-active surface

110,200‧‧‧electrode pads

12‧‧‧ Gold Line

13‧‧‧Package colloid

14‧‧‧Protective materials

16‧‧‧ solder balls

20c‧‧‧ side

201‧‧‧First protective layer

202‧‧‧Second protective layer

21‧‧‧nail head bumps

210‧‧‧Surface treatment layer

22‧‧‧Loading board

221‧‧‧Adhesive layer

23,33,43,53,63,73‧‧‧ dielectric layer

23a‧‧‧First dielectric board

23b‧‧‧Second dielectric board

230,330,430‧‧‧blind holes

24, 34, 44, 54, 64, 74‧‧‧ circuit layer

24a, 34a, 34a', 44a, 54a, 64a, 74a ‧ ‧ lines

240,340,440‧‧‧ conductive blind holes

241,341,441,541,641,741‧‧‧Electrical contact pads

25‧‧‧Insulating protective layer

250‧‧‧ openings

26‧‧‧ Heat sink

331,431,631,731‧‧‧Line slot

331a, 431a, 631a, 731a‧‧‧ bottom

34b‧‧‧Connecting mat

1A is a cross-sectional view showing a conventional memory package structure; and FIGS. 2A to 2H are cross-sectional views showing a first embodiment of a method for fabricating a package structure of the present invention; wherein, the 2B' is a 2B Another embodiment; 3A to 3F are schematic cross-sectional views showing a second embodiment of the method for fabricating a package structure of the present invention; wherein, the 3C (a) and 3C (b) diagrams are different states of the 3C diagram. a partial top view, a 3D' diagram is a partial top view of the 3D diagram; and 4A to 4D are schematic cross-sectional views of a third embodiment of the method of fabricating the package structure of the present invention; wherein, the 4B' diagram 4A to 5C are schematic cross-sectional views showing a fourth embodiment of the method for fabricating the package structure of the present invention; and FIGS. 6A to 6D are diagrams showing a fifth embodiment of the method for fabricating the package structure of the present invention; A schematic cross-sectional view; and 7A to 7C are the sixth implementation of the method for fabricating the package structure of the present invention A schematic cross-sectional view of an example.

20‧‧‧Semiconductor wafer

20a‧‧‧Action surface

20b‧‧‧Non-active surface

200‧‧‧electrode pads

21‧‧‧nail head bumps

23‧‧‧Dielectric layer

24‧‧‧Line layer

24a‧‧‧ lines

240‧‧‧conductive blind holes

241‧‧‧Electrical contact pads

25‧‧‧Insulating protective layer

250‧‧‧ openings

Claims (20)

A package structure includes: a semiconductor wafer having opposite active and non-active surfaces, the active surface having a plurality of electrode pads; a nail head bump disposed on the electrode pad, and the size of the nail head bump Is smaller than the size of the electrode pad; the dielectric layer covers the active surface and the side surface of the semiconductor wafer, and the stud bump, and exposes the non-active surface of the semiconductor wafer; the circuit layer is disposed on the dielectric layer And an electrical contact pad having a plurality of lines, a plurality of electrically connecting the lines, and a conductive blind hole disposed in the dielectric layer to electrically connect the stud bumps; and an insulating protective layer is disposed on the layer The dielectric layer and the circuit layer have a plurality of openings, so that each of the electrical contact pads is exposed to each of the openings. The package structure of claim 1, wherein the nail head bump is provided with a surface treatment layer. The package structure of claim 1, wherein the surface of the dielectric layer has a line groove, the line is disposed in the line groove, the line is embedded in the dielectric layer, and the top of the line The surface is exposed on the surface of the dielectric layer, and the electrical contact pad is disposed on the surface of the dielectric layer such that a portion of the bottom surface of the electrical contact pad follows a portion of the top surface of the line. The package structure of claim 1, wherein the surface of the dielectric layer has a line groove, and the circuit and the electrical contact pad are disposed in the circuit groove, so that the circuit layer is embedded in the dielectric layer. And the top surface of the line and the top surface of the electrical contact pad are exposed on the surface of the dielectric layer. The package structure as described in claim 1 further comprises a heat sink disposed on the exposed non-active surface of the semiconductor wafer. A package structure includes: a semiconductor wafer having opposite active and non-active surfaces, the active surface having a plurality of electrode pads; a nail head bump disposed on the electrode pad, and the size of the nail head bump The size is smaller than the size of the electrode pad; the dielectric layer covers the active surface and the side surface of the semiconductor wafer, and the stud bump, and the dielectric layer exposes a portion of the top surface of the stud bump, and the semiconductor wafer The non-active surface is exposed on the surface of the dielectric layer; the circuit layer is disposed on the dielectric layer and the stud bump, and is electrically connected to the stud bump, and the circuit layer has a plurality of lines and plural An electrical contact pad electrically connected to the line; and an insulating protective layer disposed on the dielectric layer and the circuit layer, and having a plurality of openings, wherein each of the electrical contact pads is correspondingly exposed to each of the openings. The package structure of claim 6, wherein the nail head bump is provided with a surface treatment layer. The package structure of claim 6, wherein the surface of the dielectric layer has a line groove, a bottom surface of the line groove is lower than a top surface of the nail head bump, and the line is disposed in the circuit groove. The circuit is embedded in the dielectric layer, and the top surface of the circuit is exposed on the surface of the dielectric layer, and the electrical contact pad is disposed on the surface of the dielectric layer to partially bottom the electrical contact pad. Then part of the top surface of the line. The package structure of claim 6, wherein the dielectric The surface of the layer has a line groove, the bottom surface of the line groove is lower than the top surface of the stud bump, and the line and the electrical contact pad are disposed in the circuit groove, so that the circuit layer is embedded in the dielectric layer. The top surface of the line and the top surface of the electrical contact pad are exposed on the surface of the dielectric layer. The package structure as claimed in claim 6 further comprising a heat sink disposed on the exposed non-active surface of the semiconductor wafer. A method for fabricating a package structure includes: providing a semiconductor wafer having opposite active and non-active surfaces, and having a plurality of electrode pads on the active surface of the semiconductor wafer; forming a stud bump on the electrode pad; a first dielectric plate having an opening is formed on the carrier layer of the adhesive layer, the adhesive layer is covered on one side of the opening, the semiconductor wafer is received in the opening, and the non-active surface is bonded to the adhesive layer; The second dielectric plate is pressed onto the first dielectric plate and the semiconductor wafer to cover the semiconductor wafer and the stud bump, and the first and second dielectric plates are combined to form a dielectric layer; Forming a plurality of blind vias on the layer to expose the stud bumps; forming a circuit layer having a plurality of lines and a plurality of electrical contact pads electrically connected to the lines on the dielectric layer, and the circuit layer is in the blind vias Forming a conductive blind via to electrically connect the stud bump; forming an insulating protective layer on the dielectric layer and the circuit layer, the insulating protective layer having a plurality of openings, so that each of the electrical contact pads is exposed to each of the Opening; and The carrier plate and the adhesive layer are removed to expose the inactive surface of the semiconductor wafer. The method of fabricating a package structure according to claim 11, wherein a surface treatment layer is formed on the nail head bump. The method for manufacturing a package structure according to claim 11, further comprising forming a circuit groove on a surface of the dielectric layer, wherein the blind hole communicates with a bottom of the circuit groove, and the circuit is formed in the circuit groove, The circuit is embedded in the dielectric layer, and the top surface of the circuit is exposed on the surface of the dielectric layer, and the electrical contact pad is formed on the surface of the dielectric layer, so that a part of the bottom surface of the electrical contact pad follows Part of the top of the line. The method for manufacturing a package structure according to claim 11, further comprising forming a line groove on a surface of the dielectric layer, the blind hole is connected to a bottom of the circuit groove, and the circuit and the electrical contact pad are formed on the circuit In the circuit trench, the circuit layer is embedded in the dielectric layer, and the top surface of the circuit and the top surface of the electrical contact pad are exposed on the surface of the dielectric layer. The method for manufacturing a package structure according to claim 11 is characterized in that the heat sink is disposed on the exposed non-active surface of the semiconductor wafer. A method for fabricating a package structure includes: providing a semiconductor wafer having opposite active and non-active surfaces, and having a plurality of electrode pads on the active surface of the semiconductor wafer; forming a stud bump on the electrode pad; Forming a first dielectric plate having an opening on the carrier layer of the adhesive layer, the adhesive layer covering one side of the opening, the semiconductor wafer being received in the opening, and the non-active surface being bonded to the adhesive layer Pressing a second dielectric plate on the first dielectric plate and the semiconductor wafer to cover the semiconductor wafer and the stud bump, and the first and second dielectric plates are combined to form a dielectric layer, and The dielectric layer exposes a portion of the surface of the stud bump; a circuit layer is formed on the dielectric layer and the stud bump to electrically connect the stud bump, and the circuit layer has a plurality of lines and a plurality of wires An electrical contact pad electrically connected to the circuit; forming an insulating protective layer on the dielectric layer and the circuit layer, the insulating protective layer having a plurality of openings, so that each of the electrical contact pads is exposed to each of the openings; Except for the carrier plate and the adhesive layer, the inactive surface of the semiconductor wafer is exposed. The method of fabricating a package structure according to claim 16, wherein a surface treatment layer is formed on the nail head bump. The method for manufacturing a package structure according to claim 16, further comprising forming a circuit trench on the dielectric layer, a bottom surface of the trench is lower than a top surface of the stud bump, and the circuit is formed on the circuit In the circuit trench, the circuit is embedded in the dielectric layer, and the top surface of the circuit is exposed on the surface of the dielectric layer, and the electrical contact pad is formed on the surface of the dielectric layer, so that the electrical contact pad A portion of the bottom surface is followed by a portion of the top surface of the line. The method for manufacturing a package structure according to claim 16 is characterized in that the circuit layer is formed on the dielectric layer, and a bottom surface of the circuit groove is lower than a top surface of the nail head bump, and the line and the electrical property are Contact pads formed on the line In the channel, the circuit layer is embedded in the dielectric layer, and the top surface of the circuit and the top surface of the electrical contact pad are exposed on the surface of the dielectric layer. The method for manufacturing a package structure according to claim 16 is characterized in that the heat sink is disposed on the exposed non-active surface of the semiconductor wafer.