TWI884862B - Package structure - Google Patents

Abstract

A packaging structure including a chip, a dielectric component, and a redistribution circuit layer structure is provided. The chip includes a semiconductor substrate and a chip connector disposed on the semiconductor substrate. The dielectric component is at least disposed on the chip. The redistribution circuit layer structure is disposed on the chip and dielectric component. The direct contact point of the chip connector, the dielectric component, and the redistribution circuit layer structure is located on a portion of a outer planar surface of the chip connector.

Description

Package structure

The present invention relates to a package structure, and in particular to a package structure comprising at least a chip and a corresponding dielectric body.

Modern electronic devices often include corresponding chips. In the manufacturing process of electronic devices, it is often necessary to package the corresponding chips and connect the terminals of the chips to the corresponding circuits.

With the improvement of chip manufacturing technology, the number and/or density of chip terminals may increase. Therefore, in the manufacturing process of electronic devices, the subsequent packaging process and/or the corresponding circuit connection process are becoming more and more complicated. Therefore, how to make the overall manufacturing method simpler and/or have a higher yield has become a research topic.

The present invention provides a packaging structure which is simpler to manufacture and/or has a higher yield.

The package structure of the present invention includes a chip, a dielectric and a redistribution wiring layer structure. The chip includes a semiconductor substrate and a chip connector located on the semiconductor substrate. The dielectric is at least located on the chip. The redistribution wiring layer structure is located on the chip and the dielectric. The chip connector, the dielectric and the redistribution wiring layer structure are directly in contact with each other in a portion of the outer plane surface of the chip connector.

The package structure includes a chip, a dielectric and a redistribution wiring layer structure. The chip includes a semiconductor substrate and a chip connector located on the semiconductor substrate. The dielectric is at least located on the chip. The redistribution wiring layer structure is located on the chip and the dielectric. The chip connector, the dielectric and the redistribution wiring layer structure are directly in contact with each other and are far away from and/or not located at the edge of the outer plane of the chip connector on which they are located.

Based on the above, the manufacturing of the package structure is simpler and/or has a higher yield.

Directional terms (e.g., up, down, top, bottom) used herein are used only as reference to the drawings and are not intended to imply an absolute orientation. In addition, for the sake of clarity, some layers or components may be omitted in the drawings.

Unless otherwise expressly stated, it is in no way intended that any method described herein be construed as requiring that its steps be performed in a specific order.

The present invention is more fully described with reference to the drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness, size or size of the layers or regions in the drawings may be exaggerated for clarity. The same or similar reference numbers represent the same or similar elements, and the following paragraphs will not be repeated one by one.

1A to 1I are partial cross-sectional schematic diagrams of a partial manufacturing method of a package structure according to the first embodiment of the present invention. FIG1J and FIG1K are partial cross-sectional schematic diagrams of a package structure according to the first embodiment of the present invention. For example, FIG1K may be an enlarged view corresponding to region R1 in FIG1J.

1A , a chip 110 is provided. It should be noted that only two chips 110 are shown in FIG1A exemplarily, but the present invention does not limit the number, type and/or arrangement of the chips 110 provided.

In one embodiment, the chip 110 may be disposed on a carrier 91. The carrier 91 may be made of glass, a wafer substrate, metal or other suitable materials, as long as the aforementioned materials can support the structure or components formed thereon in the subsequent manufacturing process.

In one embodiment, a release layer 92 may be formed on the carrier 91. The release layer 92 may include a light to heat conversion (LTHC) adhesive layer, but the present invention is not limited thereto.

In a possible embodiment (as described below, but not limited to), the carrier 91 may have other components (such as heat sinks, EMI shielding components). The aforementioned components may be located between the chip 110 and the carrier 91. The aforementioned components may be in direct contact with the chip 110. The aforementioned components may be in indirect contact with the chip 110; for example, a corresponding adhesive layer (such as a die attach film (DAF)) may be provided between the aforementioned components and the chip 110.

In this embodiment, the chip 110 may include a substrate 111, a plurality of connection pads 112, and a plurality of chip connectors 115. The substrate 111 may be a semiconductor substrate (e.g., a silicon substrate). One side of the substrate 111 has a component region (not shown), and the surface where the component region is located may be referred to as an active surface 110a. The connection pads 112 may be located on the active surface 110a. The chip connectors 115 may be located on the connection pads 112. In a general chip 110 design, components in the component region (e.g., components in the component region of the chip 110) can be electrically connected to corresponding connection pads 112 (e.g., part of the connection pads 112 of the chip 110) and corresponding chip connectors 115 (e.g., part of the chip connectors 115 of the chip 110) through corresponding back-end metal interconnects (BEOL Interconnect). In addition, for the sake of clarity, not all components are marked one by one in FIG. 1A or other similar figures (e.g., not all connection pads 112 or all chip connectors 115 are marked one by one).

In this embodiment, the connection pad 112 is, for example, an aluminum pad or a copper pad, but the present invention is not limited thereto.

In one embodiment, the connection pad 112 may be partially covered by the insulating layer 113 , and the insulating layer 113 may expose a portion of the connection pad 112 .

In one embodiment, a passivation layer 114 may cover the insulating layer 113 , and the passivation layer 114 may expose a portion of the connecting pad 112 .

In one embodiment, the chip connector 115 may include a conductive pillar or a conductive bump.

In one embodiment, the chip connector 115 can be formed by a lithography process, a sputtering process, an electroplating process and/or an etching process, but the present invention is not limited thereto. For example, the chip connector 115 can include a first conductive layer 115s (marked in FIG. 1K) and a second conductive layer 115p (marked in FIG. 1K) located on the first conductive layer 115s, but the present invention is not limited thereto. In a top view, the patterns of the first conductive layer 115s and the second conductive layer 115p are substantially the same. In one embodiment, the first conductive layer 115s can be referred to as a seed layer. In one embodiment, the second conductive layer 115p can be referred to as a plating layer.

In an embodiment not shown, the chip connector (e.g., a chip connector similar to chip connector 115) may include a pre-formed conductive member. For example, the chip connector may include a pre-formed conductive pillar, but the present invention is not limited thereto.

In one embodiment, the chip connector 115 may correspond to an input/output terminal (I/O terminal), a power terminal, or a ground terminal of the chip 110 .

1B and 1C , a dielectric 130 (indicated in FIG. 1C ) is formed to cover the chip 110 . The dielectric 130 may expose a portion of the chip 110 . For example, the dielectric 130 may expose the chip connector 115 of the chip 110 .

In this embodiment, the steps of forming the dielectric 130 are exemplified as follows.

Referring to FIG. 1B , a dielectric material 139 covering the chip 110 may be formed. In one embodiment, the dielectric material 139 is formed on the carrier 91 by, for example, a molding process, a coating process, or other suitable methods. Then, the gel-like or molten high molecular polymer is solidified or semi-solidified. In one embodiment, the chip 110 may not be exposed outside the dielectric material 139, but the present invention is not limited thereto.

In one embodiment, the dielectric material 139 is, for example, a molding compound, which may include but is not limited to epoxy.

Referring to FIG. 1C , after forming the dielectric material 139 (indicated in FIG. 1B ), a portion of the dielectric material 139 (indicated in FIG. 1B ) may be removed to form a dielectric body 130 (indicated in FIG. 1C ) that laterally covers the chip 110 , and the dielectric body 130 may expose the top surface 115 a of the chip connector 115 and a portion of the side surface 115 c close to the top surface 115 a. In other words, a portion of the dielectric body 130 near the chip connector 115 is more concave than the chip connector 115 .

In one embodiment, a thinning process may be performed first to remove a portion of the dielectric material 139 (as shown in FIG. 1B ); then, a suitable etching process may be performed to expose a portion of the side surface 115 c of the chip connector 115 .

In one embodiment, the aforementioned thinning process includes, for example, chemical mechanical polishing (CMP), mechanical grinding, etching or other appropriate processes, but the present invention is not limited thereto.

In one embodiment, after the aforementioned thinning process and before the aforementioned etching process, the top surface 115a of the chip connector 115 and the top surface of the thinned dielectric material 139 may be substantially coplanar.

In one embodiment, the aforementioned etching process includes, for example, a dry etching process, a wet etching process or other appropriate processes.

In one embodiment, the aforementioned dry etching process may include, for example, an appropriate ashing process, a surface ablation process, or other appropriate processes, but the present invention is not limited thereto. The aforementioned ashing process may include a plasma ashing process, and/or the aforementioned surface ablation process may include a laser ablation process, but the present invention is not limited thereto. In a possible embodiment, taking the dielectric material 139 as an example, including a polymer (such as epoxy), after the aforementioned dry etching process, the carbon concentration of the region close to the top surface 130a of the formed dielectric 130 may be greater than the carbon concentration of the region far from the top surface 130a. In a possible embodiment, a region of the dielectric body 130 close to the top surface 130a may be embedded with corresponding carbon particles or carbon residues; and/or corresponding carbon particles or carbon residues may be present on the top surface 130a of the dielectric body 130.

In one embodiment, the etchant used in the wet etching process can be appropriately selected according to the properties of the dielectric material 139. For example, for epoxy, methyl ethyl ketone (MEK) may be used as the etchant. For example, for polyimide (PI), lactam may be used as the etchant.

In one embodiment, a distance S35 (indicated in FIG. 1K ) between the top surface 115 a of the chip connector 115 and the top surface 130 a of the dielectric 130 may be approximately 0.5 micrometers (µm) to 2 micrometers.

In one embodiment, the aforementioned etching process will not substantially affect the outer surface of the chip connector 115 (eg, the top surface 115a or the exposed portion of the side surface 115c).

In one embodiment, the roughness of the top surface 115a of the chip connector 115 may be different from the roughness of the top surface 130a of the dielectric 130. In one embodiment, the top surface 130a of the dielectric 130 is rougher than the top surface 115a of the chip connector 115; that is, the roughness of the top surface 130a of the dielectric 130 is greater than the roughness of the top surface 115a of the chip connector 115.

In a possible embodiment, a portion of the dielectric material 139 (as shown in FIG. 1B ) may be directly removed by the aforementioned etching process to form a dielectric body 130 (as shown in FIG. 1C ) that laterally covers the chip 110 .

1C to 1D , an insulating layer 151 may be formed on the chip connector 115 and the dielectric 130 of the chip 110 by coating, laminating, deposition or other appropriate methods. The material of the insulating layer 151 may include an organic material (e.g., polyimide) or an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, other appropriate materials, or a stacked layer of at least two of the above inorganic materials).

Referring to FIG. 1D to FIG. 1E , an insulating opening 151 d exposing the chip connector 115 can be formed by etching or other appropriate methods. It is worth noting that the insulating layer 151 in FIG. 1E and the insulating layer 151 in FIG. 1D are basically different only in the presence or absence of the insulating opening 151 d, so the same symbol is used to represent them. In addition, for the sake of clarity, not all insulating openings 151 d are marked one by one in FIG. 1D or other similar figures. In addition, the present invention does not limit each chip connector 115 to be exposed.

In one embodiment, the opening area of the insulating opening 151d may be smaller than the surface area of the top surface 115a of the chip connector 115. In other words, the insulating opening 151d does not substantially expose all of the top surface 115a.

In this embodiment, the insulating opening 151d may only expose the top surface 115a of the corresponding chip connector 115. In one embodiment (such as the embodiment described later or the cross-sectional area not shown in this embodiment), the opening deviation (such as the shift of the opening position, the change of the opening shape and/or the change of the opening size) may be caused due to misalignment (such as exposure misalignment and/or etching misalignment), over etching or other possible factors. However, since the part of the side surface 115c of the chip connector 115 close to the top surface 115a is not covered by the dielectric 130, even if there is the aforementioned opening deviation, the impact on the electrical properties can still be reduced (detailed as follows).

Please refer to Figures 1E to 1F. After forming an insulating layer 151 having an insulating opening 151d (marked in Figure 1E), a circuit layer 152 can be formed on the insulating layer 151. The circuit layer 152 can be formed by a lithography process, a sputtering process, an electroplating process and/or an etching process, but the present invention is not limited thereto. The layout design of the circuit layer 152 can be adjusted as required, and the present invention is not limited thereto. Part of the circuit layer 152 can be filled with the insulating opening 151d to be electrically connected to the chip connector 115. The part of the circuit layer 152 filled with the insulating opening 151d can be called a conductive via.

In one embodiment, the circuit layer 152 may include a first conductive layer 152s (shown in FIG. 1K ) and a second conductive layer 152p (shown in FIG. 1K ) located on the first conductive layer 152s, but the present invention is not limited thereto. In a top view, the patterns of the first conductive layer 152s and the second conductive layer 152p are substantially the same. In one embodiment, the first conductive layer 152s may be referred to as a seed layer. In one embodiment, the second conductive layer 152p may be referred to as a cladding layer.

In this embodiment, the portion of the circuit layer 152 filled in the insulating opening 151d can directly contact the top surface 115a of the chip connector 115. For example, the portion of the first conductive layer 152s (marked in FIG. 1K) filled in the insulating opening 151d can directly contact the top surface 115a of the chip connector 115. In an embodiment (such as: the embodiment described later or the cross-sectional area not shown in this embodiment), if there is the aforementioned opening deviation phenomenon, the portion of the circuit layer 152 filled in the insulating opening 151d can more directly contact the portion of the side surface 115c of the chip connector 115 close to the top surface 115a. In this way, the impact on electrical properties can be reduced. That is, a larger process window may be provided, so that the manufacturing of the package structure 100 (shown in FIG. 1J ) may be simpler and/or have a higher yield.

Referring to FIG. 1F to FIG. 1G , in one embodiment, a corresponding insulating layer 153 and/or a corresponding circuit layer 154 may be formed on at least the chip 110 according to design requirements. The insulating layer 153 may be formed in the same or similar manner as the aforementioned insulating layer 151. The circuit layer 154 may be formed in the same or similar manner as the aforementioned circuit layer 152. In addition, the present invention does not limit the number of insulating layers 153 and/or circuit layers 154.

In one embodiment, the insulating layer 151, the wiring layer 152, the insulating layer 153 and/or the wiring layer 154 may be referred to as a redistribution layer structure (RDL structure) 150. The chip 110 may be electrically connected to corresponding circuits in the RDL structure 150 via its corresponding chip connector 115.

In one embodiment, the redistribution wiring layer structure 150 may be a fan-out redistribution wiring layer structure (fan out RDL structure). In an embodiment not shown, the redistribution wiring layer structure 150 may be a fan-in redistribution wiring layer structure (fan in RDL structure).

1G to 1H, the carrier 91 and the structure thereon are separated from each other. For example, the bonding force of the release layer 92 (or any) can be reduced by light, heat or other appropriate means, and the carrier 91 and the structure thereon can be separated from each other by applying force.

1H to 1I, a plurality of conductive terminals 181 may be formed on the circuit layer 154 (which may be a part of the redistribution circuit layer structure 150). The conductive terminals 181 may be electrically connected to the chip 110 via corresponding circuits in the redistribution circuit layer structure 150. In addition, for the sake of clarity, not all conductive terminals 181 are marked one by one in FIG. 1I or other similar figures.

The conductive terminal 181 may be a conductive pillar, a solder ball, a conductive bump, or a conductive terminal having other forms or shapes. The conductive terminal 181 may be formed by electroplating, deposition, ball placement, reflow, and/or other appropriate processes.

1I , in this embodiment, a plurality of package structures 100 may be formed through a singulation process. The singulation process may include, for example, a dicing process (cutting process) to cut through the dielectric 130 and/or the redistribution wiring layer structure 150 .

It is worth noting that after the singulation process, similar component symbols will be used for the singulated components. For example, the chip 110 (as shown in FIG. 1H) can be the chip 110 (as shown in FIG. 1I) after singulation, the dielectric 130 (as shown in FIG. 1H) can be the dielectric 130 (as shown in FIG. 1I) after singulation, the redistribution wiring layer structure 150 (as shown in FIG. 1H) can be the redistribution wiring layer structure 150 (as shown in FIG. 1I) after singulation, and the plurality of conductive terminals 181 (as shown in FIG. 1H) can be the plurality of conductive terminals 181 (as shown in FIG. 1I) after singulation, and so on. Other singulated components will follow the same component symbol rules as described above and will not be elaborated or specifically illustrated here.

It is worth noting that the present invention does not limit the order of removing the carrier 91 (if any), configuring the plurality of conductive terminals 181 and the unitization process (if necessary).

After the above steps, the manufacturing of the packaging structure 100 of this embodiment can be substantially completed.

1J and 1K , the package structure 100 includes a chip 110 and a dielectric body 130 . The chip 110 includes a chip connector 115 . The dielectric body 130 is at least located on the chip 110 .

In the present embodiment, the chip connector 115 may be located on the active surface 110a of the chip 110. The chip connector 115 may have a top surface 115a and a side surface 115c connected to the top surface 115a. The dielectric 130 may be located at least on the active surface 110a of the chip 110. The dielectric 130 may not directly cover and/or directly contact a portion of the side surface 115c1 (i.e., a portion of the side surface 115c that is closer to the top surface 115a). The dielectric 130 may directly cover and/or directly contact the remaining portion of the side surface 115c2 (i.e., another portion of the side surface 115c that is farther from the top surface 115a). In one embodiment, the top surface 115a of the chip connector 115 may be substantially planar.

In this embodiment, when the package structure 100 is viewed in cross-section (such as shown in FIG. 1J and FIG. 1K ), the slopes of the side surfaces 115 c of the chip connector 115 are substantially the same. In one embodiment, the side surfaces 115 c of the chip connector 115 are substantially flat (such as an inclined plane or a vertical plane).

In the present embodiment, the chip 110 may further include a substrate 111. The substrate 111 may be a semiconductor substrate. The dielectric 130 may more directly cover and/or directly contact the side surface 111c of the substrate 111. In the thickness direction of the package structure 100, the top surface 115a of the chip connector 115 may be the outer surface of the chip connector 115 farthest from the substrate 111; and/or, the dielectric 130 may be substantially not located between the chip connector 115 and the substrate 111.

In this embodiment, the chip connector 115 may include a first conductive layer 115s and a second conductive layer 115p located on the first conductive layer 115s, and the first conductive layer 115s is located between the second conductive layer 115p and the substrate 111. In one embodiment, the dielectric 130 may laterally completely directly cover and/or laterally completely directly contact the first conductive layer 115s.

In this embodiment, the top surface 130a of the dielectric 130 may have a first top surface region 130a1, and the first top surface region 130a1 extends from the contact point P with the chip connector 115 in a direction away from the chip connector 115. There may be a distance S35 between the top surface 115a of the chip connector 115 and the first top surface region 130a1; and/or, the roughness of the first top surface region 130a1 is different from the roughness of the top surface 115a of the chip connector 115.

In this embodiment, the package structure 100 may further include a redistribution wiring layer structure 150. The redistribution wiring layer structure 150 may be located on the chip 110 and the dielectric 130. The direct contact point P between the redistribution wiring layer structure 150 (such as the bottom insulating layer 151), the chip connector 115 and the dielectric 130 may be located in a portion of the outer plane surface of the chip connector 115 (such as a portion of the side surface 115c). In other words, the contact point P is far away from and/or not located at the edge of the outer plane surface (such as the side surface 115c) where it is located. In other words, the contact point P is not located at or far away from the intersection of the side surface 115c and the top surface 115a. That is, there is a corresponding distance between the intersection of the side surface 115c and the top surface 115a and the contact point P. The outer plane surface where the contact point P is located may not be parallel to the top surface 111a of the substrate 111 or the active surface 110a of the chip 110.

In this embodiment, in the thickness direction of the package structure 100, at least part of the circuits in the redistribution circuit layer structure 150 do not overlap the chip 110; and/or, the distance S15 between the top surface 115a of the chip connector 115 and the substrate 111 is greater than the distance S13 between the contact point P and the substrate 111.

It is worth noting that on the cross-section (such as FIG. 1K or other similar diagrams), the contact points P are drawn as dots. However, in an actual three-dimensional object, the contact points P may be circular lines. In addition, on the cross-section (such as FIG. 1K or other similar diagrams), there may be multiple contact points P, but for the sake of simplicity, not all contact points P are marked one by one.

In one embodiment, in the thickness direction of the package structure 100, the carbon element concentration (e.g., molar ratio of carbon element) of the region A1 of the dielectric 130 close to the top surface 130a may be greater than the carbon element concentration of the region A2 far from the top surface 130a. The aforementioned carbon element concentration can be measured or observed by, for example, a commonly used elemental analysis method (e.g., energy-dispersive X-ray spectroscopy (EDX), but not limited thereto), but the present invention is not limited thereto.

In one embodiment, corresponding carbon particles or carbon residues may be present in the interface region A3 (in measurement, the region including the interface region; such as the region close to the top surface 130a in the dielectric 130; and/or on the top surface 130a of the dielectric 130) between the dielectric 130 and the redistribution wiring layer structure 150. The aforementioned carbon particles or carbon residues may be measured or observed, for example, by a scanning electron microscope (SEM), but the present invention is not limited thereto.

FIG2 is a partial cross-sectional schematic diagram of a package structure according to a second embodiment of the present invention. The package structure 200 and/or its manufacturing method of the second embodiment are similar to the package structure 100 and/or its manufacturing method of the first embodiment, and similar components or regions are represented by the same reference numerals, have similar functions, materials or formation methods, and descriptions thereof are omitted. For example, FIG2 may be a cross-sectional schematic diagram similar to region R1 in FIG1J.

2 , the package structure 200 includes a chip 110 and a dielectric body 230 . The dielectric body 230 is at least located on the chip 110 .

In this embodiment, the top surface 230a of the dielectric body 230 may have a first top surface region 230a1 and a second top surface region 230a2. The first top surface region 230a1 extends from a contact point P with the chip connector 115 toward a direction away from the chip connector 115. The second top surface region 230a2 is connected to the first top surface region 230a1. Furthermore, the first top surface region 230a1 gradually approaches the second top surface region 230a2 from the point P where the first top surface region 230a1 contacts the chip connector 115; and/or the vertical distance between the second top surface region 230a2 (or the virtual surface extending therefrom) and the first top surface region 230a1 substantially gradually decreases from the point P where the first top surface region 230a1 contacts the chip connector 115 toward the second top surface region 230a2. In other words, the first top surface region 230a1 is substantially not a plane. In other words, the portion of the dielectric 230 near the chip connector 115 is more concave than the chip connector 115.

In one embodiment, the material and/or formation method of the dielectric 230 may be similar to the material and/or formation method of the aforementioned dielectric 130. For example, in the process of forming the dielectric 230, a thinning process may be first performed to remove a portion of the dielectric material 139 (indicated in FIG. 1B ); then, a dry etching process may be performed on the area near the chip connector 115 to expose a portion of the side surface 115c of the chip connector 115.

In this embodiment, a distance S35 may be provided between the first top surface region 230a1 and the top surface 115a of the chip connector 115; and/or the roughness of the first top surface region 230a1 is different from the roughness of the top surface 115a of the chip connector 115.

In one embodiment, the top surface 115a of the chip connector 115 and the second top surface region 230a2 may be located on the same plane (ie, coplanar); and/or, the roughness of the second top surface region 230a2 may be the same as or similar to the roughness of the top surface 115a of the chip connector 115.

In this embodiment, the package structure 200 may further include a redistribution wiring layer structure 150. The redistribution wiring layer structure 150 may be located on the chip 110 and the dielectric 230. The direct contact point P between the redistribution wiring layer structure 150 (e.g., the bottom insulation layer 151), the chip connector 115 and the dielectric 230 may be located in a portion of the outer plane surface of the chip connector 115 (e.g., a portion of the side surface 115c).

FIG3 is a partial cross-sectional schematic diagram of a package structure according to a third embodiment of the present invention. The package structure 300 and/or its manufacturing method of the third embodiment are similar to the package structure 100 and/or its manufacturing method of the first embodiment, and similar components or regions are represented by the same reference numerals, have similar functions, materials or formation methods, and descriptions thereof are omitted. For example, FIG3 may be a cross-sectional schematic diagram similar to region R1 in FIG1J.

3 , the package structure 300 includes a chip 110, a dielectric 130, and a redistribution wiring layer structure 150. The redistribution wiring layer structure 150 may be located on the chip 110 and the dielectric 130. The direct contact point P between the redistribution wiring layer structure 150 (e.g., the bottom wiring layer 352 or the bottom insulation layer 151), the chip connector 115, and the dielectric 130 may be located in a portion of the outer plane surface of the chip connector 115 (e.g., a portion of the side surface 115c). The material and/or formation method of the wiring layer 352 may be similar to the material and/or formation method of the aforementioned wiring layer 152.

In one embodiment, if the position of the opening 151d is shifted during the process of forming the insulating opening 151d, the portion of the circuit layer 352 filled in the insulating opening 151d can more directly contact the portion of the side surface 115c close to the top surface 115a of the chip connector 115. In this way, the impact on the electrical properties can be reduced. In other words, a larger process margin can be provided, and the manufacturing of the package structure 300 can be simpler and/or have a higher yield.

FIG4 is a partial cross-sectional schematic diagram of a package structure according to a fourth embodiment of the present invention. The package structure 400 and/or its manufacturing method of the fourth embodiment are similar to the package structure 100 and/or its manufacturing method of the first embodiment, and similar components or regions are represented by the same reference numerals, have similar functions, materials or formation methods, and descriptions thereof are omitted. For example, FIG4 may be a cross-sectional schematic diagram similar to region R1 in FIG1J.

Referring to FIG. 4 , the package structure 400 includes a chip 110, a dielectric 130, and a redistribution wiring layer structure 150. The redistribution wiring layer structure 150 may be located on the chip 110 and the dielectric 130. The direct contact point P between the redistribution wiring layer structure 150 (e.g., the bottom wiring layer 452), the chip connector 115, and the dielectric 130 may be located in a portion of the outer plane surface (e.g., a portion of the side surface 115c) of the chip connector 115. The material and/or formation method of the wiring layer 452 may be similar to the material and/or formation method of the aforementioned wiring layer 152.

In one embodiment, if the shape of the opening 151d changes and/or the size of the opening changes during the process of forming the insulating opening 151d; and/or, the insulating opening 151d has a larger size due to design requirements (e.g., larger than the top surface 115a of the chip connector 115; similar to that shown in FIG. 4), the portion of the circuit layer 452 filled in the insulating opening 151d can more directly contact the portion of the side surface 115c of the chip connector 115 close to the top surface 115a, and surround the chip connector 115. In this way, the impact on the electrical properties can be reduced. In other words, a larger process margin can be provided, and the manufacturing of the package structure 400 can be simpler and/or have a higher yield.

It is worth noting that, in the description of this application, although FIG. 1J, FIG. 2, FIG. 3 and FIG. 4 are described in different embodiments, they can still be included in the same package structure in terms of the overall structure of the package structure (e.g., similar to package structure 100, package structure 200, package structure 300 or package structure 400). For example, in a package structure of an embodiment not shown, a cross-sectional schematic diagram of one chip connector 115 and its vicinity can be shown in one of FIG. 1J, FIG. 2, FIG. 3 and FIG. 4, and a cross-sectional schematic diagram of another chip connector 115 and its vicinity can be shown in another of FIG. 1J, FIG. 2, FIG. 3 and FIG. 4. In other words, two, three or four of the corresponding components shown in FIG. 1J, FIG. 2, FIG. 3 and FIG. 4 may exist in the same package structure. For another example, in a package structure of an embodiment not shown, due to the opening deviation, different cross sections of the same chip connector 115 may have the shapes shown in one of FIG. 1J , FIG. 2 , FIG. 3 and FIG. 4 .

5A and 5B are partial cross-sectional schematic diagrams of a package structure according to the fifth embodiment of the present invention. The package structure 500 and/or its manufacturing method of the fifth embodiment are similar to the package structure 100 and/or its manufacturing method of the first embodiment, and similar components or regions are represented by the same reference numerals, have similar functions, materials or formation methods, and descriptions are omitted. For example, FIG. 5B can be an enlarged view corresponding to region R5 in FIG. 5A.

5A and 5B , the package structure 500 includes a chip 110 and a dielectric body 130 . The chip 110 includes a chip connector 515 . The dielectric body 130 is at least located on the chip 110 .

In this embodiment, the chip connector 515 may have a top surface 515a and a side surface 515c connected to the top surface 515a. The chip connector 515 may be located on the active surface 110a of the chip 110. The dielectric 130 may not directly cover and/or directly contact a portion of the side surface 515c1 (i.e., a portion of the side surface 515c that is closer to the top surface 515a). The dielectric 130 may directly cover and/or directly contact the remaining portion of the side surface 515c2 (i.e., another portion of the side surface 515c that is farther from the top surface 515a). In one embodiment, the top surface 515a of the chip connector 515 may be substantially flat.

In this embodiment, when viewed from the cross section of the package structure 500 (e.g., as shown in FIG. 5A and FIG. 5B ), the slopes of the side surfaces 515 c of the chip connector 515 are substantially the same. In one embodiment, the side surfaces 515 c of the chip connector 515 are substantially flat (e.g., an inclined plane or a vertical plane).

In this embodiment, in the thickness direction of the package structure 500, the top surface 515a of the chip connector 515 may be the outer surface of the chip connector 515 farthest from the substrate 111; and/or, the dielectric 130 may basically not be located between the chip connector 515 and the substrate 111.

In this embodiment, the chip connector 515 may include a first conductive layer 515s and a second conductive layer 515p located on the first conductive layer 515s, and the first conductive layer 515s is located between the second conductive layer 515p and the substrate 111. In one embodiment, the first conductive layer 515s may be referred to as a seed layer. In one embodiment, the second conductive layer 515p may be referred to as a coating layer.

In this embodiment, the top surface 130a of the dielectric 130 may have a first top surface region 130a1, and the first top surface region 130a1 extends from the contact point P with the chip connector 515 in a direction away from the chip connector 515. There may be a distance S35 between the top surface 515a of the chip connector 515 and the first top surface region 130a1; and/or, the roughness of the first top surface region 130a1 is different from the roughness of the top surface 515a of the chip connector 515.

In this embodiment, the direct contact point P between the redistribution wiring layer structure 150 (e.g., the bottommost insulating layer 151), the chip connector 515, and the dielectric 130 may be located in a portion of the outer plane surface (e.g., a portion of the side surface 515c) of the chip connector 515. In other words, the contact point P is away from and/or not located at the edge of the outer plane surface (e.g., the side surface 515c) where it is located. The outer plane surface where the contact point P is located may not be parallel to the top surface 111a of the substrate 111 or the active surface 110a of the chip 110.

In this embodiment, in the thickness direction of the package structure 500, the distance S15 between the top surface 515a of the chip connector 515 and the substrate 111 is greater than the distance S13 between the contact point P and the substrate 111.

In this embodiment, in the thickness direction of the package structure 500, at least a portion of a chip connector 515 may not overlap the connection pad 112, and the chip connector 515 completely overlaps the substrate 111. In one embodiment, the form of the chip connector 515 may be similar to the form of the wiring layer 152, 154. In one embodiment, the chip connector 515 can be referred to as an on-chip redistribution wiring layer (on-chip RDL). In one embodiment, the chip connector 515 can be referred to as a fan-in redistribution wiring layer (fan in RDL). In one embodiment, the chip connector 515 can be referred to as an on-chip fan-in redistribution wiring layer (on-chip fan in RDL).

6A and 6B are partial cross-sectional schematic diagrams of a package structure according to the sixth embodiment of the present invention. The package structure 600 and/or its manufacturing method of the sixth embodiment are similar to the package structure 100 of the first embodiment, the package structure 500 of the fifth embodiment and/or its manufacturing method. Similar components or regions are represented by the same reference numerals and have similar functions, materials or formation methods, and description is omitted. For example, FIG. 6B can be an enlarged view corresponding to region R6 in FIG. 6A.

6A and 6B , the package structure 600 includes a chip 110 and a dielectric 130. The chip 110 includes a chip connector 615. The dielectric 130 is at least located on the chip 110. The chip connector 615 may include a first chip connector 617 and a second chip connector 618. The connection pad 112 is electrically connected to the corresponding first chip connector 617 through the corresponding second chip connector 618.

In this embodiment, the first chip connector 617 may have a top surface 617a and a side surface 617c connected to the top surface 617a. The dielectric 130 may not directly cover and/or directly contact a portion of the side surface 617c close to the top surface 617a. The first chip connector 617 may be located on the active surface 110a of the chip 110. The top surface 617a of the first chip connector 617 may be substantially planar. The dielectric 130 may directly cover and/or directly contact the remaining portion of the side surface 617c away from the top surface 617a.

In this embodiment, when viewing the cross section of the package structure 600 (such as shown in FIG. 6A and FIG. 6B ), the slopes of the side surfaces 617 c of the first chip connector 617 are substantially the same. In other words, the side surfaces 617 c of the first chip connector 617 are substantially flat (such as an inclined plane or a vertical plane).

In this embodiment, in the thickness direction of the package structure 600, the top surface 617a of the first chip connector 617 may be the outer surface of the first chip connector 617 farthest from the substrate 111; and/or, the dielectric 130 may not be substantially located between the first chip connector 617 and the substrate 111. Furthermore, the dielectric 130 may not be substantially located between the second chip connector 618 and the substrate 111.

In this embodiment, the first chip connector 617 may include a first conductive layer 617s and a second conductive layer 617p located on the first conductive layer 617s, and the first conductive layer 617s is located between the second conductive layer 617p and the substrate 111. The dielectric 130 may directly cover and/or directly contact the first conductive layer 617s laterally. In one embodiment, the first conductive layer 617s may be referred to as a seed layer. In one embodiment, the second conductive layer 617p may be referred to as a coating layer.

In this embodiment, the second chip connector 618 may include a first conductive layer 618s and a second conductive layer 618p located on the first conductive layer 618s, and the first conductive layer 618s is located between the second conductive layer 618p and the substrate 111. The dielectric 130 may directly cover and/or directly contact the first conductive layer 618s and the second conductive layer 618p laterally. In one embodiment, the first conductive layer 618s may be referred to as a seed layer. In one embodiment, the second conductive layer 618p may be referred to as a coating layer.

In this embodiment, the top surface 130a of the dielectric 130 may have a first top surface region 130a1, and the first top surface region 130a1 extends from the contact point P with the first chip connector 617 in a direction away from the first chip connector 617. A distance S35 may be provided between the top surface 617a of the first chip connector 617 and the first top surface region 130a1; and/or the roughness of the first top surface region 130a1 is different from the roughness of the top surface 617a of the first chip connector 617.

In this embodiment, the direct contact point P between the redistribution wiring layer structure 150 (e.g., the bottommost insulating layer 151), the first chip connector 617, and the dielectric 130 may be located in a portion of the outer plane surface (e.g., a portion of the side surface 617c) of the first chip connector 617. In other words, the contact point P is away from and/or not located at the edge of the outer plane surface (e.g., the side surface 617c) where it is located. The outer plane surface where the contact point P is located may not be parallel to the top surface 111a of the substrate 111 or the active surface 110a of the chip 110.

In this embodiment, in the thickness direction of the package structure 600, the distance S15 between the top surface 617a of the first chip connector 617 and the substrate 111 is greater than the distance S13 between the contact point P and the substrate 111.

In this embodiment, in the thickness direction of the package structure 600 , at least a portion of the second chip connector 618 may not overlap the connection pad 112 .

In one embodiment, the first chip connector 617 may be similar to the chip connector 115 described above; and/or, the second chip connector 618 may be similar to the chip connector 515 described above.

7A and 7B are partial cross-sectional schematic diagrams of a package structure according to the seventh embodiment of the present invention. The package structure 700 and/or its manufacturing method of the seventh embodiment are similar to the package structure 100 and/or its manufacturing method of the first embodiment, and similar components or regions are represented by the same reference numerals, have similar functions, materials or formation methods, and are omitted from description. For example, FIG. 7B can be a cross-sectional schematic diagram similar to region R7 in FIG. 7A.

7A and 7B , the package structure 700 includes a chip 110 and a dielectric 730 . The chip 110 includes a chip connector 115 . The dielectric 730 may include a first dielectric 731 and a second dielectric 732 . The first dielectric 731 is at least located on the active surface 110 a of the chip 110 .

In this embodiment, the material of the first dielectric 731 may be different from the material of the second dielectric 732. For example, the main material of the first dielectric 731 may be polyimide (PI), and the main material of the second dielectric 732 may be epoxy.

In this embodiment, the first dielectric 731 may be formed in a different manner from the second dielectric 732. For example, the first dielectric 731 may be formed by a film lamination process or a coating process, and the second dielectric 732 may be formed by a molding process.

In this embodiment, the first dielectric 731 may not directly cover and/or directly contact a portion of the side surface 115c1 (i.e., a portion of the side surface 115c closer to the top surface 115a); and/or, the first dielectric 731 may directly cover and/or directly contact the remaining portion of the side surface 115c2 (i.e., another portion of the side surface 115c farther from the top surface 115a). In other words, a portion of the dielectric 730 near the chip connector 115 (e.g., a portion of the first dielectric 731) is more concave than the chip connector 115.

In this embodiment, the second dielectric 732 may directly cover and/or directly contact the side surface 111 c of the substrate 111 . In the thickness direction of the package structure 700 , the dielectric 730 may not be located between the chip connector 115 and the substrate 111 .

In this embodiment, the first dielectric 731 may directly and completely cover and/or directly and completely contact the first conductive layer 115s laterally.

In this embodiment, the top surface 731a of the first dielectric 731 may have a first top surface region 731a1, and the first top surface region 731a1 extends from the contact point P with the chip connector 115 in a direction away from the chip connector 115. There may be a distance S35 between the top surface 115a of the chip connector 115 and the first top surface region 731a1; and/or, the roughness of the first top surface region 731a1 is different from the roughness of the top surface 115a of the chip connector 115.

In this embodiment, the direct contact point P between the redistribution wiring layer structure 150 (e.g., the bottommost insulating layer 151), the chip connector 115, and the first dielectric 731 may be located in a portion of the outer plane surface (e.g., a portion of the side surface 115c) of the chip connector 115. In other words, the contact point P is away from and/or not located at the edge of the outer plane surface (e.g., the side surface 115c) where it is located. The outer plane surface where the contact point P is located may not be parallel to the top surface 111a of the substrate 111 or the active surface 110a of the chip 110.

Fig. 8 is a partial cross-sectional schematic diagram of a package structure according to the eighth embodiment of the present invention. The package structure 800 and/or its manufacturing method of the eighth embodiment are similar to the package structure 100 and/or its manufacturing method of the first embodiment, and similar components or regions are represented by the same reference numerals, have similar functions, materials or formation methods, and description is omitted.

Referring to FIG. 8 , the package structure 800 includes a chip 110 and a dielectric body 130 .

In this embodiment, the package structure 800 may further include a cover 882. The cover 882 may cover the back side 110b of the chip 110.

In this embodiment, the cover 882 can be embedded in the dielectric body 130. In one embodiment, the outer surface 882b of the cover 882 can be coplanar with the bottom surface 130b of the dielectric body 130.

In one embodiment, the cover 882 can have good thermal conductivity. That is, the cover 882 can be suitable as a heat sink.

In one embodiment, the cover member 882 can have good hardness. That is, the cover member 882 can be suitable as a support member.

In one embodiment, the cover 882 may have good electromagnetic wave shielding properties, that is, the cover 882 may be suitable as an EMI shielding component.

Fig. 9 is a partial cross-sectional schematic diagram of a package structure according to the ninth embodiment of the present invention. The package structure 900 and/or its manufacturing method of the ninth embodiment are similar to the package structure 100 and/or its manufacturing method of the first embodiment, and similar components or regions are represented by the same reference numerals, have similar functions, materials or formation methods, and description thereof is omitted.

9 , the package structure 900 includes a chip 110 and a dielectric body 130 .

In this embodiment, the package structure 900 may further include a cover 983. The cover 983 may cover the back side 110b of the chip 110.

In this embodiment, the cover 983 may further cover the dielectric body 130 , and the cover 983 may be located on the bottom surface 130 b of the dielectric body 130 (at the bottom in FIG. 9 ).

In one embodiment, the cover 983 can have good thermal conductivity. That is, the cover 983 can be suitable as a heat sink.

In one embodiment, the cover member 983 may have good hardness. That is, the cover member 983 may be suitable as a support member.

In one embodiment, the cover 983 can have good electromagnetic wave shielding properties. That is, the cover 983 can be suitable as an electromagnetic interference shielding member.

It should be noted that the package structure 800 of the eighth embodiment and/or the package structure 900 of the ninth embodiment may be similar to the package structure 100 of the first embodiment, but the present invention is not limited thereto. In other unillustrated embodiments, a package structure similar to the package structure 800 of and/or a package structure similar to the package structure 900 of may be similar to the package structures of other embodiments.

In summary, by making the dielectric portion near the chip connector of the chip more concave than the chip connector, the packaging structure and the manufacturing method thereof of the present invention can be manufactured more simply and/or have a higher yield.

100, 200, 300, 400, 500, 600, 700, 800, 900: packaging structure 110: chip 110a: active surface 110b: back surface 115, 515, 615: chip connector 617: first chip connector 618: second chip connector 115s, 515s, 617s, 618s: first conductive layer 115p, 515p, 6179, 618p: second conductive layer 115a, 515a, 617a: top surface 115c, 115c1, 115c2, 515c, 617c: side surface 112: connection pad 114: protective layer 113: insulating layer 111: substrate 111a: top surface 111c: side surface 139: dielectric material 130, 230, 730: dielectric 130a, 230a: top surface 130a1, 230a1: first top surface area 230a2: second top surface area 130b: bottom surface 731: first dielectric 731a: top surface 731a1: first top surface area 732: second dielectric 150: redistribution wiring layer structure 151: insulating layer 151d: insulating opening 152, 352, 452: wiring layer 152s: first conductive layer 152p: second conductive layer 153: insulating layer 154: circuit layer 181: conductive terminal 882, 983: cover 882b: outer surface 91: carrier 92: release layer A1, A2, A3: area P: contact point R1, R4, R5, R6: area S15, S13: distance S35: spacing

Figures 1A to 1I are partial cross-sectional schematic diagrams of a partial manufacturing method of a packaging structure according to the first embodiment of the present invention. Figures 1J and 1K are partial cross-sectional schematic diagrams of a packaging structure according to the first embodiment of the present invention. Figure 2 is a partial cross-sectional schematic diagram of a packaging structure according to the second embodiment of the present invention. Figure 3 is a partial cross-sectional schematic diagram of a packaging structure according to the third embodiment of the present invention. Figure 4 is a partial cross-sectional schematic diagram of a packaging structure according to the fourth embodiment of the present invention. Figures 5A and 5B are partial cross-sectional schematic diagrams of a packaging structure according to the fifth embodiment of the present invention. Figures 6A and 6B are partial cross-sectional schematic diagrams of a packaging structure according to the sixth embodiment of the present invention. Figures 7A and 7B are partial cross-sectional schematic diagrams of a packaging structure according to the seventh embodiment of the present invention. FIG8 is a partial cross-sectional schematic diagram of a packaging structure according to the eighth embodiment of the present invention. FIG9 is a partial cross-sectional schematic diagram of a packaging structure according to the ninth embodiment of the present invention.

100:Packaging structure

110: Chip

115: Chip connector

111c: Side

130: Dielectric

150: Re-layout circuit layer structure

151: Insulation layer

152: Line layer

153: Insulation layer

154: Line layer

181:Conductive terminal

R1: Region

Claims (8)

A packaging structure, comprising: a chip, including a semiconductor substrate and a chip connector located on the semiconductor substrate; a dielectric, located at least on the chip; a redistribution wiring layer structure, located on the chip and the dielectric, wherein the chip connector, the dielectric and the redistribution wiring layer structure are directly in contact with each other at a portion of the outer plane surface of the chip connector, wherein: the outer plane surface at the direct contact location is not parallel to the top surface of the semiconductor substrate; or the outer plane surface at the direct contact location is not parallel to the active surface of the chip. A package structure as described in claim 1, wherein in the thickness direction of the package structure, at least a portion of the redistribution wiring layer structure does not overlap the chip. A packaging structure as described in claim 1, wherein in the thickness direction of the packaging structure, the distance between the top surface of the chip connector and the semiconductor substrate is greater than the distance between the direct contact point and the semiconductor substrate. A packaging structure as described in claim 1, wherein the outer planar surface where the direct contact is located is the side surface of the chip connector. A packaging structure as described in claim 1, wherein the contact point is a ring-shaped line. A packaging structure as described in claim 1, wherein the dielectric has a first top surface area extending from the contact point in a direction away from the chip connector, and there is a distance between the top surface of the chip connector and the first top surface area. A packaging structure as described in claim 1, wherein the dielectric has a first top surface region extending from the contact point in a direction away from the chip connector, and the roughness of the first top surface region is different from the roughness of the top surface of the chip connector. A packaging structure, comprising: a chip, comprising a semiconductor substrate and a chip connector located on the semiconductor substrate; a dielectric, located at least on the chip; a redistribution wiring layer structure, located on the chip and the dielectric, wherein the chip connector, the dielectric and the redistribution wiring layer structure are directly in contact with each other and are far from and/or not located at the edge of the outer plane of the chip connector where they are located, wherein: the outer plane surface where the direct contact is located is not parallel to the top surface of the semiconductor substrate; or the outer plane surface where the direct contact is located is not parallel to the active surface of the chip.

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