TWI423191B - Display panel - Google Patents

Description

Display panel

The present invention relates to a display panel, and more particularly to a display panel having a narrow margin.

FIG. 1 is a top plan view of a conventional display panel. Referring to FIG. 1 , the display panel 100 includes an array substrate 102 and a color filter substrate 104 stacked on the array substrate 102 . The array substrate 102 is provided with a plurality of scanning lines 106a and a plurality of data lines 106b perpendicular to the scanning lines 106a. The scan line 106a is interleaved with the data line 106b and defines a display area AA. In general, each of the scan lines 106a can be interconnected with a drive circuit 110 by a wire 108 to receive a scan signal from the drive circuit 110.

In order to achieve a high-resolution design, the display panel 100 can adopt a resolution design of a Wide Video Graphic Array (WVGA) standard, that is, the resolution of the display panel 100 is 800×480. Under such resolution, when the wires 108 are disposed on both sides of the display panel 100, 240 wires 108 are disposed on each side. Assuming that each of the wires 108 has a line width of 3 microns and a spacing between two adjacent wires 108 of 3 microns, the total width of the 240 wires 108 is about 1.437 cm. From this calculation, on the single side, the front edge width W of the display panel 100 is approximately 1.5 cm or so. That is to say, the margin width W on both sides of the display area AA of the display panel 100 needs to reserve at least 3 cm of space. Under such a design, the margin width W will limit the variety of product designs.

The invention provides a display panel with a narrow margin design and good signal transmission reliability.

The invention provides a display panel having a display area and a pad area located around the display area. The display panel includes an array substrate, a pair of substrates, a sealant, and a display medium layer. The array substrate has an active device array, a plurality of first pads, and a plurality of second pads. The active device array is disposed in the display area, and the first pad and the second pad are disposed in the pad area and are respectively located on adjacent sides of the active device array, wherein the second pad is directly connected to the active device array. The opposite substrate has a conductive light shielding pattern to define a plurality of third pads, a plurality of fourth pads, and a plurality of transmission paths. The transmission path is located in the display area, and the two ends of each transmission path are respectively connected to one of the third pads and one of the fourth pads, wherein the third pad is opposite to the first pad, and the fourth pad It is opposite to the second pad. The sealant is disposed in the pad region to bond the array substrate and the opposite substrate, and the sealant comprises a colloid and a plurality of conductive particles distributed in the colloid. The weight percentage of the conductive particles in the sealant is 1.5% to 6%, wherein the first pads are electrically connected to the third pads through the conductive particles, and the second pads are electrically connected to the fourth pads. The display medium layer is disposed in a space surrounded by the array substrate, the opposite substrate, and the sealant.

Based on the above, in the display panel of the present invention, the light shielding pattern on the opposite substrate can provide a function of transmitting signals, and the conductive particles are interspersed in the sealant to electrically connect the pads of the opposite substrate and the array substrate. Therefore, the display panel has a narrow margin design and good signal transmission reliability.

The above described features and advantages of the present invention will be more apparent from the following description.

2 is a partial top plan view of an array substrate of a display panel according to an embodiment of the invention. Referring to FIG. 2 , the array substrate 210 has an active device array 212 , a plurality of first pads 214 , and a plurality of second pads 216 . The first pads 214 and the second pads 216 are respectively located on adjacent sides of the active device array 212, and the second pads 216 are directly connected to the active device array 212. That is to say, when the outline of the display area AA is a rectangle, the first pad 214 and the second pad 216 are respectively located on two adjacent sides of the rectangular outline.

In detail, the active device array 212 includes a plurality of scan lines 212a, a plurality of data lines 212b, and a plurality of pixel structures 212c. The scan line 212a and the data line 212b are interlaced with each other, and the pixel structure 212c is electrically connected to one of the corresponding scan lines 212a and the corresponding one of the data lines 212b. The location where the active device array 212 is located is an area in which a picture is to be displayed, and may be defined as a display area AA. The position where the first pad 214 and the second pad 216 are located is, for example, defined as the pad area PA, and the pad area PA is, for example, located at the periphery of the display area AA.

In this embodiment, the scan signal required for the scan line 212a is, for example, outputted by a chip not shown, and the first pad 214 and the second pad 216 are used to transmit the scan signal required for the scan line 212a. . Therefore, in this embodiment, the second pad 216 is directly connected to the scan line 212a, and the first pad 214 is located at one end of the data line 212b. In other embodiments, if the first pad 214 and the second pad 216 are configured to transmit the data signal required for the data line 212b, the second pad 216 is directly connected to the data line 212b, for example, and the first pad. 214 is located at one end of the scan line 212a.

FIG. 3 illustrates a counter substrate according to an embodiment of the present invention. Referring to FIG. 3, the opposite substrate 220 has a conductive light shielding pattern 222 to define a plurality of third pads 222a, a plurality of fourth pads 222b, and a plurality of transmission paths 222c. Two ends of each of the transmission paths 222c are respectively connected to one of the third pads 222a and one of the fourth pads 222b. In the present embodiment, the transmission paths 222c are independent and electrically insulated from each other, so each transmission path 222c can transmit a signal.

The counter substrate 220 is designed, for example, to correspond to the array substrate 210 of FIG. That is, the array substrate 210 of FIG. 2 and the opposite substrate 220 of FIG. 3 are opposed to each other to form a substrate structure of a display panel. Therefore, the transmission path 222c is, for example, located in the display area AA, and the third pad 222a and the fourth pad 222b are, for example, located in the pad area PA. Referring to FIG. 2 and FIG. 3 simultaneously, in the case where the two are opposed to each other, the area of the transmission path 222c overlaps, for example, the positions of the scanning line 212a and the data line 212c. That is, the transmission path 222c constitutes, for example, a grid-like pattern to shield the positions of the scanning lines 212a and the data lines 212c. In addition, the third pad 222a faces the first pad 214, and the fourth pad 222b faces the second pad 216. That is, the third pad 222a and the fourth pad 222b are respectively disposed corresponding to the arrangement positions of the first pad 214 and the second pad 216.

In order to clearly illustrate the design of the present invention, a display panel will be proposed which is basically formed by the array substrate 210 of FIG. 2 and the opposite substrate 220 of FIG. 4 is a partial cross-sectional view of a display panel in accordance with an embodiment of the present invention. The cross section of Fig. 4 is shown corresponding to the cross-sectional line I-I' in Fig. 2 and the cross-sectional line II-II' in Fig. 3. Therefore, if the components mentioned in the following are the components already described in the previous paragraph, the same reference numerals will be given.

Referring to FIG. 2 to FIG. 4 simultaneously, the display panel 200 has a display area AA and a pad area PA located around the display area AA. The display panel 200 includes an array substrate 210, a counter substrate 220, a sealant 230, and a display medium layer 240. The display medium layer 240 is, for example, located in a space surrounded by the array substrate 210, the opposite substrate 220, and the sealant 230. In addition, the sealant 230 is disposed in the pad area PA to bond the array substrate 210 and the opposite substrate 220. Moreover, the sealant 230 includes a colloid 232 and a plurality of conductive particles 234 distributed in the colloid 232.

It is worth mentioning that the first pad 214 is electrically connected to the third pad 222a through the conductive particles 234, and the second pad 216 is electrically connected to the fourth pad 222b. Therefore, after receiving the scan signal, the first pad 214 may sequentially pass the conductive particles 234, the third pad 222a, the transmission path 222c, the fourth pad 222b, the other conductive particles 234, and the second pad 216. The transmission is input to the corresponding scan line 212a. In this way, the display panel 200 only needs to arrange a plurality of pads around the display area AA, and does not need to arrange a plurality of wires around the display area AA to transmit the scan signals.

Under such a design, the front edge of the display panel 200 only needs to conform to the required width of the pad. In addition, when the resolution of the display panel 200 is increased, the area around the display area AA is such that the area of the arrangement pads does not need to be widened, and the front edge width is not increased. Therefore, under the requirement of improving the resolution, the display panel 200 can still have the characteristics of a narrow margin.

It is worth mentioning that the reliability of the first pad 214 electrically connecting the third pad 222a and the reliability of the second pad 216 electrically connecting the fourth pad 222b are affected by the concentration of the conductive particles 234. When the concentration of the conductive particles 234 is too low, the opposite pads may not be turned on, and the concentration of the conductive particles 234 is too high, which may cause cost waste and the risk of short circuit between adjacent two pads. Therefore, in order to provide good signal transmission quality and cost considerations, the weight percentage of the conductive particles 234 in the sealant 232 is, for example, 1.5% to 6%. Of course, the concentration of the conductive particles 234 can be determined according to the actual panel resolution and the panel size. For example, for a panel having a 4.2 WVGA resolution, the weight percentage of conductive particles 234 in the sealant 232 can range from 2% to 6%, although these values are for illustrative purposes only and are not intended to limit the invention.

In addition, in order to avoid the problem that the conductive particles 234 electrically connect the adjacent pads to cause poor signal transmission quality, at least a certain distance between the pads can be maintained in the layout design of the pads. For example, the distance d1 between the adjacent first pads 214, the distance d2 of the adjacent second pads 216, the distance d3 of the adjacent third pads 222a, and the adjacent fourth pads 222b The distance d4 may be greater than twice the diameter D of each of the conductive particles 234. For example, the diameter D is, for example, 5.5 um. However, the diameter D is determined by the size of the gap between the visible array substrate 210 and the opposite substrate 220. In other embodiments, each of the conductive particles 234 may have a plurality of surface protrusions (not shown) to improve the reliability of the first pad 214 electrically connecting the third pad 222a and the second pad 216. The reliability of the fourth pad 222b is electrically connected.

In addition, the array substrate 210 further includes a plurality of first transparent pads 218a, a plurality of second transparent pads 218b, and a first insulating layer 202. The first insulating layer 202 covers at least the active device array 212 (only the scan line 212a and the data line 212b of the active device array 212 are illustrated in FIG. 4) and the first insulating layer 202 has a plurality of first contact windows C1 to make the first The transparent pad 218a contacts the first pad 214, and the second transparent pad 218b contacts the second pad 216.

In general, in the design of the active device array 212, at least two layers of insulating material are disposed in order to maintain electrical independence between the components. Therefore, the first insulating layer 202 may be composed of the gate insulating layer 202a and the protective layer 202b disposed in the active device array 212. That is to say, the first insulating layer 202 described in this embodiment is not necessarily a single material, a single insulating layer integrally formed, and the first insulating layer 202 is actually formed by stacking a plurality of insulating material layers. In addition, the material of the gate insulating layer 202a and the protective layer 202b includes yttrium oxide, tantalum nitride, an organic insulating material, and the like.

Similarly, the opposite substrate 220 further includes a plurality of third transparent pads 224, a plurality of fourth transparent pads 226, and a second insulating layer 204. The second insulating layer 204 covers at least the transmission path 222c and the second insulating layer 204 has a plurality of second contact windows C2 such that the third transparent pad 224 contacts the third pad 222a, and the fourth transparent pad 226 contacts the fourth. Pad 222b. In addition, the opposite substrate 220 further has a common electrode layer 228 located in the display area AA, and the second insulating layer 204 is located between the common electrode layer 228 and the transmission path 222c. That is, the common electrode layer 228 and the transmission path 222c are electrically insulated from each other to have different voltage signals. The material of the second insulating layer 204 includes yttrium oxide, tantalum nitride, an organic insulating material, and the like.

It is to be noted that the first transparent pad 218a and the third transparent pad 224 are opposite to each other, so that the first pad 214 can pass through the first transparent pad 218a, the conductive particles 234, and the third transparent pad 224. The third pad 222a is connected. In addition, the second transparent pad 218b and the fourth transparent pad 226 are opposite to each other. Therefore, the second pad 216 can be electrically connected to the fourth through the second transparent pad 218b, the conductive particles 234, and the fourth transparent pad 226. Pad 222b.

However, the positions where the first contact window C1 and the second contact window C2 are located structurally constitute a relatively recessed state. Once the conductive particles 234 are located in the recesses, it is easy for the conductive particles 234 to simultaneously contact the opposing transparent pads. When the area occupied by the recessed structure is larger, the reliability of the first pad 214 electrically connecting the third pad 222a and the reliability of the second pad 216 electrically connecting the fourth pad 222b will be worse. In particular, when an insulating layer is formed of an organic insulating material, the depth of the recess of the contact window is larger, and the reliability of the ground connection is less likely to be poor. Therefore, in the present embodiment, the first contact window C1 can be aligned with the second contact window C2 to set the relatively recessed structure at the same position. As a result, the probability that the conductive particles 234 cannot simultaneously contact the opposing pads can be reduced to improve the reliability of the first pads 214 electrically connecting the third pads 222a and the second pads 216 are electrically connected to the fourth connection. The reliability of the pad 222b. That is to say, the signal transmission of the display panel 200 can have a desired quality.

In this embodiment, the material of the display medium layer 240 may be a liquid crystal material, an electronic ink, an electrowetting display material, an electrophoretic material, a plasma material, or an organic light emitting material. That is, the display panel 200 may be a liquid crystal display panel, an electronic paper display panel, an electrowetting display panel, an electrophoretic display panel, a plasma display panel, or an organic light emitting display panel.

When the display medium layer 240 is a liquid crystal material, the display panel 200 further includes an alignment layer 206 disposed between the display medium layer 240 and the array substrate 210 and between the display medium layer 240 and the opposite substrate 220. In general, the adhesion between the sealant 230 and the alignment layer 206 is poor, so the alignment layer 206 can be contacted with the sealant 230 by adjustment of the process conditions. For example, if the alignment layer 206 is formed by a printing process (eg, letterpress printing, APR), the area of the printed pattern can be appropriately adjusted to be reduced to an appropriate range so that the alignment layer 206 can be located in the display area AA without extending. To the area where the sealant 230 is located. Alternatively, the alignment layer 206 is made of an appropriately viscous alignment material to ensure that the alignment layer 206 does not overflow to the location of the sealant 230.

In addition to this, the alignment layer 206 can also be fabricated using a technique of optical alignment. That is to say, the display panel 200 is formed by the optical alignment technology after the array substrate 230 and the opposite substrate 220 are assembled and filled with the liquid crystal material. As such, the adhesion between the sealant 230 and the substrate (210 or 220) is not affected by the alignment layer 206. Here, the optical alignment process may be implemented only on one of the array substrate 210 and the opposite substrate 220, or both. In other words, when the alignment layer 206 is a photo alignment layer, it may be disposed only between the display medium layer 240 and the array substrate 210 or between the display medium layer 240 and the opposite substrate 220. In general, the array substrate 210 and the opposite substrate 220 need to maintain a certain gap to exhibit good display quality. Specifically, when the concentration of the conductive particles 234 is high, the conductive particles 234 are sufficient to support the gap between the array substrate 210 and the opposite substrate 220. However, in order to ensure a gap between the array substrate 210 and the opposite substrate 220, insulating gap particles (not shown) may be selectively added to the sealant 230. That is to say, the insulating gap particles (not shown) can be selectively added to the sealant 230 depending on actual needs or product design.

In addition to the above components and structural design, the display panel 200 may also have a color filter pattern (not shown) to provide a colorful display effect. Moreover, a color filter pattern (not shown) may be disposed on the opposite substrate 220 in a grid pattern defined by the transmission path 222c. Of course, the color filter pattern (not shown) can also be integrated into the active device array 212 to form a color filter on array (COA) design.

In summary, the display panel of the present invention transmits the scan signal or the data signal to the corresponding scan line or data line by using the light-shielding conductive pattern in the display area. Therefore, the display panel of the present invention has a narrow margin design. At the same time, the sealant of the present invention has a certain concentration of conductive particles, so that the display panel has good signal transmission reliability. In the display panel of the present invention, the layout of the sealant and the layout of the pads contribute to the improvement of signal transmission reliability.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 200. . . Display panel

102, 210. . . Array substrate

104. . . Color filter substrate

106a. . . Scanning line

106b. . . Data line 106b

108. . . wire

110. . . Drive circuit

202. . . First insulating layer

202a. . . Brake insulation

202b. . . The protective layer

204. . . Second insulating layer

206. . . Alignment layer

212. . . Active component array

212a. . . Scanning line

212b. . . Data line

212c. . . Pixel structure

214. . . First pad

216. . . Second pad

218a. . . First transparent pad

218b. . . Second transparent pad

220. . . Counter substrate

222. . . Conductive shading pattern

222a. . . Third pad

222b. . . Fourth pad

222c. . . Transmission path

224. . . Third transparent pad

226. . . Fourth transparent pad

228. . . Common electrode layer

230. . . Frame glue

232. . . colloid

234. . . Conductive particle

240. . . Display media layer

AA. . . Display area

C1. . . First contact window

C2. . . Second contact window

D. . . diameter

D1~d4. . . distance

I-I’, II-II’. . . Section line

PA. . . Mat area

W. . . Front edge width

FIG. 1 is a top plan view of a conventional display panel.

2 is a partial top plan view of an array substrate of a display panel according to an embodiment of the invention.

3 is a partial top plan view of a counter substrate according to an embodiment of the invention.

4 is a partial cross-sectional view showing a display panel according to an embodiment of the present invention.

200. . . Display panel

202. . . First insulating layer

202a. . . Brake insulation

202b. . . The protective layer

204. . . Second insulating layer

206. . . Alignment layer

210. . . Array substrate

212a. . . Scanning line

212b. . . Data line

214. . . First pad

216. . . Second pad

218a. . . First transparent pad

218b. . . Second transparent pad

220. . . Counter substrate

222a. . . Third pad

222b. . . Fourth pad

222c. . . Transmission path

224. . . Third transparent pad

226. . . Fourth transparent pad

228. . . Common electrode layer

230. . . Frame glue

232. . . colloid

234. . . Conductive particle

240. . . Display media layer

AA. . . Display area

C1. . . First contact window

C2. . . Second contact window

D. . . diameter

I-I’, II-II’. . . Section line

PA. . . Mat area

Claims (9)

A display panel having a display area and a pad area around the display area, the display panel includes: an array substrate having an active device array, a plurality of first pads, and a plurality of second pads, The active device array is disposed in the display area, and the first pads and the second pads are disposed in the pad area and are respectively located on adjacent sides of the active device array, wherein the second connections The pad is directly connected to the active device array; the pair of substrates has a conductive light shielding pattern to define a plurality of third pads, a plurality of fourth pads, and a plurality of transmission paths, wherein the transmission paths are located in the display area, Each of the two ends of the transmission path is respectively connected to one of the third pads and one of the fourth pads, wherein the third pads are opposite to the first pads, and the fourth pads A mask is disposed opposite to the second pads; a mask is disposed in the pad region to bond the array substrate and the opposite substrate, and the sealant includes a colloid and a plurality of conductive layers distributed in the colloid Particles, the conductive particles are in the The weight percentage of the rubber is 1.5% to 6%. The first pads are electrically connected to the third pads through the conductive particles, and the second pads are electrically connected to the fourth pads. a pad; and a display medium layer disposed in the space surrounding the array substrate, the opposite substrate, and the sealant. The display panel of claim 1, wherein a distance between the adjacent first pads, a distance between the adjacent second pads, and adjacent third pads The distance and the adjacent fourth pads are greater than twice the diameter of each of the conductive particles. The display panel of claim 1, wherein each of the conductive particles has a plurality of surface protrusions. The display panel of claim 1, further comprising an alignment layer disposed between the display medium layer and the array substrate and between the display medium layer and the opposite substrate, and the alignment layer is not The frame is in contact with the glue. The display panel of claim 1, further comprising an optical alignment layer disposed between the display medium layer and the array substrate or between the display medium layer and the opposite substrate. The display panel of claim 1, wherein the active device array comprises: a plurality of scan lines disposed in the display area; and a plurality of data lines disposed in the display area and interlaced with the scan lines And a plurality of pixel structures disposed in the display area and electrically connecting the scan lines and the data lines, wherein when the second pads are connected to the scan lines, the first pads are located at the One end of the data lines, and the second pads are connected to the data lines, the first pads are located at one end of the scan lines. The display panel of claim 1, wherein the array substrate further comprises a plurality of first transparent pads, a plurality of second transparent pads, and a first insulating layer, the first insulating layer covering at least the active The device array has a plurality of first contact windows for contacting the first transparent pads to the first pads, and the second transparent pads contacting the second pads. The display panel of claim 7, wherein the opposite substrate further comprises a plurality of third transparent pads, a plurality of fourth transparent pads, and a second insulating layer, the second insulating layer covering at least And a plurality of second contact windows for contacting the third transparent pads to the third pads, and the fourth transparent pads contacting the fourth pads, and the first The contact window aligns the second contact windows. The display panel of claim 8, wherein the opposite substrate further has a common electrode layer located in the display area, and the second insulating layer is further located between the common electrode layer and the transmission paths. .