201137812 WP9810-C400-1055 33265twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種顯示面板，且特別是有關於一種窄額緣 的顯示面板。 【先前技術】 圖1為習知一種顯示面板的上視示意圖。請參照圖丨，顯示 面板100包括陣列基板（array substrate) 102以及疊設於陣列基板 1〇2上的彩色渡光基板（color filter substrate) 1〇4。陣列基板1〇2 上設有多條掃描線106a以及與垂直於掃描線1〇6a的多條資料線 106b。掃描線10如與資料線1〇6b交錯並定義出顯示區AA。一般 來說，每一條掃描線106a例如可藉由一條導線1〇8與—驅動電路 110相互連接，以接收來自驅動電路110的掃描訊號。 為了達到高解析度的設計，顯示面板100可採用寬視訊圖像 陣列（Wide Video Graphic Array, WVGA)標準的解析度設計，亦 即顯示面板1〇〇的解析度為8〇〇χ48〇。在這樣的解析度之下，將導 線108配置在顯示面板100的兩側邊時，每一側邊需配置有之牝 條的導線108。假設每一條導線1〇8的線寬為3微米，兩相鄰導線 108之間的間距為3微米，則240條導線108的總寬度約為1437 釐米。以此推算，在單一側邊上，顯示面板1〇〇的額緣寬度w大 約需要]，5釐米左右才足夠。也就是說，顯示面板1〇〇的顯示區 AA兩側的額緣寬度W合計至少需要預留3釐米的空間。在這樣 的。又片之下，額緣見度W將限制了產品設計的多樣性。 201137812 WP9810-C400-1055 33265twf.doc/n 【發明内容】 本發明提供一種顯示面板’具有窄額緣的設計以及良好的訊 號傳輸信賴性。 本發明提出一種顯示面板，其具有一顯示區以及位於顯示區 周邊的一接墊區。顯示面板包括一陣列基板、一對向基板、一框 膠以及一顯示介質層。陣列基板具有一主動元件陣列、多個第一 接墊以及多個第二接墊。主動元件陣列配置於顯 示區中，第一接 墊與第一接塾配置於接塾區中，並分別位於主動元件陣列之相鄰 兩側，其中第二接墊直接連接主動元件陣列。對向基板具有一導 電遮光圖案以定義出多個第三接墊、多個第四接墊以及多個傳輸 路徑。傳輸路徑位於顯示區中，且各傳輸路徑的兩端分別地連接 其中-個第三接墊以及其中一個第四接墊，其，第三接墊與第— 接塾相向而設，而第四接墊與第二接射目向而設^膠配置於接 墊區中以接合陣列基板與對向基板，且框膠包括一膠體以及分 於膠體中的多個導電粒子。導電粒子在框膠中的重量百分2為 ^5%至6%，其中透過導電粒子，第一接墊電性連接第三接塾，而 第一接墊電性連接第四接墊。顯示介質層配置於陣列基板、 基板與框膠所圍之一空間中。 。 基於上述，本發明的顯示面板中，對向基板上的遮光圖案可 提供傳輸1«的功能，且鄉中散佈有導電粒子以將對向基板與 陣列基板的接塾電性連接在—起。所以，顯示面板具有窄額緣: 設計以及良好的信號傳輸信賴性。 ， 為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施 例，並配合所附圖式作詳細說明如下。 、 201137812 WP9810-C400-1055 33265twf.doc/n 【實施方式】 圖2繪不為本發明之—實施例的顯示面板之陣列基板的局部 上視示意圖。請參照圖2，陣列基板210具有一主動元件陣列212、 多個第一接墊214以及多個第二接墊216。第一接墊214與第二接 墊216分職於主動元件陣列212之相鄰兩側，而第二接墊216 直接連接主動元件陣列212。也就是說，顯示區AA的輪廓為矩形 日可，第-接塾214與第二接塾216分別位於矩形輪廓的相鄰兩邊。 詳§之，主動兀件陣列212包括多條掃描線212a、多條資料 線2l2b以及夕個晝素結構212c。掃描線2i2a與資料線21%彼此 父錯’而晝素結構2仏電性連接對應的其中一條掃描線2丨2&與 對應的其巾-條資料線212b。线元件陣列212所在的位置是預 定要顯示晝面的區域，而可定義為一顯示區AA中。第一接墊214 與第-接墊216所在位置關如定義為接墊區pA，且接塾區pA 例如是位在顯示區AA的周邊。 以本實施例而言，掃描線212a所需的掃描訊號例如是由一 未繪不出來的晶片輸出，而第一接墊214與第二接墊216用以傳 輸掃描線212a所需的掃描訊號。所卩，在本實施例中，第二接塾 216直接連接掃描線212a，而第一接塾214位於資料線簡的一 為。在其他的實施方式中，第一接墊214與第二接墊216若設以 傳輸資料線212 b所需的資料訊號，則第二接墊2丨6例如會直接連 接貝料線212b，而第一接墊214則位於掃描線以仏的一端。 圖3鉍示為本發明之一實施例的對向基板。請參照圖3 ’對 向基板220具有-導電遮光圖案222以定義出多個第三接塾 222a、多個第四接墊222b以及多個傳輸路徑22仏。各傳輸路徑 201137812 WP9810-C400-1055 33265twf.doc/n 222c的兩端分別地連接其中一個第三接墊222a以及其中一個第四 接墊222b。在本實施例中，這些傳輸路徑222c彼此獨立且電性絕 緣，所以每一條傳輸路徑222c可以傳遞一種訊號。 對向基板220例如是對應圖2的陣列基板21〇而設計的。也 就是說’ _ 2的陣列基板210與圖3的對向基板22〇才目向組立可 以構成一顯示面板的基板架構。所以，傳輸路徑222c例如是位在 顯示區AA中，而第三接墊222a與第四接墊22沘例如位在接墊 區PA中。請同時參照圖2與圖3，在兩者相向組立的情形下，傳 輸路徑222c的面積例如會重疊於掃描線212a與資料線212c的位 置。也就是說，傳輸路徑222c例如構成網格狀的圖案，以遮蔽掃 私線212a與資料線212c的位置。另外，第三接塾222a與第一接 墊214相向，且第四接墊222b與第二接墊216相向。亦即，第三 接墊222a與第四接墊222b是分別地對應著第一接墊214與第二 接墊216的配置位置而設。 為了 /月疋說明本發明之设計以下將提出一種顯示面板，其基 本上是由圖2的陣列基板210與圖3的對向基板220組立而成。 圖4繪示為本發明之一實施例的顯示面板之局部剖面示意圖。圖4 的剖面是對應圖2中剖線1-1，以及圖3中剖線ΙΙ-ΙΓ而繪示的。所 以’以下内容中所提到的元件若是先前段落中已經說明的元件， 將會使相同的標號標示。 請同時參照圖2至圖4，顯示面板200具有顯示區AA以及 位於顯示區AA周邊的接墊區PA。顯示面板200包括陣列基板 210、對向基板220、框膠230以及顯示介質層240。顯示介質層 240例如位於陣列基板21〇、對向基板220以及框膠230所包圍的 201137812 WP9810-C400-1055 33265twf.doc/n 空間中。此外，框膠230配置於接墊區PA中以接合陣列基板21〇 與對向基板220。並且，框膠230包括一膠體232以及分布於膠體 232中的多個導電粒子234。 值得一提的是，透過導電粒子234的設計可使第一接墊214 電性連接第三接墊222a，而第二接墊216電性連接第四接墊 222b。所以，第一接墊214接收到掃描訊號後，可以依序地藉由 導電粒子234、第三接墊222a、傳輸路徑222c、第四接墊222b、201137812 WP9810-C400-1055 33265twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a display panel, and more particularly to a display panel having a narrow margin. [Prior Art] FIG. 1 is a schematic top view of a conventional display panel. Referring to the drawing, the display panel 100 includes an array substrate 102 and a color filter substrate 1〇4 stacked on the array substrate 1〇2. The array substrate 1 2 is provided with a plurality of scanning lines 106a and a plurality of data lines 106b perpendicular to the scanning lines 1〇6a. The scan line 10 is interleaved with the data lines 1〇6b and defines the display area AA. In general, each of the scan lines 106a can be connected to the drive circuit 110 by a wire 1 to 8 to receive a scan signal from the drive circuit 110. In order to achieve a high-resolution design, the display panel 100 can adopt a resolution design of a Wide Video Graphic Array (WVGA) standard, that is, the resolution of the display panel is 8〇〇χ48〇. Under such resolution, when the wires 108 are disposed on both sides of the display panel 100, the wires 108 of each of the sides are disposed on each side. Assuming that each of the wires 1 〇 8 has a line width of 3 μm and the spacing between two adjacent wires 108 is 3 μm, the total width of the 240 wires 108 is about 1437 cm. From this calculation, on the single side, the front edge width w of the display panel 1 大 is about required, and about 5 cm is sufficient. That is to say, the margin width W on both sides of the display area AA of the display panel 1A needs to reserve at least 3 cm of space. In this way. Under the film, the forehead visibility W will limit the diversity of product design. 201137812 WP9810-C400-1055 33265twf.doc/n SUMMARY OF THE INVENTION The present invention provides a display panel having a narrow margin design and good signal transmission reliability. The present invention provides a display panel having a display area and a pad area located around the display area. The display panel includes an array substrate, a pair of substrates, a mask, and a display medium layer. The array substrate has an active device array, a plurality of first pads, and a plurality of second pads. The active device array is disposed in the display area, and the first pad and the first interface are disposed in the interface region and are respectively located on adjacent sides of the active device array, wherein the second pad is directly connected to the active device array. The opposite substrate has a conductive light shielding pattern to define a plurality of third pads, a plurality of fourth pads, and a plurality of transmission paths. The transmission path is located in the display area, and two ends of each transmission path are respectively connected to one of the third pads and one of the fourth pads, wherein the third pad is opposite to the first port, and the fourth The bonding pad and the second bonding target are disposed in the pad region to engage the array substrate and the opposite substrate, and the sealant comprises a colloid and a plurality of conductive particles divided into the colloid. The weight percentage of the conductive particles in the sealant is from 5% to 6%, wherein the first pads are electrically connected to the third interface through the conductive particles, and the first pads are electrically connected to the fourth pads. The display medium layer is disposed in a space surrounded by the array substrate, the substrate, and the sealant. . Based on the above, in the display panel of the present invention, the light-shielding pattern on the opposite substrate can provide the function of transmitting 1«, and the conductive particles are interspersed in the home to electrically connect the opposite substrate to the array substrate. Therefore, the display panel has a narrow margin: design and good signal transmission reliability. The above described features and advantages of the present invention will be more apparent from the following description. [Embodiment] FIG. 2 is a partial top plan view showing an array substrate of a display panel which is not an embodiment of the present invention. Referring to FIG. 2 , the array substrate 210 has an active device array 212 , a plurality of first pads 214 , and a plurality of second pads 216 . The first pads 214 and the second pads 216 are assigned to adjacent sides of the active device array 212, and the second pads 216 are directly connected to the active device array 212. That is to say, the outline of the display area AA is a rectangular day, and the first interface 214 and the second interface 216 are respectively located on the adjacent sides of the rectangular outline. In detail, the active device array 212 includes a plurality of scan lines 212a, a plurality of data lines 214b, and a singular element structure 212c. The scan line 2i2a and the data line 21% are both parental errors, and the memory structure 2仏 electrically connects one of the scan lines 2丨2& and the corresponding towel-strip data line 212b. The position at which the line element array 212 is located is an area in which a predetermined face is to be displayed, and can be defined as a display area AA. The position where the first pad 214 and the first pad 216 are located is defined as the pad area pA, and the interface area pA is, for example, located at the periphery of the display area AA. In this embodiment, the scan signal required for the scan line 212a is outputted by an unillustrated chip, and the first pad 214 and the second pad 216 are used to transmit the scan signal required for the scan line 212a. . Therefore, in this embodiment, the second interface 216 is directly connected to the scan line 212a, and the first interface 214 is located at the data line. In other embodiments, if the first pad 214 and the second pad 216 are configured to transmit the data signal required for the data line 212 b, the second pad 2 丨 6 is directly connected to the bead line 212 b, for example. The first pad 214 is located at one end of the scan line. Figure 3 illustrates a counter substrate in accordance with one embodiment of the present invention. Referring to FIG. 3', the opposite substrate 220 has a conductive light-shielding pattern 222 to define a plurality of third interfaces 222a, a plurality of fourth pads 222b, and a plurality of transmission paths 22A. Each of the transmission paths 201137812 WP9810-C400-1055 33265twf.doc/n 222c is connected to one of the third pads 222a and one of the fourth pads 222b, respectively. In the present embodiment, these transmission paths 222c are independent of each other and electrically insulated, so that each transmission path 222c can transmit a signal. The opposite substrate 220 is designed, for example, corresponding to the array substrate 21 of FIG. That is to say, the array substrate 210 of _ 2 and the opposite substrate 22 of Fig. 3 are visually assembled to form a substrate structure of a display panel. Therefore, the transmission path 222c is, for example, located in the display area AA, and the third pad 222a and the fourth pad 22 are, for example, located in the pad area PA. Referring to Fig. 2 and Fig. 3 simultaneously, in the case where the two are opposed to each other, the area of the transmission path 222c overlaps, for example, the positions of the scanning line 212a and the data line 212c. That is, the transmission path 222c constitutes, for example, a grid-like pattern to shield the positions of the smear line 212a and the data line 212c. In addition, the third interface 222a faces the first pad 214, and the fourth pad 222b faces the second pad 216. That is, the third pad 222a and the fourth pad 222b are respectively disposed corresponding to the arrangement positions of the first pad 214 and the second pad 216. The design of the present invention will be described below. The display panel will be basically assembled from the array substrate 210 of Fig. 2 and the opposite substrate 220 of Fig. 3. 4 is a partial cross-sectional view of a display panel in accordance with an embodiment of the present invention. The cross section of Fig. 4 is shown corresponding to the line 1-1 in Fig. 2 and the line ΙΙ-ΙΓ in Fig. 3. Therefore, if the elements mentioned in the following are the elements already described in the previous paragraph, the same reference numerals will be used. Referring to FIG. 2 to FIG. 4 simultaneously, the display panel 200 has a display area AA and a pad area PA located around the display area AA. The display panel 200 includes an array substrate 210, a counter substrate 220, a sealant 230, and a display medium layer 240. The display medium layer 240 is, for example, located in the space of the 201137812 WP9810-C400-1055 33265twf.doc/n surrounded by the array substrate 21A, the opposite substrate 220, and the sealant 230. In addition, the sealant 230 is disposed in the pad area PA to bond the array substrate 21A and the opposite substrate 220. Moreover, the sealant 230 includes a colloid 232 and a plurality of conductive particles 234 distributed in the colloid 232. It is worth mentioning that the first pad 214 is electrically connected to the third pad 222a through the conductive particles 234, and the second pad 216 is electrically connected to the fourth pad 222b. Therefore, after receiving the scan signal, the first pad 214 can sequentially pass the conductive particles 234, the third pad 222a, the transmission path 222c, the fourth pad 222b,
另-導電粒子234以及第二接塾216傳輸以輸人至對應的掃描線 ⑽。如此一來’顯示面板200僅需在顯示區AA周邊配置多個 接塾’而不需在顯示區AA周邊配置多條導線崎遞掃描訊號。 在這樣的設計下，顯示面板2〇〇的額緣僅需符合接墊所需寬 f即可。此外，顯示面板的解析度提升時，顯示區aa周邊 又乂配置接塾的©積不需加寬，而不會造成額緣寬度的增加。所 以，在提高解析度的要求下，顯示面板·仍可具有窄額緣的特 點。 値付提的疋，由於導電粒子234的濃度影響第一接塾別 電〖生連接第二接塾222a的信賴性以及第二接塾216電性連接第四 的信賴性。當導電粒子咖濃度太低時，可能使相對兩 ’’、、法通㈣電粒子234漠度太高又可能造成成本上的浪 目鄰兩兩接㈣的短路風險。因此ι 了提供良好的訊號傳 ^品貝又可以兼具成本的考量，導電粒子234在框膠232中的重 里百刀t例*為1.5%至6%。當然，導電粒子濃度的高低可 二依據貫際的面板解析度與面板尺寸來決定。舉例而言，以U 、WGA解析度的面板而言，導電粒子234在框膠232中的重量 201137812 WP9810-C400-1055 33265twf.doc/n 百分比可以為2%至6% ,不過這些數值僅是舉例說明之用並非用 以限定本發明。 此外，為了避免導電粒子234使相鄰的接墊之間電性連接而 造成訊號傳輸品質不良的問題，在接墊的佈局設計上可使各接墊 之間至少維持特定的距離。舉例來說，相鄰的第一接墊214之間 的距離dl、相鄰的第二接墊216的距離d2、相鄰的第三接墊222a 的距離d3以及相鄰的第四接墊222b的距離d4可以大於各導電粒 子234的一直徑D的兩倍。舉例而言，直徑D例如為5 5um。不 過，直徑D可視陣列基板210與對向基板22〇之間的間隙大小而 決定。在其他的實施態樣中，各導電粒子234還可以具有多個表 面凸起(未繪示），以提高第一接墊214電性連接第三接墊222a的 Ί吕賴性以及第二接墊216電性連接第四接塾222b的信賴性。 另外，由剖面圖可知，陣列基板21〇更具有多個第一透明接 墊218a、多個第二透明接墊218b以及一第一絕緣層202。第一絕 緣層202至少覆蓋主動元件陣列212(圖4中僅繪示出主動元件陣 列212的掃描線21M與資料線212b)且第一絕緣層202具有多個 第一接觸窗ci以使第一透明接墊218a接觸第一接墊214，以及 使第二透明接墊218b接觸第二接墊216。 一般而言，主動元件陣列212的設計中，為了維持各元件之 間的電性獨立，配置有至少兩層絕緣材料層。因此，第一絕緣層 202可以由設置於主動元件陣列212中的閘絕緣層2〇2&以及保護 層202b所組成。也就是說，本實施例所描述的第一絕缘層2〇2並 不-定是單-材質、-體成型的單—絕緣層，而第一絕緣層2〇2 λ際上是由多個絕緣材料層堆疊而成的。此外，閘絕緣層2〇2a以 201137812 WP9810-C400-1055 33265t\vf.doc/n 及保護層202b的材質包括有氧化石夕、氮化石夕、有機絕緣材料等。 相似地，對向基板220更具有多個第三透明接墊224、多個 第四透明接墊226以及一第二絕緣層2〇4。第二絕緣層2〇4至少覆 蓋傳輸路徑222c且第二絕緣層2〇4具有多個第二接觸窗c2以使 第三透明接塾似接觸第三接墊2瓜，以及使第四透明接塾孤 接觸第四接塾222b。此外，對向基板22〇更具有位於顯示區aa 中的一共用電極層228,而第二絕緣層2〇4更位於共用電極層228 • 與傳輸路徑222c之間。也就是說，共用電極層228與傳輸路徑222c 彼此電性絕緣以具有不同的電壓訊號。第二絕緣層綱的材質包 括有氧化矽、氮化矽、有機絕緣材料等。 值得一提的是，第一透明接墊218a與第三透明接墊224相 向而没，所以第一接墊214可以透過第一透明接墊218a、導電粒 子234以及第二透明接墊224電性連接第三接墊。另外，第 了透明接墊218b與第四透明接墊226相向而設，所以第二接墊216 可以透過第二透明接墊218b、導電粒子234以及第四透明接墊226 電性連接第四接墊222b。 •然而，第一接觸窗C1與第二接觸窗C2所在位置在結構上構 成個相對凹陷的狀態。一但導電粒子234位於凹陷中，容易發 生導電粒子234無法同時接觸相向的兩透明接塾。當凹陷結構所 2面積越大’第一接墊214電性連接第三接墊222a的信賴性以及 第一接塾216電性連接第四接墊222b的信賴性將會越差。尤其 B 、 ^以有機絕緣材料製作絕緣層時，接觸窗的凹陷深度越大，而 越合易造成地性連接的信賴性不佳。所以，在本實施例中，第一 萄® C1可以對背第二接觸窗c]以將相對凹陷的結構設置於同 201137812 WP9810-C400-1055 33265twf.doc/n 樣的位置。如此-來，導電粒子234無法同時接觸相向的兩接塾 之機率將可降低而提高第-接塾214電性連接第三接塾心的作 賴性以及第二接塾训電性連接第四接塾咖的信賴性。也狀 說，顯示面板200的訊號傳輪可以具有理想的品質。 .在本實施例中，顯示介質層的材f可以是液晶材料、電 子油墨、電濕示材料、電特料、電紐料或是有機發光材 料等。也就是說，齡面板200相_晶齡面板、電子紙顯 不面板、電、4潤顯不©板、電泳顯示面板、電魏示面板或是有 機發光顯示面板等。 當顯示介質層24G為液晶材料時，顯示面板雇更包括一配 向層206’其配置於顯示介質層24〇與陣列基板21〇之間以及顯示 介質層240與對向基板220之間。一般而言，框勝23〇與配向層 2 06之間的黏著性不良，所以配向㉟2 〇 6可以藉由製程條件的調整 而不與框膠230接觸。舉例來說，若採用印刷製程(例如凸版印刷， APR)裘作配向層206時，則印刷圖案的面積可適度的調整以縮小 至適g的施圍，使配向層206可位於顯示區aa中而不延伸至框 膠230所在區域。或是，選用適當黏滯性的配向材料來製作配向 層206以確保配向層206不會溢流至框膠230所在位置。 除此之外，配向層206也可以採用光配向的技術加以製作。 也就是說，顯示面板200是在框膠230將陣列基板210與對向笑 板220組立並填入液晶材料之後，才採用光配向技術來製作配向 層206。如此一來，框膠230與基板(21〇或220)之間的黏著性不 會文到配向層206的影響。在此，光配向製程可以僅實施於陣列 基板210與對向基板220其中一者上，或是實施於兩者上。也就 10 201137812 WP9810-C400-1055 33265twf.doc/n 是說，配向層206為光配向層時，可以僅配置於顯示介質層24〇 與陣列基板210之間或顯示介質層24〇與對向基板22〇之間。 一般而言，陣列基板210與對向基板22〇需維持一定的間隙 以呈現良好的顯示品質。具體來說，當導電粒子234的濃度較高 日守，導^粒子234便足以支撐陣列基板21〇與對向基板22〇間的 間隙。不過，為了確保陣列基板21〇與對向基板22〇間的間隙， 框朦23Q中還可以選擇性地添加絕緣間隙粒子(未綠示）。也就是 • 說’絕緣間隙粒子(未繪示）可以視實際需求或是產品設計而選擇性 地添加於框膠230中。 除了上述元件與結構設計外，顯示面板2〇〇還可以具有彩色 淚光圖案(未以提供多彩化的顯示效果。並且，彩色滤光圖 案(未繪示)可以配置於對向基板22〇上，位則專輸路徑2瓜所定 義出來的網格狀圖案中。當然，彩色濾光圖案(未繪示)也可以整合 方、主動7〇件陣列212中’而構成彩色據光片在障列基板上㈣ filter on array，COA)的設計。 综上所述’本發日㈣齡面板利㈣*區巾㈣光導電圖案 _ 傳遞_訊號或是㈣訊號至對應的掃描線或是資料線H、 本=的顯示面板具有窄繼的設計。同時，本發日㈣框膠具有 2定濃度的導電粒子，而使顯示面板具有良好的訊號傳輸信賴 在本發明的顯示面板中，_的佈局與接_佈局更有助於 提高訊號傳輸信賴性。 、 、 雖然本發明已以實施例揭露如上，然其並非用以限定 明，任何所屬技術職t具有it常知識者，在不_杯明: 神和範_，當可作些狀更動㈣飾，故本糾之保護範圍^ 201137812 WP9810-C400-1055 33265twf.doc/n 視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1為習知一種顯示面板的上視示意圖。 圖2繪不為本發明之一實施例的顯#面板之陣列基板的局部 上視示意圖。 圖3繪示為本發明之-實施例之對向基板的局部上視示意 圖。 〜 圖4繪示為本發明之—實施例之顯示面板的局部剖面示意' ^ 圖。 【主要元件符號說明】 100、200 :顯示面板 102、210 :陣列基板 104 :彩色濾光基板 106a :掃描線 106b :資料線 106b。 10S :導線 110 :驅動電路 202 :第一絕緣層 202a:閘絕緣層 ，. 202b :保護層 204 :第二絕緣層 206 :配向層 212 :主動元件陣列 212a :掃描線 212b :資料線 212c :晝素結構 214 :第一接墊 216 :第二接墊 218a :第一透明接墊 218b :第二透明接墊 220 :對向基板 222 :導電遮光圖案 222a :第三接墊 222b :第四接墊 12 201137812 WP9810-C400-1055 33265twf.doc/nFurther, the conductive particles 234 and the second interface 216 are transferred for input to the corresponding scan line (10). As a result, the display panel 200 only needs to arrange a plurality of interfaces around the display area AA without having to arrange a plurality of wire-strip scan signals around the display area AA. Under such a design, the front edge of the display panel 2〇〇 only needs to conform to the required width f of the pad. In addition, when the resolution of the display panel is increased, the © product of the peripheral area of the display area aa does not need to be widened, and the front edge width is not increased. Therefore, under the request of improved resolution, the display panel can still have the characteristics of a narrow margin. The weight of the conductive particles 234 affects the reliability of the first connection electrode 224a and the reliability of the second connection port 216 electrically connected to the fourth port. When the concentration of the conductive particles is too low, the relative humidity of the two particles may be too high, which may cause a short circuit risk of the cost of the two waves. Therefore, it is possible to provide a good signal transmission. The cost of the conductive particles 234 in the sealant 232 is 1.5% to 6%. Of course, the concentration of the conductive particles can be determined according to the resolution of the panel and the size of the panel. For example, in the panel with U and WGA resolution, the weight of the conductive particles 234 in the sealant 232 may be 2% to 6% by weight, the weight of the 201137812 WP9810-C400-1055 33265twf.doc/n, but these values are only The use of the examples is not intended to limit the invention. In addition, in order to avoid the problem that the conductive particles 234 electrically connect adjacent pads to cause poor signal transmission quality, at least a certain distance between the pads can be maintained in the layout design of the pads. For example, the distance d1 between the adjacent first pads 214, the distance d2 of the adjacent second pads 216, the distance d3 of the adjacent third pads 222a, and the adjacent fourth pads 222b The distance d4 may be greater than twice the diameter D of each of the conductive particles 234. For example, the diameter D is, for example, 5 5 um. However, the diameter D is determined by the size of the gap between the array substrate 210 and the counter substrate 22A. In other embodiments, each of the conductive particles 234 may have a plurality of surface protrusions (not shown) to improve the electrical connection of the first pad 214 to the third pad 222a and the second connection. The pad 216 is electrically connected to the reliability of the fourth port 222b. In addition, as can be seen from the cross-sectional view, the array substrate 21 further includes a plurality of first transparent pads 218a, a plurality of second transparent pads 218b, and a first insulating layer 202. The first insulating layer 202 covers at least the active device array 212 (only the scan line 21M and the data line 212b of the active device array 212 are illustrated in FIG. 4) and the first insulating layer 202 has a plurality of first contact windows ci to make the first The transparent pad 218a contacts the first pad 214, and the second transparent pad 218b contacts the second pad 216. In general, in the design of the active device array 212, at least two layers of insulating material are disposed in order to maintain electrical independence between the components. Therefore, the first insulating layer 202 may be composed of the gate insulating layer 2〇2& and the protective layer 202b provided in the active device array 212. That is to say, the first insulating layer 2 〇 2 described in this embodiment is not a single-material, body-formed single-insulating layer, and the first insulating layer 2 〇 2 λ is composed of a plurality of A layer of insulating material is stacked. In addition, the gate insulating layer 2〇2a includes the materials of 201137812 WP9810-C400-1055 33265t\vf.doc/n and the protective layer 202b, including oxidized stone, cerium nitride, organic insulating material and the like. Similarly, the opposite substrate 220 further has a plurality of third transparent pads 224, a plurality of fourth transparent pads 226, and a second insulating layer 2〇4. The second insulating layer 2〇4 covers at least the transmission path 222c and the second insulating layer 2〇4 has a plurality of second contact windows c2 such that the third transparent contact contacts the third pad 2 and the fourth transparent connection The 塾 is in contact with the fourth port 222b. In addition, the opposite substrate 22 further has a common electrode layer 228 located in the display area aa, and the second insulating layer 2〇4 is located between the common electrode layer 228 and the transmission path 222c. That is, the common electrode layer 228 and the transmission path 222c are electrically insulated from each other to have different voltage signals. The material of the second insulating layer includes yttrium oxide, tantalum nitride, an organic insulating material, and the like. It is worth mentioning that the first transparent pad 218a and the third transparent pad 224 are opposite to each other, so the first pad 214 can pass through the first transparent pad 218a, the conductive particles 234 and the second transparent pad 224. Connect the third pad. In addition, the first transparent pad 218b and the fourth transparent pad 226 are opposite to each other. Therefore, the second pad 216 can be electrically connected to the fourth through the second transparent pad 218b, the conductive particles 234, and the fourth transparent pad 226. Pad 222b. • However, the positions of the first contact window C1 and the second contact window C2 are structurally configured to be relatively recessed. Once the conductive particles 234 are located in the recesses, it is easy for the conductive particles 234 to simultaneously contact the opposite transparent interfaces. When the area of the recessed structure 2 is larger, the reliability of the first pad 214 electrically connecting the third pad 222a and the reliability of the first port 216 electrically connecting the fourth pad 222b will be worse. In particular, B, ^ When the insulating layer is made of an organic insulating material, the depth of the recess of the contact window is larger, and the more reliable, the reliability of the ground connection is not good. Therefore, in the present embodiment, the first C1 can be placed opposite the second contact window c] to position the relatively recessed structure at the same position as 201137812 WP9810-C400-1055 33265twf.doc/n. In this way, the probability that the conductive particles 234 cannot simultaneously contact the opposite two contacts will be reduced, and the first connection 214 is electrically connected to the third connection and the second connection is electrically connected. The trustworthiness of the coffee shop. It is also said that the signal transmission wheel of the display panel 200 can have an ideal quality. In the present embodiment, the material f of the display medium layer may be a liquid crystal material, an electronic ink, an electrowetting material, an electric material, an electric material or an organic light-emitting material. That is to say, the age panel 200 phase _ crystal age panel, electronic paper display panel, electricity, 4 run display board, electrophoretic display panel, electric display panel or organic light display panel. When the display medium layer 24G is a liquid crystal material, the display panel further includes an alignment layer 206' disposed between the display medium layer 24A and the array substrate 21A and between the display medium layer 240 and the opposite substrate 220. In general, the adhesion between the frame and the alignment layer 260 is poor, so the alignment 352 〇 6 can be adjusted by the process conditions without contacting the sealant 230. For example, if a printing process (for example, letterpress printing, APR) is used as the alignment layer 206, the area of the printed pattern can be appropriately adjusted to be reduced to a suitable g-environment, so that the alignment layer 206 can be located in the display area aa. It does not extend to the area where the sealant 230 is located. Alternatively, the alignment layer 206 is formed using an appropriately viscous alignment material to ensure that the alignment layer 206 does not overflow to the location of the sealant 230. In addition to this, the alignment layer 206 can also be fabricated using a technique of optical alignment. That is to say, the display panel 200 is formed by using the photoalignment technique to form the alignment layer 206 after the array substrate 230 is assembled with the alignment board 220 and filled with the liquid crystal material. As a result, the adhesion between the sealant 230 and the substrate (21 or 220) is not affected by the alignment layer 206. Here, the optical alignment process may be performed only on one of the array substrate 210 and the opposite substrate 220, or both. That is, 10 201137812 WP9810-C400-1055 33265twf.doc/n is that when the alignment layer 206 is a light alignment layer, it may be disposed only between the display medium layer 24 and the array substrate 210 or the display medium layer 24 and the opposite direction. Between the substrates 22〇. In general, the array substrate 210 and the opposite substrate 22 need to maintain a certain gap to exhibit good display quality. Specifically, when the concentration of the conductive particles 234 is high, the particles 234 are sufficient to support the gap between the array substrate 21 and the opposite substrate 22. However, in order to secure a gap between the array substrate 21A and the counter substrate 22, insulating spacer particles (not shown in green) may be selectively added to the frame 23Q. That is, • The insulating gap particles (not shown) can be selectively added to the sealant 230 depending on actual needs or product design. In addition to the above-described components and structural design, the display panel 2A may also have a colored tear pattern (not to provide a colorful display effect. Moreover, a color filter pattern (not shown) may be disposed on the opposite substrate 22 The position is in the grid pattern defined by the path 2. Of course, the color filter pattern (not shown) can also be integrated into the active, active 7-piece array 212 to form a color light film in the barrier. The design of the filter on array (COA) on the column substrate. In summary, the present day (four) age panel profit (four) * area towel (four) light conductive pattern _ transfer _ signal or (four) signal to the corresponding scan line or data line H, the = display panel has a narrow design. At the same time, this day (4) sealant has 2 constant concentrations of conductive particles, so that the display panel has good signal transmission. In the display panel of the present invention, the layout and connection layout of _ is more helpful to improve signal transmission reliability. . Although the present invention has been disclosed in the above embodiments, it is not intended to be limiting, and any technical position has the knowledge of it, and in the absence of the cup: God and Fan _, when it is possible to make some changes (4), Therefore, the scope of protection of this correction ^ 201137812 WP9810-C400-1055 33265twf.doc / n as defined in the scope of the patent application is subject to change. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a top plan view of a conventional display panel. 2 is a partial top plan view of an array substrate which is not an embodiment of the present invention. Figure 3 is a partial top plan view of a counter substrate of an embodiment of the present invention. 4 is a partial cross-sectional schematic view of a display panel according to an embodiment of the present invention. [Description of main component symbols] 100, 200: display panel 102, 210: array substrate 104: color filter substrate 106a: scanning line 106b: data line 106b. 10S: wire 110: drive circuit 202: first insulating layer 202a: gate insulating layer, 202b: protective layer 204: second insulating layer 206: alignment layer 212: active device array 212a: scan line 212b: data line 212c: 昼214: first pad 216: second pad 218a: first transparent pad 218b: second transparent pad 220: opposite substrate 222: conductive opaque pattern 222a: third pad 222b: fourth pad 12 201137812 WP9810-C400-1055 33265twf.doc/n
222C :傳輸路徑 226 :第四透明接墊 230 :框膠 234 :導電粒子 AA :顯不區 C1 :第一接觸窗 D :直徑 Ι-Γ、ΙΙ-ΙΓ :剖線 W :額緣寬度 224 :第三透明接墊 228 :共用電極層 232 :膠體 240 :顯示介質層 C2 :第二接觸窗 dl〜d4 :距離 PA :接墊區222C: transmission path 226: fourth transparent pad 230: frame glue 234: conductive particles AA: display area C1: first contact window D: diameter Ι-Γ, ΙΙ-ΙΓ: section line W: front edge width 224: Third transparent pad 228: common electrode layer 232: colloid 240: display medium layer C2: second contact window dl~d4: distance PA: pad area
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