TW201143292A - Power converter and pulse width modulation signal controlling apparatus thereof - Google Patents

Abstract

A pulse width modulation signal controlling apparatus is disclosed. The pulse width modulation signal controlling apparatus includes a signal pin, a core circuit, a setting-judging circuit, a signal tuning and selecting circuit and a timer circuit. The signal pin connected to a setting device for receiving an external input signal. The setting-judging circuit receives and compares a setting signal with a reference value to generate a comparing result. The signal tuning and selecting circuit coupled to the signal pin and tunes the external input signal to the setting signal in a first status, and couples the signal pin to the core circuit in a second status. The setting signal is generated according to the setting device. The timer circuit controls the status of the signal tuning and selecting circuit and sets the signal tuning and selecting circuit in the first status within a pre-determined timing period.

Description

33805twf.doc/n 201143292 VI. Description of the Invention: [Technical Field] The present invention relates to a power conversion device, and more particularly to a pulse width modulation signal control device for a power conversion device. [Prior Art] In response to the versatility of today's electronic products, it is a popular method to generate and provide different operating power sources by a so-called power converter. Among them, the power conversion device switches the power transistor switch by using a Pulse Width Modulation (PWM) signal to achieve a switching operation between power sources. The pulse width modulation signal is usually generated by a pulse width modulation signal control device. In the pulse width modulation signal control device is integrated circuit (Integrated

In the case of Circuit, IQ彳b, in order to increase the new function of the pulse width modulation control device, it is often necessary to add additional pins to provide additional input signals. = In the integrated circuit, 'these extra connections' will take up a larger circuit area in the circuit layout of the pulse width modulation signal, and make the circuit 2 increase in the case of an increase in the total number of pins. The circuit-wide pulse width is difficult to control, and it is possible that the 4 boards of the county's wide-ranging signal control device should also be used for t °. In other words, 'this additional butterfly's board is too troublesome. problem. The invention provides a pulse width modulation signal control device, which enables the mode setting function to be completed through the signal pin position, and does not require redundant pins. The invention provides a power conversion device, wherein the mode setting function of the pulse width modulation signal control device can be completed through the signal pin position, and no need for redundant feet. The invention provides a pulse width modulation signal control device, which comprises a signal pin, a core circuit, a set break circuit, a signal adjustment and selection circuit, and a timing circuit. The signal pin is connected to the setting component for receiving the external input signal 2, the setting determining circuit receives the setting signal, compares the setting signal with the reference value, and generates a setting judgment result. The signal adjustment and selection circuit is coupled to the signal pin. When the signal is in the first state, the signal pin is coupled to the setting judgment circuit, and the external input signal is adjusted according to the setting 7G, and the signal pin is coupled to the first state. Bit to the core circuit. The setting signal is generated according to the setting. The timing circuit generates a selection signal. The timing circuit is connected to the signal adjustment and the circuit is selected to control the phantom state, wherein the 50 volt circuit causes the signal adjustment and selection circuit to be in the first state for a predetermined period of time. In an embodiment of the present invention, the setting determining circuit includes a comparator for receiving an external input signal and a reference value, and comparing the setting signal with the reference value to generate a setting determination result. In an embodiment of the present invention, the setting determining circuit further includes a lock, and the lock determination setting result is determined according to the shackle signal. 33805twf.doc/n 201143292

J. VJ 1 ATT In an embodiment of the invention, the timing circuit described above generates a pickup signal even when the timing is long enough for a predetermined period of time. In one embodiment of the invention, the set determination circuit described above includes a person-to-digital conversion H and a process ϋ. The first-class analog converter signal pin 'receives and converts the format of the Hebi format to a digital format. The setting signal of the digit format is 'and based on the 6 apostrophe of the comparison digit format and the reference value to generate a setting judgment result. In an embodiment of the invention, the setting determination circuit further includes a register. The register is coupled to the analog digital converter and sets the signal according to the lock signal lock digit format. In an embodiment of the invention, the pulse width modulation signal control device described above further includes a second analog digital converter. The second analog-to-digital converter is coupled to receive the feedback signal of the analog format and convert the feedback signal of the analog format into a digital format. The feedback signal is at least one of a feedback voltage and a return current. In one embodiment of the invention, the processor receives the feedback signal ' in a digital format and generates a protection signal in response to the feedback signal in the digital format. In an embodiment of the invention, the pulse width modulation signal control device further includes a pulse width and light age S circuit. The pulse width-dependent signal generating circuit is lightly connected to the setting circuit to generate at least one pulse width modulation signal according to the setting result and the protection signal. In an embodiment of the invention, the signal conditioning and selection circuit described above includes, for example, a source ', a first switching element, and a second switching element. The current source is connected to the signal pin. The first switching element is connected in series between the current source and the reference voltage 1W 33805twf.doc/n 201143292. The second switching element is connected in series between the core circuit and the signal pin. Wherein, when the first switching element is turned on, the current source provides an adjustment current through the reference resistor, and thereby the external input signal is adjusted as a setting signal. The invention further provides a power conversion device comprising at least one power conversion circuit and a pulse width modulation signal control device. The pulse width modulation signal control device is coupled to the power conversion circuit for generating at least one pulse width modulation signal to control the power conversion operation of the power conversion circuit, and the pulse width modulation signal control device includes a signal pin, a core circuit, and a setting judgment. Circuit: signal adjustment and selection circuit and timing circuit. The signal pin is connected to the setting component for receiving the input signal. The setting judging circuit receives the setting signal, compares the setting signal with the reference value, and thereby generates a setting judgment result. The signal adjustment and selection circuit is lightly connected to the signal position, and the first stage is set to the judgment circuit and the light external input signal is used as the slave signal and the second state is connected to the signal pin to the private circuit. Set the letterhead to determine the component. The timing circuit generates a selection signal. The timing circuit 1 adjustment and selection circuit controls the signal adjustment and selection circuit to cause the signal adjustment and selection circuit to be in the first state for a predetermined period of time. In an embodiment of the invention, the power conversion circuit described above is a DC power supply hard circuit. The touch circuit or the AC conversion (4) is timed by the timing circuit based on the pulse width modulation signal control time. According to the calculation, the external input signal is adjusted by (4) adjustment and selection circuit to 33805twf.doc/n 201143292 month & In this way, the mode setting function does not need to provide an additional pin, and the function of setting the 彳§ number to complete the mode setting can be completed by the signal pin position, thereby effectively saving the circuit area. [Embodiment] Referring to Figure 1, there is shown a transition of κ of the pulse width modulation signal control device 1GG according to an embodiment of the present invention. The pulse width modulation control unit includes a signal pin no, a signal adjustment and selection circuit 12, a setting determination circuit 130, a core circuit 140, and a timing circuit 15A. For example, the pulse width modulation signal control device 100 is configured as an example. The pulse width modulation signal control device 100 externally connects a setting component through the isp pin 110 and receives a reference level signal through the setting component. An example is the external input signal Vdd. The signal adjustment and selection circuit 120 is coupled to the signal pin 110, and the signal pin 110 is connected to the core circuit 140 according to the selection signal SEL, or the external input signal Vdd is adjusted to the setting signal MSET and coupled to the signal pin 110 to determine the setting. Circuit 130. DETAILED DESCRIPTION The signal adjustment and selection circuit 120 performs an operation of adjusting and coupling the external input signal Vdd in accordance with the selection signal SEL. For example, when the selection signal SEL is at the first level (eg, the logic low level "〇''), the signal adjustment and selection circuit 120 is now in the first state to adjust the external input signal Vdd to another voltage level. The bit setting signal MSET. Moreover, the signal adjusting and selecting circuit 120 couples the signal pin 11 to the 201143292 IW 33805twf.doc/n

The determination circuit 130 transmits the setting signal MSET to the setting determination circuit 13A. Please note here that the setting signal MSET is set according to an electrical characteristic of the setting component. In this embodiment, the setting component is the reference resistor. The setting signal MSET is determined according to the resistance value of the reference resistor core #. In other embodiments, the setting component may also be a capacitor, a diode, etc. That is to say, the user can change the setting characteristic signal MSET by changing the electrical characteristic value of the external setting component, for example, the resistance value of the reference resistance device, and further the pulse width modulation signal control device. 〇^ = Different mode settings. In addition, when the selection signal SEL is at the second level (for example, the logic level "1"), the signal adjustment and selection circuit 12 is located in the second state at this time to lightly connect the signal pin 110 to the core circuit. The core circuit 14 is caused to operate normally according to the external input signal Vdd. In this embodiment, the core circuit 140 may be a so-called power supply excellent (four) (four), that is, the broken pulse width adjustment (four) device (10) controlled - difficult circuit (not given) - whether the output voltage has approached or rose to - The stability does not change ^ the level 'to obtain the branch (four) to produce - the electric New Zealand letter to inform the Potter Road to begin operation. The selection signal SEL is generated by the timing circuit 150. Wherein, the timing circuit H0 镰 pulse width modulation signal controls the operating power supply (in the embodiment where the operation power is equivalent to the external input Vdd) is supplied. • The timing is performed. When the timing result of the timer 16150 is less than a predetermined, predetermined time period, the timing circuit 15G generates a selection signal shame adjustment and selection circuit (10) difficult to connect the signal pin to the set judgment 201143292 ---------33805twf. The doc/n interrupt circuit 130 transmits the setting signal MSET to the setting judgment circuit = 〇. In contrast, when the timing result of the timing circuit 150 is greater than or equal to the pre-turn time period, the timing circuit 150 changes the generated selection signal to cause the signal adjustment and selection circuit 120 to couple the signal pin 110 to the core circuit 140 to directly connect the external circuit. The signal vdd is input to the core circuit 14A. More specifically, when the operation power supply of the pulse width modulation signal control device 1 刚 starts to rise to a stable state. At this time, the pulse width modulation signal control device 100 is just beginning to operate. Since the conversion circuit controlled by the pulse width modulation control device 1 is not yet in operation since the mode is configured, the output voltage of the conversion circuit is not yet close to a predetermined voltage value, and the core to circuit 140 does not need to operate. . Here, the signal adjustment and selection circuit 12 传送 transmits the setting signal MSET to the setting determination circuit 13A so that the setting determination circuit 130 operates the comparison of the setting signal MSET with the reference value. After the timer circuit 150 has passed the preset time period, the setting determination circuit 130 is allowed to output the mode setting signal m〇DE_SET. At the same time, a conversion circuit controlled by the pulse width modulation k number control device 100 starts to operate, and the signal adjustment and selection circuit 120 directly connects the external input signal vdd to the core circuit 140' so that the core circuit 14 can start to determine The state of the output voltage. In this way, through a single signal pin 11 (), the mode setting of the pulse width modulation signal control device 1 and the original core circuit 140 and the like can be completed, and no additional need is added. Feet. Here, the comparison operation of the setting determination circuit 130 is performed by comparing the setting signal MSET with the magnitude of the reference value. When the reference value has only one value, the setting judgment circuit 13 can be obtained by this comparison action. 33805twf.doc/n 201143292

_____.TW Set the judgment result M〇DE_SET by setting the two modes (for example, set the signal that the judgment result MODE_SET is one bit). Of course, if the reference value includes a plurality of values, the setting determination circuit 130 can obtain the setting determination result MODE_SET that can set more modes by using the comparison operation (for example, setting the determination result MODE-SET to a signal of a plurality of bits) . The pulse width modulation signal control device 1 can determine the result MODE_SET according to the setting, and determines the operation mode in the plurality of operation modes. ' • • ‘ . . As a practical example, if the reference value has only one value VI, it can be obtained by setting the signal MSET to be greater than the value VI to obtain the setting judgment result MODE-SET of the two modes. If the reference value includes two different values VI and V2 and the value VI is greater than V2, the setting of the three modes can be determined by setting the signal MSET to be greater than the value, between the value and V2, or less than the value V2. The result is MODE_SET. It is worth mentioning that the setting result MODE_SET generated by the setting judging circuit 13A can be stably presented, and when the timing of the external circuit I% reaches a predetermined time period, the signal .SETF is generated. The pickup signal SETF is sent to the setting judgment circuit 13A, and the setting judgment circuit 130 picks up the setting judgment result MODE SET generated by the lock signal SETF. Referring to FIG. 2A, FIG. 2A is a schematic diagram of an embodiment of a pulse width modulation signal control apparatus 100. In the drawing of Fig. 2, the signal adjustment and selection circuit 120 includes a voltage combining component ι21 and a switching element 201143292 X A ‘ * * 33805 twf.doc/n 122, 123. The voltage coupling element 121 is coupled to the signal pin 110 to receive the external input signal Vdd. The switching element 123 is connected in series between the voltage coupling element 121 and the reference voltage GND, and is controlled by the selection signal SEL1. The switching element 122 is connected in series between the core circuit 140 and the signal pin 11 and is controlled by the selection signal SEL2. Wherein, when the switching element 123 is turned on, the voltage coupling element 121 couples the voltage on the signal pin 110 to generate the setting signal mset. Further, the switching elements 123 and 122 are not turned off at the same time. In the arrangement stage, the initial state switching element 122 and the switching element 123 are turned on, and then the switching element 122 is turned off, indicating that the pulse width modulation signal control device 100 is performing the mode setting operation. When the pulse width modulation signal control device 1 completes the mode setting operation, the switching element 122 is turned on to connect the external input signal Vdd to the core circuit 14A, after which the switching element 123 is turned off. The setting judgment circuit 130 includes a comparator 131 and a shackle 132. The comparator 131 receives the setting signal MSET and the reference value Vref, and compares the indefinite signal MSET with the reference value Vref to generate a setting determination result MODE_SET. The lock m handle is connected to the comparator m, and the determination result MODE_SET is set according to the pickup lock signal SETF. - Please refer to FIG. 2A and FIG. 2B in synchronization with FIG. 2B, wherein FIG. 2B is an operation waveform diagram of the embodiment of FIG. 2A. After the external input signal Vdd is stably supplied to the signal pin no and after a delay time Td, the timer circuit 150 starts the timing operation according to the start count flag START. At this time, since the timing has not yet reached the predetermined time period, the voltage PGOOD on the signal pin 11〇 is adjusted to the setting signal MSETe, and the timing circuit=the selection signal SEL2 generating the logic high level to turn off the switching element 122, and 12 33805twf.doc/n 201143292 The setting signal MSET is lightly coupled to the comparison n(3) to be compared with the reference value Vref' and then the setting judgment result (10) dE is generated. In the timing circuit of the timing circuit (9) to reach the service time period, that is, at the critical time point TA, the timer circuit 15 generates the pickup signal setf to pick up the lock setting judgment result MQDE_SET' and generates a solution (four) selects the fresh SEL2 to conduct. Switching element m, after which, the timing circuit 15 is more productive ^

Line Compendium (4) selects the money SEL1 to cut off the _ element so that the external input signal vdd is directly connected to the core circuit 14 〇. Please refer to FIG. 3, which is a schematic diagram of a pulse width device according to another embodiment of the present invention. The pulse width modulation signal control device 3 includes the signal pin 310, the signal adjustment and selection circuit 32, the judgment circuit 330, the core circuit 34, and the timing circuit 35, including the analog digital conversion II36G and the pulse width. The modulation signal generating circuit 37 is turned on. Different from the embodiment shown in Fig. 2A, the present embodiment determining circuit 330 includes an analog digital conversion circuit 331, a temporary memory, and a processor 333. Wherein, the analog digital conversion circuit 331 is numbered = 310 to receive and convert the _ format of the set signal hall τ to the digit = ▲ dMSET. The register 332 _ is connected to the analog digital switching circuit to receive the setting signal of the digital format, and the third circuit is connected to the timing circuit 350 to receive the lock signal and the lock signal SETF to pick up the lock format. Hey. The processor 3 is coupled to the register 332 to receive the setting signal dMSET of the latch format of the register 332. The processor cuts the secret to the analog digital conversion circuit 360 and the pulse width modulation signal generating circuit. Among them, the 201143292 33805 twf.doc/n analog digital conversion circuit 360 receives the feedback signal of the analog format, and the feedback signal is the feedback voltage VFB and the feedback current. At least __ of the IFB. Here, the feedback voltage VFB and the feedback current IFB are voltage and current signals fed by the turn-off terminal of the power conversion device (not shown) applied by the pulse width modulation signal # device 300. The analog digital conversion circuit 360 converts at least one of the received feedback voltage VFB and the feedback current IFB into a digital format feedback voltage dVFB and a feedback current dlF^. The processor 333 receives at least one of the feedback voltage dVFB and the feedback current dIFB in the digital format to compare with the set_number dMSET, and thereby determines whether the power conversion device has a phenomenon in which a so-called voltage or current abnormality occurs. Here, voltage anomalies include over voltage and under v〇ltage, and current anomalies include over current and under current. As a simple example, when the processor 333 determines that the setting signal dMSET is greater than the feedback voltage dVFB, it indicates that the voltage is too low; when the setting signal dMSET is smaller than the feedback voltage dVFB, it indicates that the voltage overshoot phenomenon occurs; and the setting signal dlvISET is large. When the current dIFB is fed back, it indicates that the current is too low; when the setting signal dMSET is smaller than the feedback current dlFB, it indicates that the current is too high. The processor 333 further generates the protection signal PROT according to the above-mentioned determined phenomenon, and the pulse width modulation signal generation circuit wo enters the protection mode to stop the pulse width modulation when receiving the protection signal PR〇t generated by the processor 333. Signal PWM OUT. 90114^?Q? 1 33805tuf.doc/n Further, the signal adjustment and selection circuit 320 in the present embodiment includes a current source 321 and switching elements 322, 323. In the configuration phase, the selection signals SEL1 and SEL2 both default to a low level, and when the timing circuit 350 does not reach the predetermined time period, the selection signal SEL2 is supplied to turn off the switching element 322 (at the same time, the selection signal SEL1 defaults to a low level). To turn on the switching element 323). At the same time, the current source 321 supplies the adjustment current through the reference resistor Rref, and thereby adjusts the external input signal .vdd to the set signal MSET. In other words, the setting signal MSET can be set by the magnitude of the resistance of the reference resistor. And when the timing circuit 350 counts for a predetermined period of time, the timing power, 350 provides the selection signal SEL2 to turn on the switching element 322, and then the selection signal SEL1 is turned off to turn off the switching element 323' and cut off the current provided by the current source 321 The flow path, in turn, transmits an external input signal Vdd to the core circuit 340 for normal operation. Referring to Figs. 4A to 4C, Figs. 4A to 4C are views showing a power conversion device 4A of three embodiments of the present invention, respectively. In the drawing of Fig. 4A, the power conversion device 400 includes a power conversion circuit 410 and a pulse width modulation signal control device 3A. Among them, the pulse width modulation signal control device 3 is the embodiment shown in the foregoing FIG. The power conversion circuit 410 is coupled to the pulse width modulation signal (4), and the imx receives the pulse width modulation signal generated thereby.

The PWM-〇UT ° power conversion circuit 410 is a DC-to-DC power converter that receives the DC voltage VD C and converts it into a bamboo power source by the pulse width modulation signal pWM_〇UT to generate a DC output voltage VOUT. Here, the pulse width modulation signal control device 300 may be replaced with the pulse width modulation signal control device 2 of Fig. 2A. The DC-to-DC power converter 410 of Figure 15201143292 X" \j i 1 vv 33805twf.doc/n can also be replaced by other types of DC-to-DC power converters. In the illustration of Fig. 4B, the power conversion device 400 includes a power conversion circuit 420 and a pulse width modulation signal control device 3A. The power conversion circuit 420 is lightly connected to the pulse width modulation signal control device 3 to receive the pulse width modulation signal PWM_OUT generated thereby. The power conversion circuit 420 is an AC output voltage VOUT which is an AC-to-DC power converter that receives the AC voltage VAC and performs power conversion by the PWM signal PWM_OUT. In the illustration of FIG. 4B, the pulse width modulation signal control device 300 can also be replaced with the pulse width modulation signal control device 2A illustrated in FIG. 2A. The parent-to-DC power converter 420 can also be replaced by other types of AC-to-DC power converters. In the illustration of Fig. 4C, the power conversion device 400 includes a power conversion circuit 430 and a pulse width modulation signal control device 3A. The power conversion circuit 430 is coupled to the pulse width modulation signal control device 300 to receive the pulse width modulation signal PWM_OUT generated thereby. The power conversion circuit 430 is a DC-to-AC power supply, and the converter 'receives a DC voltage VDC and converts the PWM signal from the pulse width modulation signal PWM to OUT to generate an AC output voltage VOUT. Similarly, in the illustration of FIG. 4C, the pulse width modulation signal control device 300 can also be replaced with the pulse width modulation signal control device 200 shown in FIG. 2A. The DC-to-AC power converter 430 can also be replaced by other forms of DC-to-AC power converters. 16 201143292 ------rw 33805twf.doc/n In summary, the present invention uses a timer to time the signal pin to receive external input signals and set signals at different points in time. When the setting signal is received at the signal pin, the mode setting action is completed. After the mode setting action is completed, the original action of the core circuit to which the original signal pin is connected is restored. Although the present invention has been disclosed in the above embodiments, it is intended to limit the present invention.

: In the spirit and scope of the invention, when you can make some changes and run 3 X Ming Zhi Baowei as a money agency t please full-time _ defined. BRIEF DESCRIPTION OF THE DRAWINGS 1. A schematic diagram showing a pulse width modulation signal 1〇〇 according to an embodiment of the present invention. Embodiment of the display 7F pulse width modulation signal control device (10) Fig. 2B is a green waveform diagram showing the operation of the embodiment of Fig. 2A. 300 Μ Μ Μ 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四Bit 17 201143292 33805twf.doc/n 120, 320: signal adjustment and selection circuit 130, 330: setting determination circuit 140, 340: core circuit 150, 350: timing circuit 121: voltage coupling element 122, 123, 322, 323: switch Element 131: Comparator 132: Townhouse 360, 331: Analog-to-digital converter 370: Pulse width modulation signal generation circuit 332: Register 333: Processor 321: Current source 400: Power conversion device 410 to 430: Power supply Conversion circuit Vref: Reference value START: Start count flag Td: Delay time PGOOD, VDC, VAC: Voltage PROT: Protection signal IFB, dIFB: Feedback current VFB, dVFB: Feedback voltage MSET, dMSET: Set signal SEL, SEU, SEL2: selection signal 201143292 iW 33805twf.doc/n

Vdd : External input signal Rref : Reference resistance MODE_SET : Set judgment result SETF : 拴 lock signal PWM_OUT : Pulse width modulation signal TA : Critical time point 201143292 iW 33805twf.doc/n

19

Claims (1)

33805twf.doc/n 201143292 VII. Application for Patent Park: L A pulse width modulation signal control device, comprising: - signal pin 'connection' - setting component for receiving input signal; - core circuit coupled to the signal a pin determining circuit 5, receiving a setting signal, comparing the setting signal with a reference value, and thereby generating a setting judgment result; a signal adjustment and selection circuit, lightly connected to the signal pin, the signal is adjusted to the length of the circuit, the first state is connected to the signal pin to the setting = the circuit is tilted, the component is set, and the setting is When the second state is in the second state, the signal pin is connected to the core circuit, and the setting signal is generated according to the setting component; and the (four) way is coupled to the signal adjusting and selecting circuit to control the signal shaping and selecting circuit. a state in which the timing circuit causes the signal adjustment and selection circuit to be located in the first shaped bear for a predetermined period of time. 2. Please refer to the pulse width signal described in item 如 The device, wherein the setting determining circuit comprises: a J-comparator, receiving the setting money to set a reference value to the reference value to generate the setting determination result. 3. The device as described in claim 2, wherein the setting determination circuit further comprises: ' . No. control, wherein the timing f path generates a pickup signal during the period of the signal, and the latch is coupled to the comparator, and the adjusting and selecting circuit is located in the first state to pick up the setting judgment result. 20 \V 33805 twf.doc/n 201143292^ 4. The pulse device as described in claim 2, wherein the setting determining circuit comprises: wide (four) ^ controlling a first analog-to-digital converter, and lightly connecting the signal pin Receiving and converting the setting signal of the analog format into a digital format; to pick up the patch and turn pure, according to the setting signal of the 拴 lock signal pickup digital format. The special analogy (4) 4 describes the _ signal-controlled second analog-to-digital converter, the secret processing 11, receiving the analog format 'and converting the analog format __ signal into a digit; the two 13⁄4 feedback signal is - feedback voltage and - At least its bit hi of the feedback current processes the credit of the money-receiving digit format, and generates a signal according to the _ money of the digital format. The device has a pulse width modulation signal control according to the fifth aspect of the patent scope, according to the broad modulation domain generation circuit, and is connected to the setting judgment circuit, and determines whether to generate at least a pulse width modulation signal according to the ^ signal. . • For example, please refer to the pulse width control signal described in the third paragraph of the patent scope, set the signal in j to light and select the t path to include: • 2-switching element 'transferred at the signal pin and a reference voltage 21 33805twf .doc/n 201143292 A second switching element is coupled between the core circuit and the signal pin. 8. The pulse width modulation signal control device of claim 1, wherein the setting component is a resistor. 9. A power conversion device comprising: at least one power conversion circuit; a pulse width modulation signal control device coupled to the power conversion circuit for generating at least one pulse width modulation signal to control a power conversion operation of the power conversion circuit. The pulse width modulation signal control device comprises: a signal pin Bit, connected to a setting component for receiving an external input signal; a core circuit coupled to the signal pin; - setting a judgment Wei, touch-setting signal, comparing the setting ## with a reference value, and thereby generating a Set the judgment result; - Signal tuning circuit to the 'secret bribe lion position, the signal adjustment and selection circuit is located in the -first state axis connected to the signal pin to the = judgment circuit and according to _ set component data (four) human signal for the 仏 signal and located - the second state _ the money foot to the core, the heart circuit, the towel of the slave money generated by the lion mosquito component; and the ten-hour circuit, the light adjustment and selection circuit to control = signal adjustment and Selecting the state of the circuit 'where the timing circuit causes the signal and the selection circuit to be in the first state for a predetermined period of time. 10. The power conversion conversion device according to claim 9 is characterized in that the pulse width modulation signal control device has a plurality of operation modes, and the operation result is determined according to the determination result of 22 201143292 33805 twf.doc/n. . 11. The power conversion device of claim 9, wherein the pulse width modulation signal control device receives a feedback signal, and determines whether to stop generating the at least one pulse width adjustment according to the feedback signal and the setting determination result. Change the signal. 12. The power conversion device of claim 11, wherein the power conversion circuit is a DC to DC power conversion circuit, a DC to AC power conversion circuit, or an AC to DC power conversion circuit. twenty three