TWI410052B - Analog to digital converter having amplified functions - Google Patents
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Abstract
Description
本發明係關於一種類比數位訊號轉換器,尤其是關於一種具有訊號放大功能之類比數位訊號轉換器。 The present invention relates to an analog digital signal converter, and more particularly to an analog digital signal converter having a signal amplification function.
由於人類之生理訊號為類比訊號,此訊號無法藉由處理器分析,因此需要將此類比訊號轉換成處理器所接受的數位訊號,如此才能藉由處理器將人類的的生理訊號加以分析。 Since the human physiological signal is an analog signal, the signal cannot be analyzed by the processor, so the analog signal needs to be converted into a digital signal accepted by the processor, so that the human physiological signal can be analyzed by the processor.
訊號轉換的傳統式做法為經過一類比數位訊號轉換器,將類比訊號轉換成數位訊號,但是人類的生理訊號非常之微弱,而且一般的轉換器設計並不具有放大之功能(如中華民國專利編號:200726094及I231098),因此需要外接一放大電路先將此訊號加以放大,再進行轉換。另外,類比數位訊號轉換器的精準度亦是設計重點,多數的設計都不會考慮元件數值誤差所造成的精準度問題,如此會造成精準度偏差的問題(如中華民國專利編號:I247487及200707915)。 The traditional method of signal conversion is to convert the analog signal into a digital signal through a type of digital signal converter, but the human physiological signal is very weak, and the general converter design does not have the function of amplification (such as the Republic of China patent number) :200726094 and I231098), therefore, an external amplifier circuit is required to first amplify the signal and then convert it. In addition, the accuracy of analog digital signal converters is also the design focus. Most designs do not consider the accuracy problems caused by component numerical errors, which may cause accuracy deviations (such as the Republic of China patent number: I247487 and 200707915). ).
因此,綜合上述有必要提供一種創新且較進步的發明,若能將放大電路與訊號轉換電路積體化而不需外接放大電路,並且針對電容電路加以設計,以將數值誤差修正而得到 更高的精準度。此為本發明設計創新之重點。 Therefore, it is necessary to provide an innovative and more advanced invention in combination with the above, if the amplifier circuit and the signal conversion circuit can be integrated without an external amplifier circuit, and the capacitor circuit is designed to correct the numerical error. Higher precision. This is the focus of design innovation in the present invention.
本發明目的之一在提供一種具有放大功能之類比數位轉換器,其包括一儀表放大器及一訊號轉換電路,藉由將放大器與訊號轉電路積體化,輸入類比訊號可經由內部之放大器將類比訊號放大,再將放大之訊號送至訊號轉換電路進行轉換之動作。 One of the objects of the present invention is to provide an analog digital converter having an amplification function, comprising an instrumentation amplifier and a signal conversion circuit. By integrating the amplifier and the signal conversion circuit, the input analog signal can be analogized via an internal amplifier. The signal is amplified, and then the amplified signal is sent to the signal conversion circuit for conversion.
本發明之另一目的在提供一種具有放大功能之類比數位轉換器中之一種類比數位訊號轉換電路之數值校正設計。由於此類比數位訊號轉換電路是使用電容電荷充、放電架構,因此電容會造成數值上的誤差而造成精準度下降。因此本設計中,透過演算法之計算,然後將此演算法計算之後的結果用硬體電路加以實現,如此可修正電容數值所造成的誤差。 Another object of the present invention is to provide a numerical correction design for a type-to-digital signal conversion circuit of an analog-to-digital converter having an amplification function. Since such a digital signal conversion circuit uses a capacitor charge charging and discharging structure, the capacitance causes a numerical error and causes a decrease in accuracy. Therefore, in this design, the calculation of the algorithm is performed, and then the result of the calculation of the algorithm is implemented by a hardware circuit, so that the error caused by the capacitance value can be corrected.
為達到上述目的,本發明所提供之具有放大功能之類比數位轉換器中之該訊號轉換系統架構又包含:一儀表放大電路、一取樣持電路、一類比訊號比較電路、一數位訊號控制電路、一開關陣列、一電容電荷式數位類比轉換器及一電容數值校正電路,其中該儀表放大電路將類比訊號放 大,再將訊號輸入至訊號轉換電路。 In order to achieve the above object, the signal conversion system architecture in the digital converter with the amplification function provided by the present invention further comprises: an instrument amplification circuit, a sample holding circuit, a analog signal comparison circuit, a digital signal control circuit, a switch array, a capacitor-charged digital analog converter, and a capacitance value correction circuit, wherein the meter amplifier circuit puts an analog signal Large, then input the signal to the signal conversion circuit.
參考圖1所示,本發明之具有放大功能之類比數位訊號轉換系統最佳實施例包含:一儀表放大器(IA,Instrumentation Amplifier)10與一訊號轉換器11。該儀表放大器10之架構係由運算放大器所組成,為一簡單之放大器,其放大電路之放大倍率可由調整外部電阻來決定其數值之大小,因此該儀表放大器(IA)10可將微小信號加以放大。又,該類比數位訊號轉換器11係用來將放大之後之類比訊號轉換成處理器所能處理的數位訊號 Referring to FIG. 1, a preferred embodiment of the analog digital signal conversion system having the amplification function of the present invention comprises: an instrumentation amplifier (IA) 10 and a signal converter 11. The instrumentation amplifier 10 is composed of an operational amplifier, which is a simple amplifier whose amplification factor can be adjusted by an external resistor to determine the magnitude of the value. Therefore, the instrumentation amplifier (IA) 10 can amplify the small signal. . Moreover, the analog digital signal converter 11 is used to convert the analog signal after amplification into a digital signal that the processor can process.
圖2為本發明類比數位訊號轉換系統11之較佳實施例。如圖2所示,該訊號轉換器11又包含:一取樣保持電路111、一類比訊號比較器112、一數位訊號控制器113、一開關陣列110、一電容電荷式數位類比轉換器114及一電容數值校正電路115。該取樣保持電路111能將輸入訊號進行過濾以獲得較正確的訊號。該類比訊號比較器112,能將放大之後的輸入訊號與回授訊號進行比較,以獲得數位訊號控制器的控制訊號。該數位訊號控制器113,能得到轉換器十 位元數位碼的輸出。該開關陣列110,能防止訊號衰減。該電容電荷式數位類比轉換器114,能將回授的數位訊號轉換成類比訊號,並且與輸入訊號進行比較。而該電容數值校正電路115,能將電容數值進行自我校正,以獲得較為精確的數值。該電容電荷式數位類比轉換器又包含十一組電容,能藉由電容充電放電之特性,將數位訊號轉換成類比訊號 2 is a preferred embodiment of the analog digital signal conversion system 11 of the present invention. As shown in FIG. 2, the signal converter 11 further includes: a sample and hold circuit 111, an analog signal comparator 112, a digital signal controller 113, a switch array 110, a capacitance-charged digital analog converter 114, and a Capacitance value correction circuit 115. The sample and hold circuit 111 can filter the input signal to obtain a more correct signal. The analog signal comparator 112 can compare the amplified input signal with the feedback signal to obtain a control signal of the digital signal controller. The digital signal controller 113 can obtain the converter ten The output of the bit digit code. The switch array 110 prevents signal attenuation. The capacitive-charged digital analog converter 114 converts the feedback digital signal into an analog signal and compares it with the input signal. The capacitance value correction circuit 115 can self-correct the capacitance value to obtain a more accurate value. The capacitance-charged digital analog converter further comprises eleven sets of capacitors, which can convert digital signals into analog signals by the characteristics of capacitance charging and discharging.
參考圖3所示,該取樣保持電路111又包含:一第一訊號取樣電容116、一第一運算放大器117、一第二訊號保持電容118及一第二運算放大器119。該第一訊號取樣電容116和該第二訊號保持電容118能將訊號進行取樣保持之動作;而該第一運算放大器117和第二運算放大器119具有訊號緩衝之功能。且該兩組取樣電容116、118與該兩組運算放大器117、119可交換進行取樣與保持之動作。 Referring to FIG. 3, the sample and hold circuit 111 further includes a first signal sampling capacitor 116, a first operational amplifier 117, a second signal holding capacitor 118, and a second operational amplifier 119. The first signal sampling capacitor 116 and the second signal holding capacitor 118 can perform sampling and holding operations; and the first operational amplifier 117 and the second operational amplifier 119 have a function of signal buffering. And the two sets of sampling capacitors 116, 118 and the two sets of operational amplifiers 117, 119 can be exchanged for sampling and holding.
再如參考圖3所示,該取樣保持電路(Sampling and Holding Circuit)111用來接收時脈訊號401,當正半週來臨時,第一訊號取樣電容116及第一運算放大器117進行取樣動作,而第二訊號取樣電容118及第二運算放大器119則進行保持動作;反之,當時脈訊號401的負半週來臨時,第一訊號取樣電容116及第一運算放大器117進行保持動作,而 第二訊號取樣電容118及第二運算放大器119則進行取樣動作,如此反覆運作即可達成雙取樣的功能。 As shown in FIG. 3, the sampling and holding circuit 111 is configured to receive the clock signal 401. When the positive half cycle comes, the first signal sampling capacitor 116 and the first operational amplifier 117 perform sampling operations. The second signal sampling capacitor 118 and the second operational amplifier 119 perform a holding operation; conversely, when the negative half cycle of the pulse signal 401 comes, the first signal sampling capacitor 116 and the first operational amplifier 117 perform a holding operation, and The second signal sampling capacitor 118 and the second operational amplifier 119 perform a sampling operation, so that the double sampling function can be achieved by repeating the operation.
參考圖4所示,該類比訊號比較器112能將放大後的類比訊號與回授訊號進行比較,而獲得數位訊號控制器113的控制訊號。該類比訊號比較器112又包含:一偏壓電路301及一差動對比較器主電路302。經由該偏壓電路301供給該差動對比較器主電路302一穩定的偏壓值,若此偏壓值不穩定則會造成該差動對比較器主電路302的錯誤動作。該差動對比較器主電路302能接收偏壓電路301之電壓,並將兩類比輸入訊號進行比較,以產生一數位控制訊號。若由該取樣保持電路111輸出的類比訊號值大於回授訊號402值,則類比訊號比較器112會輸出數位訊號0。而若由取樣保持電路111輸出的類比訊號值小於回授訊號402值,則類比訊號比較器112會輸出數位訊號1。準此,由類比訊號比較器所獲得的訊號可控制數位訊號控制器113的動作。 Referring to FIG. 4, the analog signal comparator 112 can compare the amplified analog signal with the feedback signal to obtain the control signal of the digital signal controller 113. The analog signal comparator 112 further includes a bias circuit 301 and a differential pair comparator main circuit 302. The differential pair comparator main circuit 302 is supplied with a stable bias value via the bias circuit 301. If the bias value is unstable, the differential operation of the comparator main circuit 302 is caused. The differential pair comparator main circuit 302 can receive the voltage of the bias circuit 301 and compare the two analog input signals to generate a digital control signal. If the analog signal value output by the sample and hold circuit 111 is greater than the value of the feedback signal 402, the analog signal comparator 112 outputs the digital signal 0. If the analog signal value output by the sample and hold circuit 111 is less than the value of the feedback signal 402, the analog signal comparator 112 outputs the digital signal 1. Accordingly, the signal obtained by the analog signal comparator can control the action of the digital signal controller 113.
參考圖5所示,該數位訊號控制器113係能產生所需之數位訊號,此訊號並用來控制該開關陣列110以產生所需之訊號。該數位訊號控制器113又包含:一上層序向邏輯電路120及一下層序向邏輯電路121。該上層序向邏輯電路120 能產生控制訊號去控制下層序向邏輯電路;而該下層序向邏輯電路121能在接收控制訊號之後產生回授訊號與十位元數位碼。該數位訊號控制器113主要是由上層之位移暫存器120控制下層暫存器121。其控制器動作原理為一開始先經由上層序向邏輯電路120設定初始值,將最高位元(MSB,Most Significant Bit)設定為1,其它位元設定為0,亦即數值設定為二位元數值10000000000。如果類比訊號比較器112之輸出訊號為1,最高位元(MSB)將會被重設為0,並且保持到整個比較週期結束為止;反之,若類比訊號比較器112之輸出訊號為1,則最高位元(MSB)會繼續保持為1。其餘的位元以此類推,在第一個位元比較完成之後,再進行第二個位元的比較,一個時脈的時間決定一個位元的數值,一開始之最高位元(MSB)都先設為1,然後依類比訊號比較器112之輸出決定要保持1或改為0。 Referring to FIG. 5, the digital signal controller 113 is capable of generating a desired digital signal which is used to control the switch array 110 to generate the desired signal. The digital signal controller 113 further includes an upper sequence logic circuit 120 and a lower layer sequence logic circuit 121. The upper sequence logic circuit 120 A control signal can be generated to control the lower sequence logic circuit; and the lower sequence logic circuit 121 can generate a feedback signal and a tens digit code after receiving the control signal. The digital signal controller 113 is mainly controlled by the upper level shift register 120 to control the lower layer register 121. The controller operates on the principle that the initial value is first set to the logic circuit 120 via the upper sequence, the highest bit (MSB, Most Significant Bit) is set to 1, and the other bits are set to 0, that is, the value is set to two bits. The value is 10000000000. If the output signal of the analog signal comparator 112 is 1, the highest bit (MSB) will be reset to 0 and will remain until the end of the entire comparison period; conversely, if the output signal of the analog signal comparator 112 is 1, then The highest bit (MSB) will remain at 1. The rest of the bits are deduced by analogy. After the first bit comparison is completed, the second bit is compared. The time of one clock determines the value of one bit. The highest bit (MSB) at the beginning is Set to 1 first, then decide to keep 1 or 0 depending on the output of the analog signal comparator 112.
參考圖6所示,該電容數值校正電路115又包含:一校正電容201及一校正DAC電路(Digital/Analog Converter,數位/類比轉換器)202。經由演算法(Algorithm)能夠計算出電容校正值,亦即將電容電荷式數位類比轉換器的每一電容誤差值計算出來,再累加到輸出部份再進行充、放電,如此可 將電容電荷式數位類比轉換器的每一電容誤差值加以校正,以修正誤差值所造成的充、放電準位問題,俾確保其精準度。該校正DAC電路202能將校正碼轉換成類比電壓,再輸入至校正電容,如此可獲得精確的訊號。 Referring to FIG. 6, the capacitance value correction circuit 115 further includes a correction capacitor 201 and a correction DAC circuit (Digital/Analog Converter) 202. Through the algorithm, the capacitance correction value can be calculated, that is, each capacitance error value of the capacitance-charged digital analog converter is calculated, and then added to the output portion to be charged and discharged, so that The capacitance error value of the capacitance-charged digital analog converter is corrected to correct the charge and discharge levels caused by the error value, and the accuracy is ensured. The correction DAC circuit 202 can convert the correction code into an analog voltage and then input it to the correction capacitor, so that an accurate signal can be obtained.
訊號經由儀表放大器10放大之後,將此訊號輸入該取樣保持電路111,該取樣保持電路111會將此類比訊號進行過濾之動作,以獲得較準確之訊號,然後再將該訊號送至類比訊號比較器112。在比較出電壓值之後可獲得1與0之數位訊號,此數位訊號是用來控制數位訊號控制器113之動作。數位訊號控制器113之輸出結果再送至開關陣列110,此該開關陣列110是用來防止因訊號衰減而造成電容電荷式數位類比轉換器114之錯誤動作。在加入開關陣列110後,可將訊號維持在1.8V之準位,接著再將訊號送回至電容電荷式數位類比轉換器114,經由轉換之後,再與取樣保持電路111之輸出結果進行比較,之後將比較結果輸入至數位訊號控制器113,以此電路動作循環,經過十一個時脈頻率之後方能得到所需之十位元數位碼。 After the signal is amplified by the instrumentation amplifier 10, the signal is input to the sample and hold circuit 111, and the sample and hold circuit 111 filters the analog signal to obtain a more accurate signal, and then sends the signal to the analog signal. 112. The digital signals of 1 and 0 are obtained after comparing the voltage values, and the digital signals are used to control the operation of the digital signal controller 113. The output of the digital signal controller 113 is sent to the switch array 110, which is used to prevent the erroneous action of the capacitive-charged digital analog converter 114 due to signal attenuation. After the switch array 110 is added, the signal can be maintained at the level of 1.8V, and then the signal is sent back to the capacitance-charged digital analog converter 114, and after being converted, the output of the sample-and-hold circuit 111 is compared. Then, the comparison result is input to the digital signal controller 113, and the circuit operates in a loop, and after the eleven clock frequencies, the required tens digit code can be obtained.
本發明具有低複雜度、低功率消耗、自我校正電路及訊號放大之優點,此轉換器系統非常適合應用在民生及醫療工 業使用上。 The invention has the advantages of low complexity, low power consumption, self-correcting circuit and signal amplification. The converter system is very suitable for application in people's livelihood and medical workers. Industry use.
該較佳具體實施例僅為了易於說明本發明之技術內容,而並非將本發明狹義地限制於該實施例,凡依本發明之精神及以下申請專利內容所列之情況所做之種種變化實施均屬本發明之範圍。 The preferred embodiments are merely illustrative of the technical contents of the present invention, and are not intended to limit the invention to the embodiments, and various changes are made in accordance with the spirit of the present invention and the circumstances listed in the following claims. All are within the scope of the invention.
10‧‧‧儀表放大器 10‧‧‧Instrument Amplifier
11‧‧‧類比數位訊號轉換器 11‧‧‧ Analog Digital Signal Converter
110‧‧‧開關陣列 110‧‧‧Switch array
111‧‧‧取樣保持電路 111‧‧‧Sampling and holding circuit
112‧‧‧類比訊號比較器 112‧‧‧ analog signal comparator
113‧‧‧數位訊號控制器 113‧‧‧Digital Signal Controller
114‧‧‧電容電荷式數位類比轉換器 114‧‧‧Capacitive-charged digital analog converter
115‧‧‧電容數值校正電路 115‧‧‧Capacitance value correction circuit
116‧‧‧第一取樣保持電容 116‧‧‧First sample hold capacitor
117‧‧‧第一取樣保持運算放大器 117‧‧‧First sample-and-hold op amp
118‧‧‧第二取樣保持電容 118‧‧‧Second sample holding capacitor
119‧‧‧第二取樣保持運算放大器 119‧‧‧Second sample-and-hold op amp
120‧‧‧上層序向邏輯電路 120‧‧‧Upper sequence logic
121‧‧‧下層序向邏輯電路 121‧‧‧lower sequence logic
201‧‧‧校正電容 201‧‧‧correcting capacitor
202‧‧‧校正DAC電路 202‧‧‧Correct DAC circuit
301‧‧‧偏壓電路 301‧‧‧bias circuit
302‧‧‧差動對比較器主電路 302‧‧‧Differential pair comparator main circuit
401‧‧‧時脈訊號 401‧‧‧ clock signal
402‧‧‧回授訊號 402‧‧‧Response signal
圖1為本發明具有放大功能之類比數位訊換轉器示意圖;圖2為本發明類比數位訊號轉換器之架構示意圖;圖3為本發明取樣保持電路示意圖;圖4為本發明類比訊號比較器示意圖;圖5為本發明數位訊號控制器之架構示意圖;圖6為本發明電容數值校正電路示意圖; 1 is a schematic diagram of an analog digital converter having an amplification function; FIG. 2 is a schematic diagram of an analog digital converter of the present invention; FIG. 3 is a schematic diagram of a sample and hold circuit of the present invention; FIG. 5 is a schematic structural diagram of a digital signal controller according to the present invention; FIG. 6 is a schematic diagram of a capacitor numerical value correcting circuit according to the present invention;
10‧‧‧儀表放大電路 10‧‧‧Amplifier amplifier circuit
11‧‧‧類比數位轉換電路 11‧‧‧ analog digital conversion circuit
Claims (5)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW98119841A TWI410052B (en) | 2009-06-12 | 2009-06-12 | Analog to digital converter having amplified functions |
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| Application Number | Priority Date | Filing Date | Title |
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| TW98119841A TWI410052B (en) | 2009-06-12 | 2009-06-12 | Analog to digital converter having amplified functions |
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| Publication Number | Publication Date |
|---|---|
| TW201044792A TW201044792A (en) | 2010-12-16 |
| TWI410052B true TWI410052B (en) | 2013-09-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW98119841A TWI410052B (en) | 2009-06-12 | 2009-06-12 | Analog to digital converter having amplified functions |
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| TW (1) | TWI410052B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10511318B2 (en) | 2018-02-13 | 2019-12-17 | Nuvoton Technology Corporation | Digital background calibration circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200913507A (en) * | 2007-09-14 | 2009-03-16 | Realtek Semiconductor Corp | Self-calibrating digital-to-analog converter and method thereof |
| TW200924718A (en) * | 2007-12-07 | 2009-06-16 | Univ Nat Sun Yat Sen | Low power implantable bladder presure monitor system |
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2009
- 2009-06-12 TW TW98119841A patent/TWI410052B/en not_active IP Right Cessation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200913507A (en) * | 2007-09-14 | 2009-03-16 | Realtek Semiconductor Corp | Self-calibrating digital-to-analog converter and method thereof |
| TW200924718A (en) * | 2007-12-07 | 2009-06-16 | Univ Nat Sun Yat Sen | Low power implantable bladder presure monitor system |
Non-Patent Citations (1)
| Title |
|---|
| M.-C. Huang and S.-I. Liu, "A fully differential comparator-based switched-capacitor DeltaSigma modulator," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 5, pp. 369-373, May 2009. * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10511318B2 (en) | 2018-02-13 | 2019-12-17 | Nuvoton Technology Corporation | Digital background calibration circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201044792A (en) | 2010-12-16 |
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