201044792 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種類比數位訊號轉換器，尤其是關於一 種具有訊號放大功能之類比數位訊號轉換器。 【先前技術】 〇 由於人類之生理訊號為類比訊號，此訊號無法藉由處理 器分析’因此需要將此類比訊號轉換成處理器所接受的數位 訊號’如此才能藉由處理器將人類的的生理訊號加以分析。 訊號轉換的傳統式做法為經過一類比數位訊號轉換界， 將類比訊號轉換成數位訊號，但是人類的生理訊號非常之微 弱，而且一般的轉換器設計並不具有放大之功能(如中華民國 專利編號:200726094及1231098) ’因此需要外接一放大電路 先將此訊號加以放大，再進行轉換。另外，類比數位訊號轉 換器的精準度亦是設計重點’多數的設計都不會考慮元件數 值誤差所造成的精準度問題，如此會造成精準度偏差的問題 (如中華民國專利編號:1247487及200707915)。 因此，綜合上述有必要提供一種創新且較進步的發明， 若能將放大電路與訊號轉換電路積體化而不需外接放大電 路’並且針對電容電路加以設計’以將數值誤差修正而得到 201044792 更高的精準度。此為本發明設計創新之重點。 【發明内容】 本發明目的之-在提供—種具有放大功能之類比數位 轉換器，其包括-儀表放大器及一訊號轉換電路，藉由將 放大器與訊號轉電路積體化，輪入類比訊號可經由内部之 ❹ 社&將紙峨放大’縣放大之峨送JL訊號轉換電 路進行轉換之動作。 本發明之另-目的在提供—種具姐大魏之類比數 位轉換器巾之-種酿數位訊轉換電路之數值校正設 十由於此類比數位訊號轉換電路是使用電容電荷充、放 電架構，因此電容會造成數值上的誤差而造成精準度下 ) 降。因此本設計巾’透過法之計算，然後將此演算法 計算之後的結果用硬體電路加以實現，如此可修正電容數 值所造成的誤差。 為達到上述目的，本發明所提供之具有放大功能之類 比數位轉換器中之該訊號轉換系統架構又包含:一儀表放大 電路、一取樣持電路、一類比訊號比較電路、一數位訊號 控制電路、-開關陣列、一電容電荷式數位類比機電路 及一電容數值校正電路，其中該儀表放大電路將類比訊號 5 .201044792 放大，再將訊號輸入至訊號轉換電路。 【實施方式】 參考圖1所示，本發明之具有放大功能之類比數位訊號 轉換系統最佳實施例包含：一儀表放大器(IA，Instrumentation Amplifier) 1〇與一訊號轉換器η。該儀表放大器10之架構 係由運算放大器所組成，為一簡單之放大器，其放大電路之 放大倍率可由調整外部電阻來決定其數值之大小，因此該儀 表放大器(ΙΑ) 10可將微小信號加以放大。又，該類比數位訊 號轉換器11係用來將放大之後之類比訊號轉換成處理器所 能處理的數位訊號 圖2為本發明類比數位訊號轉換系統u之較佳實施 例。如圖2所示，該訊號轉換器π又包含：一取樣保持電 路11卜一類比訊號比較器112、一數位訊號控制器113、一 開關陣列110、一電容電荷式數位類比轉換電路114及一電 容數值校正電路115。該取樣保持電路1U能將輸入訊號進 行過濾以獲得較正確的訊號。該類比訊號比較器112，能將 放大之後的輸入訊號與回授訊號進行比較，以獲得數位訊號 控制器的控制訊號。該數位訊號控制器113，能得到轉換器 6 201044792 十位元數位碼的輸出。該開關陣列110，能防止訊號衰減。 該電容電荷式數位類比轉換器114 ’能將回授的數位訊號轉 換成類比訊號，並且與輸入訊號進行比較。而該電容數值校 正電路115，能將電容數值進行自我校正，以獲得較為精確 的數值。該電容電荷式數位類比轉換器又包含十一組電容， 能藉由電容充電放電之特性，將數位訊號轉換成類比訊號 參考圖3所示，該取樣保持電路111又包含：一第一訊號 取樣電容116、一第一運算放大器117、一第二訊號保持電容 118及一第二運算放大器119。該第一訊號取樣電容116和該 第二訊號保持電容118能將訊號進行取樣保持之動作；而該第 一運算放大器117和第二運算放大器119具有訊號緩衝之功 能。且該兩組取樣電容116、118與該兩組運算放大器117、 119可交換進行取樣與保持之動作。 再如參考圖3所示，該取樣保持電路(SampUng Holding Circuit )111用來接收時脈訊號4〇1，當正半週來臨 枯，第一訊號取樣電容116及第一運算放大器η?進行取樣 動作，而第二訊號取樣電容118及第二運算放大器119則進 行保持動作；反之’當時脈訊號4Q1的負半週來臨時，第一 訊號取樣電容116及第-料放大器m進行麟動作，而 7 201044792 第二訊號取樣電容118及第二運算放大器119則進行取樣動 作，如此反覆運作即可達成雙取樣的功能。 參考圖4所示，該類比訊號比較器112能將放大後的類 比訊號與回授訊號進行比較，而獲得數位訊號控制器113的 控制訊號。該類比訊號比較器112又包含：一偏壓電路301 及一差動對比較器主電路302。經由該偏壓電路301供給該 差動對比較器主電路302 —穩定的偏壓值，若此偏壓值不穩 定則會造成該差動對比較器主電路302的錯誤動作。該差動 對比較器主電路302能接收偏壓電路301之電壓，並將兩類 比輸入訊號進行比較，以產生一數位控制訊號。若由該取樣 保持電路111輸出的類比訊號值大於回授訊號402值，則類 比訊號比較器112會輸出數位訊號〇。而若由取樣保持電路 111輸出的類比訊號值小於回授訊號402值，則類比訊號比 較器112會輸&數位域丨。軸，_比訊號比較器所獲 得的訊號可控制數位訊號控制器113的動作。 參考圖5所示，練位減控彻ln係魅生所需之 數位訊號’此訊號並絲控繼關陣列iig以產生所需之 訊號。該數位訊號控· 113又包含：_上層序向邏輯電路 及一下層序向糖電路⑵。該上層序向邏輯電路12〇 8 201044792 能產生控制訊號去控制下層序向邏輯電路；而該下層序向邏 輯_ 121能在接收控制訊號之後產生回授訊號與十位元數 位碼。该數位訊號控制器113主要是由上層之位移暫存器12〇 控制下層暫存器m。其控制n動作原理為—開始先經由上 層序向邏輯電路120設定初始值，將最高位元(MSB，M〇st ❹ SigmilcantBit)設定為1，其它位元設定為〇，亦即數值設定 為一位元數值10000000000。如果類比訊號比較器之輸 出訊號為1 ’最高位元(MSB)將會被重設為〇，並且保持到整 個比較週齡束為止；反之，細比峨味㈣112之輸出 讯號為1 ’則最高位元(MSB)會繼續保持為〗。其餘的位元以 此類推，在第一個位元比較完成之後，再進行第二個位元的 比較，一個時脈的時間決定一個位元的數值，一開始之最高 D 位兀(MSB)都先設為卜然後依類比訊號比較器U2之輸出 決定要保持1或改為〇。 參考圖ό所示’該電容數值校正電路115又包含：一校 正電容 201 及一校正電路 DAC(Digital/Anal〇gC〇nverter，數 位/類比轉換器）202。經由演算法(Aig〇rithm)能夠計算出電 容校正值’亦即將電容電荷式的每一電容誤差值計算出來， 再累加到輸出部份再進行充、放電，如此可將電容電荷式數 9 201044792 位類比轉換器的每一電容誤差值加以校正，以修正誤差值所 造成的充、放電準位問題，俾確保其精準度。該校正電路 DAC 202能將校正碼轉換成類比電壓，再輸入至校正電容， 如此可獲得精確的訊號。201044792 VI. Description of the Invention: [Technical Field] The present invention relates to an analog digital signal converter, and more particularly to an analog digital signal converter having a signal amplification function. [Prior Art] Since the human physiological signal is an analog signal, this signal cannot be analyzed by the processor 'so it is necessary to convert such a specific signal into a digital signal accepted by the processor' so that the human physiology can be processed by the processor. Signals are analyzed. The traditional method of signal conversion is to convert the analog signal into a digital signal through a class of analog-to-digital signal conversion, but the human physiological signal is very weak, and the general converter design does not have the function of amplification (such as the Republic of China patent number). :200726094 and 1231098) 'Therefore, an external amplifier circuit is required to amplify this signal and then convert it. In addition, the accuracy of the analog digital signal converter is also the design focus 'Most of the design will not consider the accuracy of the component numerical error, which will cause the accuracy of the deviation (such as the Republic of China patent number: 1247487 and 200707915 ). Therefore, it is necessary to provide an innovative and more advanced invention in combination with the above, if the amplifier circuit and the signal conversion circuit can be integrated without the need for an external amplifier circuit 'and the capacitor circuit is designed' to correct the numerical error to obtain 201044792. High precision. This is the focus of design innovation in the present invention. SUMMARY OF THE INVENTION An object of the present invention is to provide an analog-to-digital converter with an amplification function, which includes an instrumentation amplifier and a signal conversion circuit. By integrating the amplifier and the signal conversion circuit, the analog signal can be wheeled. Through the internal 社 社 & the paper 峨 magnified 'the county magnified 峨 sent JL signal conversion circuit to convert the action. Another object of the present invention is to provide a numerical correction device for a type of digital conversion circuit of a kind of analog-to-digital converter towel with a large-scale converter, because such a digital-to-digital conversion circuit uses a capacitive charge charging and discharging structure. Capacitance can cause numerical errors that cause accuracy. Therefore, the design towel is subjected to the calculation of the method, and then the result of the calculation of the algorithm is implemented by a hardware circuit, so that the error caused by the capacitance value can be corrected. In order to achieve the above object, the signal conversion system architecture in the digital converter with the amplification function provided by the present invention further comprises: an instrument amplification circuit, a sample holding circuit, a analog signal comparison circuit, a digital signal control circuit, a switch array, a capacitance-charged digital analog circuit and a capacitance value correction circuit, wherein the instrument amplification circuit amplifies the analog signal 5 .201044792 and then inputs the signal to the signal conversion circuit. [Embodiment] Referring to FIG. 1, a preferred embodiment of the analog-to-digital signal conversion system having the amplification function of the present invention comprises: an instrumentation amplifier (IA) and a signal converter η. The instrumentation amplifier 10 is composed of an operational amplifier, which is a simple amplifier whose amplification factor can be adjusted by an external resistor to determine the value of the amplifier. Therefore, the instrumentation amplifier (ΙΑ) 10 can amplify the small signal. . Moreover, the analog digital signal converter 11 is used to convert the analog signal after amplification into a digital signal that can be processed by the processor. Figure 2 is a preferred embodiment of the analog digital signal conversion system u of the present invention. As shown in FIG. 2, the signal converter π further includes: a sample and hold circuit 11 , an analog signal comparator 112 , a digital signal controller 113 , a switch array 110 , a capacitance charge digital analog conversion circuit 114 , and a Capacitance value correction circuit 115. The sample and hold circuit 1U can filter the input signal to obtain a more correct signal. The analog signal comparator 112 can compare the amplified input signal with the feedback signal to obtain a control signal of the digital signal controller. The digital signal controller 113 can obtain the output of the converter 6 201044792 tens digit code. The switch array 110 prevents signal attenuation. The capacitively charged digital analog converter 114' converts the feedback digital signal into an analog signal and compares it with the input signal. The capacitance value correction circuit 115 can self-correct the capacitance value to obtain a more accurate value. The capacitor-charged digital analog converter further comprises eleven sets of capacitors, and the digital signal can be converted into an analog signal by the characteristics of the capacitor charging and discharging. Referring to FIG. 3, the sample-and-hold circuit 111 further includes: a first signal sampling. The capacitor 116, a first operational amplifier 117, a second signal holding capacitor 118 and a second operational amplifier 119. The first signal sampling capacitor 116 and the second signal holding capacitor 118 can perform signal sampling and holding operations; and the first operational amplifier 117 and the second operational amplifier 119 have signal buffering functions. And the two sets of sampling capacitors 116, 118 and the two sets of operational amplifiers 117, 119 can be exchanged for sampling and holding. As shown in FIG. 3, the sampling and holding circuit (SampUng Holding Circuit) 111 is configured to receive the clock signal 4〇1, and when the positive half cycle comes, the first signal sampling capacitor 116 and the first operational amplifier η are sampled. The second signal sampling capacitor 118 and the second operational amplifier 119 perform the holding operation; otherwise, when the negative half cycle of the pulse signal 4Q1 comes, the first signal sampling capacitor 116 and the first material amplifier m perform the lining action. 7 201044792 The second signal sampling capacitor 118 and the second operational amplifier 119 perform a sampling operation, so that the double sampling function can be achieved by repeating the operation. Referring to FIG. 4, the analog signal comparator 112 can compare the amplified analog signal with the feedback signal to obtain the control signal of the digital signal controller 113. The analog signal comparator 112 further includes a bias circuit 301 and a differential pair comparator main circuit 302. The differential pair comparator main circuit 302 is supplied with a stable bias value via the bias circuit 301, and if the bias value is unstable, the differential operation of the comparator main circuit 302 is caused. The differential pair comparator main circuit 302 can receive the voltage of the bias circuit 301 and compare the two types of input signals to generate a digital control signal. If the analog signal value output by the sample hold circuit 111 is greater than the value of the feedback signal 402, the analog signal comparator 112 outputs a digital signal 〇. If the analog signal value output by the sample and hold circuit 111 is less than the value of the feedback signal 402, the analog signal comparator 112 will input the & digit field. The axis, _ the signal obtained by the signal comparator controls the action of the digital signal controller 113. Referring to FIG. 5, the digitization signal required for the immersion is controlled and the grid is relayed to generate the desired signal. The digital signal control 113 further includes: an upper sequence logic circuit and a lower sequence sugar circuit (2). The upper sequence logic circuit 12 〇 8 201044792 can generate a control signal to control the lower sequence logic circuit; and the lower sequence logic _ 121 can generate a feedback signal and a tens digit code after receiving the control signal. The digital signal controller 113 is mainly controlled by the upper level shift register 12 to control the lower register m. The principle of the operation of the control n is that the initial value is first set to the logic circuit 120 via the upper sequence, the highest bit (MSB, M〇st ❹ SigmilcantBit) is set to 1, and the other bits are set to 〇, that is, the value is set to one. The bit value is 10000000000. If the output signal of the analog signal comparator is 1 'the highest bit (MSB) will be reset to 〇 and will remain until the entire age of the comparison; otherwise, the finer than the taste (4) 112 of the output signal is 1 ' The highest bit (MSB) will remain as 〗. The rest of the bits are deduced by analogy. After the first bit comparison is completed, the second bit is compared. The time of one clock determines the value of one bit, and the highest D bit (MSB) at the beginning. It is first set to Bu and then decided to keep 1 or change to 〇 according to the output of the analog signal comparator U2. Referring to the figure ’, the capacitance value correcting circuit 115 further includes a correction capacitor 201 and a correction circuit DAC (Digital/Anal 〇gC〇nverter, digital/analog converter) 202. Through the algorithm (Aig〇rithm), the capacitance correction value can be calculated. That is, each capacitance error value of the capacitance charge type is calculated, and then added to the output part to be charged and discharged, so that the capacitance charge type 9 201044792 Each capacitance error value of the bit analog converter is corrected to correct the charge and discharge level problems caused by the error value, and to ensure its accuracy. The correction circuit DAC 202 can convert the correction code into an analog voltage and then input it to the correction capacitor, so that an accurate signal can be obtained.
訊號經由儀表放大器1〇放大之後，將此訊號輸入該取樣 保持電路m，該取樣保持電路lu會將此類比訊號進行過 遽之動作，卩餅鮮叙峨，織·龍舰至類比 訊號比較器112。在比較出賴值之後可獲得丨與G之數位 訊號，此數位訊號是絲控制數位訊號控制器113之動作。 數位訊號控制H 113之輸出結果再送至關_ 11〇，此該 開關陣列11G是用來防峨衰減而造錢容電荷式數位 類比轉換H 114之錯誤動作。在加人關_⑽後，可將 R號轉在UV之準位’接著再將訊號送回至電容電荷式 數位類比職n m，經由魏之後，再與取細爾⑴ 之輸出結料行時，之後耻概果輸人至數健號控制 :113 ’以此電物_，經過十—辦脈辭之後方能 得到所需之十位元數位碼。 本發明具有低複雜度、低功率消耗、自我校正電路及訊 號放大之優點’此轉換衫统轉適合朗在民生及醫療工 .201044792 業使用上。 該較佳具體實施例僅為了易於說明本發明之技術内 容’而並非將本發明狹義地限制於該實施例，凡依本發明之 精神及以下申請專利内容所列之情況所做之種種變化實施 均屬本發明之範圍。 Ο 【圖式簡單說明】 圖1為本發明具有放大功能之類比數位訊換轉器示意圖； 圖2為本發明類比數位訊號轉換器之架構示意圖； 圖3為本發明取樣保持電路示意圖； 圖4為本發明類比訊號比較器示意圖； 圖5為本發明數位訊號控制器之架構示意圖； 圖6為本發明電容數值校正電路示意圖； 【主要元件符號說明】 10 儀表放大器 11 類比數位訊號轉換器 110 開關陣列 111 取樣保持電路 112 類比訊號比較器 11 201044792 113 數位訊號控制器 114 115 116 117 118 119 120 Ο 121 201 202 301 302 401 402 電容電荷式數位類比訊號轉換器 電容數值校正電路 第一取樣保持電容 第一取樣保持運算放大器 第二取樣保持電容 第二取樣保持運算放大器 上層序向邏輯電路 下層序向邏輯電路 校正電容 校正電路DAC 偏壓電路 差動對比較器主電路 時脈訊號 回授訊號 Ο 12After the signal is amplified by the instrumentation amplifier 1〇, the signal is input to the sample-and-hold circuit m, and the sample-and-hold circuit lu will perform such an action on the analog signal, and the cake is narrated, and the weaving dragon-to-class analog signal comparator 112. The digital signal of 丨 and G can be obtained after comparing the lag values, and the digital signal is the action of the wire control digital signal controller 113. The output of the digital signal control H 113 is sent to the off state _ 11 〇, and the switch array 11G is used to prevent the 峨 attenuation and make the charge-type digital analog conversion H 114 wrong action. After adding _(10), you can turn the R number to the UV level' and then send the signal back to the capacitance-charged digital analog class nm. After the Wei, and then take the output of the fine (1) After that, the shame results in the number of people to control the number: 113 'this electric object _, after the ten-doing pulse, can get the required tens digit code. The invention has the advantages of low complexity, low power consumption, self-correcting circuit and signal amplification. This conversion shirt is suitable for use in the people's livelihood and medical workers. 201044792. The preferred embodiment is merely illustrative of the technical content of the present invention, and is not intended to limit the invention to the embodiment, and various changes are made in accordance with the spirit of the present invention and the circumstances listed in the following claims. All are within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of an analog digital converter with an amplification function according to the present invention; FIG. 2 is a schematic diagram of an analog digital converter of the present invention; FIG. 3 is a schematic diagram of a sample and hold circuit of the present invention; FIG. 5 is a schematic structural diagram of a digital signal controller according to the present invention; FIG. 6 is a schematic diagram of a capacitor numerical value correcting circuit according to the present invention; [Signal Description of Main Components] 10 Instrumentation Amplifier 11 Analog Digital Signal Converter 110 Switch Array 111 Sample and Hold Circuit 112 Analog Signal Comparator 11 201044792 113 Digital Signal Controller 114 115 116 117 118 119 120 Ο 121 201 202 301 302 401 402 Capacitance Charge Digital Analog Signal Converter Capacitance Value Correction Circuit First Sample Hold Capacitor A sample and hold operational amplifier second sample hold capacitor second sample hold operational amplifier upper sequence to logic circuit lower sequence to logic circuit correction capacitance correction circuit DAC bias circuit differential pair comparator main circuit clock signal feedback signal Ο 12