CN107994903B

CN107994903B - Analog-to-digital conversion circuit and pipeline analog-to-digital converter

Info

Publication number: CN107994903B
Application number: CN201711350635.4A
Authority: CN
Inventors: 殷秀梅; 杨培
Original assignee: Beijing Tebang Microelectronic Technology Co ltd
Current assignee: Beijing Tebang Microelectronic Technology Co ltd
Priority date: 2017-12-15
Filing date: 2017-12-15
Publication date: 2021-07-16
Anticipated expiration: 2037-12-15
Also published as: CN107994903A

Abstract

The disclosure relates to an analog-to-digital conversion circuit and a pipeline analog-to-digital converter. The circuit is a stage of a pipeline analog-to-digital converter, and comprises: the system comprises an SADC module, an MDAC module, a control and measurement module, a MUX module and a correction module, wherein the MUX module is connected between the SADC module and the MDAC module; the control and measurement module is connected with the MUX module and outputs control, enable and correction signals; the correction module is connected with the control and measurement module. Under the control of the enable signal, the MUX module outputs a digital signal or a control signal to the MDAC module and the correction module; when the MUX module outputs the digital signal, the correction module corrects the output digital signal according to the capacitor mismatch parameter. According to the embodiment of the disclosure, the capacitance mismatch parameter of the pipeline analog-to-digital converter can be obtained and the output digital signal can be corrected, so that the high-precision pipeline analog-to-digital converter is realized with lower circuit complexity.

Description

Analog-to-digital conversion circuit and pipeline analog-to-digital converter

Technical Field

The present disclosure relates to the field of integrated circuits, and in particular, to an analog-to-digital conversion circuit and a pipeline analog-to-digital converter.

Background

The pipeline Analog-to-Digital Converter (ADC) is composed of several stages of modules with similar functions, each module including a sub Analog-to-Digital conversion (SADC) module and a Digital-to-Analog conversion and amplification (MDAC) module, etc.

The precision of the pipeline ADC is closely related to the signal processing precision of the MDAC module, and the working parameters of the MDAC module influence the signal processing precision of the MDAC module. For example, non-idealities in the capacitance matching in the MDAC module have a large impact on the accuracy of the MDAC module. The effect of capacitance mismatch on MDAC output error has two aspects: one is a mismatch term independent of the SADC quantization result, i.e., gain error; the other is a mismatch term related to the SADC quantization result. Both errors can cause the influence of reduction of precision of the pipeline ADC, rising of each subharmonic and the like. In the multi-bit MDAC structure, the mismatch term effect on the quantization result of SADC is more significant. In order to ensure the precision of the pipeline ADC, the capacitance matching precision is required to meet the design requirement.

In the related art, a large design margin (for example, an increase in capacitance area) is generally left, or capacitance compensation is performed by an analog or digital manner. However, increasing the capacitance area increases the input load and the operational amplifier (OPA) load of the pipeline ADC, which not only increases the power consumption of the pipeline ADC, but also significantly increases the design difficulty of other modules such as the sampling switch and the OPA; the adoption of the analog capacitance compensation mode needs a complex switched capacitor network, thereby obviously increasing the complexity of an analog circuit and improving the difficulty of layout; the digital capacitance compensation mode has high requirement on the measurement precision of MDAC capacitance mismatch, a traditional measurement scheme needs to input a plurality of high-precision direct-current voltages to an ADC (analog to digital converter) of a production line, and the test environment cost is high.

Disclosure of Invention

In view of this, the present disclosure provides an analog-to-digital conversion circuit, which can measure and correct a capacitance mismatch error at a low cost, and implement a high-precision pipeline analog-to-digital converter.

According to an aspect of the present disclosure, there is provided an analog-to-digital conversion circuit, the circuit being a stage of a pipelined analog-to-digital converter, the circuit comprising: a sub-analog-to-digital conversion SADC module, an analog-to-digital conversion and amplification MDAC module, a control and measurement module, a multiplexer MUX module and a correction module,

an input end of the SADC module inputs an analog signal, and an output end of the SADC module outputs a first digital signal after analog-to-digital conversion;

the MUX module is connected between the SADC module and the MDAC module, one input end of the MUX module inputs the first digital signal, the other input end of the MUX module inputs the control signal, and an enable end of the MUX module inputs an enable signal;

one input end of the MDAC module inputs the analog signal, the other input end of the MDAC module is connected with the output end of the MUX module, and the output end of the MDAC module outputs a residual error signal;

the control and measurement module is connected to the MUX module, a first output end outputs a control signal, a second output end outputs an enable signal, and a third output end outputs a correction signal;

the correction module is connected to the control and measurement module, one input end of the correction module is connected with the output end of the MUX module or the first digital signal output by the SADC module, the other input end of the correction module is input with the correction signal, and the output end of the correction module outputs a second digital signal,

wherein the output terminal of the MUX module outputs the first digital signal or the control signal to the MDAC module under the control of the enable signal,

the correction module corrects the first digital signal according to the capacitance mismatch parameter and outputs the corrected second digital signal.

In one possible implementation, the circuit further comprises an analog-to-digital conversion ADC module,

the ADC module is connected to the MDAC module and the control and measurement module, the input end of the ADC module inputs the residual difference signal, and the output end of the ADC module outputs a third digital signal after analog-to-digital conversion;

and the input end of the control and measurement module inputs the third digital signal.

In one possible implementation, the ADC module includes an SADC module of a next stage analog-to-digital conversion circuit of the pipeline analog-to-digital converter.

In a possible implementation manner, when the output end of the MUX module outputs the control signal, the analog signal is switched to a first analog voltage, and the control and measurement module determines the capacitance mismatch parameter according to the control signal and the third digital signal and generates a correction signal including the capacitance mismatch parameter.

In one possible implementation, the first analog voltage is at a zero level.

In one possible implementation manner, the control signal includes a plurality of digital signals sequentially output, and the number of the plurality of digital signals is the same as the number of sampling capacitors of the MDAC module.

In a possible implementation manner, the determining, by the control and measurement module, the capacitance mismatch parameter according to the control signal and the third digital signal includes:

measuring a third digital signal output by the ADC module for multiple times during the period that the MUX module outputs the current digital signal of the control signal, and acquiring multiple measurement signal values;

determining an average of the plurality of measurement signal values as the measurement signal corresponding to the current digital signal;

and determining the capacitance mismatch parameter according to a plurality of digital signals of the control signal and a plurality of measuring signals respectively corresponding to the plurality of digital signals of the control signal.

In one possible implementation, the sum of the digits of the normalized control signal is in the same interval as the value of the normalized analog signal.

In one possible implementation, the number of bits of the control signal is the same as the number of sampling capacitors of the MDAC module.

In one possible implementation, the control signal comprises different m digital signals,

each bit of the first signal and each bit of the second signal in the m digital signals are different by 2 bits, and other bits are the same;

each bit of m/2-1 third signals in the m digital signals and each bit of the first signals are different by 2 bits, and other bits are the same;

each bit of m/2-1 fourth signals in the m digital signals and each bit of the second signals are different by 2 bits, and other bits are the same,

wherein m is a natural number greater than 1.

In one possible implementation, determining the capacitance mismatch parameter according to a plurality of digital signals of the control signal and a plurality of measurement signals respectively corresponding to the plurality of digital signals of the control signal includes:

performing addition and subtraction operations on the plurality of measurement signals for a plurality of times respectively to obtain a first mismatch parameter of a plurality of sampling capacitors in the MDAC module relative to a first capacitor in the plurality of sampling capacitors;

obtaining a second mismatch parameter of the plurality of sampling capacitors relative to a capacitor mean value of the plurality of sampling capacitors according to the first mismatch parameter;

determining the second mismatch parameter as the capacitive mismatch parameter,

and the number of addition and subtraction operations is the number of sampling capacitors in the MDAC module minus 1.

According to another aspect of the present disclosure, there is provided a pipeline analog-to-digital converter, each stage of which includes an analog-to-digital conversion circuit as described above.

According to the analog-to-digital conversion circuit and the pipeline analog-to-digital converter in each aspect of the disclosure, the capacitance mismatch parameter of the pipeline analog-to-digital converter can be obtained through the control and measurement module, the first digital signal output by the SADC module is corrected through the correction module, and the corrected second digital signal is output, so that the high-precision pipeline analog-to-digital converter is realized with lower circuit complexity.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

Fig. 1 is a schematic diagram of a first-stage analog-to-digital conversion circuit of a pipeline analog-to-digital converter according to the related art.

Fig. 2a and 2b are schematic diagrams of a circuit structure of an MDAC module of an analog-to-digital conversion circuit according to the related art and a circuit timing thereof, respectively.

Fig. 3 is a schematic diagram of a transmission curve of an MDAC module of an analog-to-digital conversion circuit according to the related art.

Fig. 4a and 4b are schematic diagrams of an analog-to-digital conversion circuit, respectively, shown according to an exemplary embodiment of the present disclosure.

Fig. 5a is a flowchart illustrating steps for determining a capacitance mismatch parameter according to an exemplary embodiment of the present disclosure.

Fig. 5b is a schematic diagram illustrating the determination of a capacitance mismatch parameter according to an exemplary embodiment of the present disclosure.

Fig. 6 is a schematic diagram illustrating an MDAC module transmission curve of an analog-to-digital conversion circuit according to an exemplary embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.

Fig. 1 is a schematic diagram of a first-stage analog-to-digital conversion circuit of a pipeline analog-to-digital converter according to the related art. For example, the pipelined ADC may include several stages of analog-to-digital conversion circuits with similar functions, as shown in fig. 1, an analog-to-digital conversion circuit 10 according to the related art may include:

a sub-analog-to-digital conversion (SADC) module 101, wherein an initial signal V is input to an input terminal of the SADC module 101_in0The output end outputs a digital signal Dout0 after analog-to-digital conversion; wherein if the first stage analog-to-digital conversion circuit is not adopted, V_in0Is an analog signal provided by a former-stage analog-to-digital conversion circuit;

a digital-to-analog conversion and amplification (MDAC) module 102, the MDAC module 102 being connected to the SADC module 101, an input terminal of which inputs the initial signal V_in0The other input end inputs a digital signal Dout0, and the output end outputs a residual difference signal V_res0。

In one possible implementation, as shown in fig. 1, the MDAC module 102 may include a digital-to-analog converter (DAC), an adder, an operational amplifier (OPA), and a clock generator. The input end of the DAC inputs a digital signal Dout0, and the output end of the DAC is connected with one input end of the adder; the other input end of the adder inputs an initial signal V_in0With output connected to an operational amplifier OPAAn input end; residual signal V is output at the output end of OPA_res0(ii) a The clock generator outputs clock signals to the DAC, the adder, and the OPA, respectively.

For example, the initial signal V_in0The signals enter the SADC module 101 and the MDAC module 102 at the same time, coarse quantization (i.e., preliminary analog-to-digital conversion) is performed in the SADC module 101, for example, 1 to 4 bits are quantized, and the quantization result (digital signal Dout0) is sent to the MDAC module 102. MDAC module 102 converts the output of SADC module 101 into a different reference voltage, the initial signal V_in0After subtraction, the difference is amplified by several times by OPA to obtain residual signal V_res0And sending to the next stage for treatment.

Fig. 2a and 2b are schematic diagrams of a circuit structure of an MDAC module of an analog-to-digital conversion circuit according to the related art and a circuit timing thereof, respectively. Fig. 3 is a schematic diagram of a transmission curve of an MDAC module of an analog-to-digital conversion circuit according to the related art.

Fig. 2a shows an exemplary specific circuit structure of the MDAC module 102, and fig. 2b shows a clock signal of the MDAC module 102 shown in fig. 2 a. The clock signal may comprise two inverted clocks Φ₁And phi₂Wherein T is_clkIndicating the period of the system clock, C_S0,1-C_S0,nRepresenting the sampling capacitance, n represents the number of sampling capacitances (the number of sampling capacitances n is the same as the number of bits of the digital signal Dout0), C_stg02Representing the sampling capacitance of the second stage, C_F0Representing the feedback capacitance, V_rpAnd V_rnRespectively representing a positive reference voltage and a negative reference voltage.

In one possible implementation, as shown in FIG. 2a, at Φ₁Phase (e.g. phi)₁1/2 clock period T being high_clk)，V_in0Is sampled into each sampling capacitor C_S0,1-C_S0,nIn (1). End of sample (e.g., #)₁Low) is phi₁The respective switches are turned off. Phi₂Phase (e.g. phi)₂1/2 clock period T being high_clk) The switch is closed, at which time each capacitor C_S0,1-C_S0,nThe voltage of the lower plate is controlled by the output signal of the SADC module 101 according to the output of the SADC module 101Output signal (quantization result) to select V_rpOr V_rnThe digital-to-analog conversion in MDAC is thus achieved, resulting in the transmission curve shown in fig. 3. The OPA works in a closed loop negative feedback state, and according to the charge conservation and the working principle of the ideal OPA, the following can be obtained:

in the formula (1), V_res0Representing the residual signal, V, output by the MDAC module 102_in0Representing the input initial signal, d0_kRepresenting the k-th bit, d0, of the digital signal Dout0 of the SADC module 101_kIs in the range of [ -1, 1 [)]，C_S0,kRepresents the capacitance value of the kth sampling capacitor, k is an integer between 1 and n, C_F0Representing the capacitance value, V, of the feedback capacitor_refRepresenting the full-scale voltage of the pipeline ADC, the input signal range of the pipeline ADC should be [ -V ]_ref，V_ref]Within the range of (1).

The effect of capacitance mismatch on MDAC output error has two aspects: one is a mismatch term independent of the SADC quantization result, i.e. gain error

The other is a mismatch term related to SADC quantization result

Both errors can cause the influence of reduction of precision of the pipeline ADC, rising of each subharmonic and the like. In the multi-bit MDAC structure, the mismatch term effect on the quantization result of SADC is more significant. In order to ensure the precision of the pipeline ADC, the capacitance matching precision is required to meet the design requirement.

Fig. 4a and 4b are schematic diagrams of an analog-to-digital conversion circuit, respectively, shown according to an exemplary embodiment of the present disclosure. This circuit 40 is any stage of a pipelined ADC. As shown in fig. 4a and 4b, the circuit 40 includes: a sub analog to digital conversion SADC module 401, a digital to analog conversion and amplification MDAC module 402, a control and measurement module 405, a multiplexer MUX module 404, and a correction module 403.

Wherein, the input end of the SADC module 401 inputs the analog signal V_inThe output end outputs a first digital signal D after analog-to-digital conversion₁；

The MUX module 404 is connected between the SADC module 401 and the MDAC module 402, and has an input terminal for inputting the first digital signal D₁The other input end inputs a control signal D_ctrlThe enable end inputs an enable signal Cali _ en;

the MDAC module 402 inputs an analog signal V at an input terminal_inThe other input end inputs a first digital signal D₁And the output end outputs a residual difference signal V_res；

The control and measurement module 405 is connected to the MUX module 402, and a first output terminal outputs a control signal D_ctrlA second output terminal outputs an enable signal Cali _ en, and a third output terminal outputs a correction signal D₄；

The calibration module 403 is connected to the control and measurement module 405, and has an input terminal connected to the output terminal of the MUX module (as shown in FIG. 4 a) or connected to the first digital signal D output by the SADC module 401₁(as shown in FIG. 4 b), and the other input end inputs a correction signal D₄The output end outputs a second digital signal D₂。

Wherein, under the control of the enable signal Cali _ en, the output terminal of the MUX module 404 outputs the first digital signal D₁Or the control signal D_ctrlTo the MDAC module 402. For example, when the enable signal Cali _ en is 0, the first digital signal D is gated₁(ii) a When the enable signal Cali _ en is 1, the control signal D is gated_ctrl. Wherein the control signal D_ctrlMay be the same as the number of sampling capacitors of the MDAC module 402.

Wherein the correction module 403 is used for correcting the first digital signal D according to the capacitance mismatch parameter₁Correcting and outputting the corrected second digital signal D₂。

According to the analog-to-digital conversion circuit disclosed by the embodiment of the disclosure, the capacitance mismatch parameter of the pipeline analog-to-digital converter can be obtained through the control and measurement module, the first digital signal output by the SADC module is corrected through the correction module, and the corrected second digital signal is output, so that the high-precision pipeline analog-to-digital converter is realized with lower circuit complexity.

For example, the SADC module 401 and the MDAC module 402 may adopt the related art circuit structure, and the analog signal V_inSimultaneously enters an SADC module 401 and an MDAC module 402, and performs a preliminary analog-to-digital conversion in the SADC module 401 to obtain a conversion result (a first digital signal D)₁) Into the MDAC module 402. The MDAC module 402 converts the output of the SADC module 401 into different reference voltages, i.e., an analog signal V_inAfter subtraction, the difference is amplified by several times by OPA to obtain residual signal V_resAnd sending to the next stage for treatment. The MDAC module 402 may include a digital-to-analog converter (DAC), an adder, an operational amplifier (OPA), and a clock generator. Wherein the first digital signal D₁The same number of bits as the number of sampling capacitors of the MDAC module 402.

In one possible implementation, as shown in fig. 4a, the correction module 403 may be connected to an output of the MUX module 404. When the circuit is in the normal operation mode, the output terminal of the MUX module 404 outputs the first digital signal D₁The first digital signal D is input to an input terminal of the calibration module 403₁The output end outputs a second digital signal D₂. As shown in fig. 4b, the correction module 403 may also be connected to the output terminal of the SADC module 401, and directly input the first digital signal D₁The output end outputs a second digital signal D₂. The calibration module 403 can calibrate the signal D according to the capacitance mismatch parameter outputted from the control and measurement module₄Or stored capacitance mismatch parameter versus first digital signal D₁Correcting to output corrected second digital signal D₂。

In one possible implementation, the capacitance mismatch parameter of the analog-to-digital conversion circuit may be determined by a calibration test. The MUX module 404 may be controlled by the control and measurement module 405 such that the MUX module 404 outputs a control signal D during the test mode_ctrl。

In one possible implementation, the output of the MUX module 404 is controlledSystem signal D_ctrlTime, analog signal V_inSwitched to the first analog voltage, and the control and measurement module 405 controls the voltage according to the control signal D_ctrlAnd a third digital signal D₃Determining a capacitance mismatch parameter and generating a correction signal D comprising the capacitance mismatch parameter₄. Wherein, the first analog voltage may be at a zero level.

In the correction test, the analog signal V input to the analog-to-digital conversion circuit may be input_inShort-circuited to zero level (first analog voltage). Considering the DC offset at the input of an operational amplifier (OPA), the actual input analog signal V_inIt will be a static voltage close to zero level. Fig. 6 is a schematic diagram illustrating an MDAC module transmission curve of an analog-to-digital conversion circuit according to an exemplary embodiment of the present disclosure. As shown in the transmission curve of fig. 6, the analog signal V_inCan be divided into intervals of-4, -3, -2, -1, 0, 1, 2, 3, 4 and the like. Wherein, for the first stage analog-to-digital conversion circuit, the analog signal V_inNamely zero level; if not, the analog signal V is_inIs an analog signal (residual signal V) output by the previous stage analog-to-digital conversion circuit_res) The analog signal may be offset due to dc mismatch at the preceding stage.

In one possible implementation, the control signal D_ctrlThe device comprises a plurality of digital signals which are sequentially output, and the number of the digital signals is the same as that of sampling capacitors of the MDAC module.

During the calibration test, the control and measurement module 405 may generate a plurality of digital signals sequentially output through an internal state machine as the control signal D_ctrlAnd (6) outputting. The number of digital signals may be greater than or equal to the number of bits of the control signal (i.e., the number of sampling capacitors in the MDAC module 402) in order to enable the calculation of the capacitance mismatch parameter. For example, the control signal D_ctrlThere are m digital signals D_ctrl，jWherein j takes the value of 1-m, m>1; each digital signalD_ctrl，jComprising an n-bit number d_ijWherein i takes the value of 1-n, n>1, and m is more than or equal to n.

As mentioned above, the analog signal V actually input by the first stage analog-to-digital conversion circuit_inIt will be a static voltage close to zero level. In this case, the control signal D is used to ensure that the MDAC module 402 has a minimal effect on the measurement accuracy_ctrl，jThe value of each digit of (A) is required to ensure the residual signal V_resAs close to 0V as possible (e.g., V may be made_resLess than or equal to 0.5V). Therefore, the signal input by the ADC module of the next stage is also in the range close to 0V, so that the linearity and the precision of the ADC module of the next stage are better.

In this case, the normalized control signal D may be made_ctrl，jEach digit of (d)_ijSum of (1)_j(d_ij) With the normalized analog signal V_inWithin the same interval. For the first stage analog-to-digital conversion circuit, the analog signal V_inI.e. the quiescent voltage close to zero level, sum of the stage_j(d_ij) Can take the value of 0 and the normalized analog signal V_inIn the same interval, thereby ensuring the optimal working state of the MDAC module; if not the first stage analog to digital conversion circuit, there may be an input offset (residual signal V)_resOffset), normalized analog signal V_inPossibly in the interval 1, 0 or-1 of FIG. 6, then sum for that stage_j(d_ij) The value can be correspondingly set to 1, 0 or-1, thereby ensuring the optimal working state of the MDAC module.

According to the circuit structure of the MDAC module, and the residual difference signal is compared with the reference voltage (full-amplitude input voltage) V_refBy performing the normalization, the following formula (2) can be obtained:

in the formula (2), V_res，jIndicating that the control signal is D_ctrl，jResidual signal, V, output by time MDAC module 102_inWhich is representative of the analog signal that is input,d_ijrepresenting a digital signal D_ctrl，jI is an integer of 1 to n, d_ijIs in the range of [ -1, 1 [)]，C_S,iA capacitance value (for example, C) representing the ith sampling capacitance_FA capacitance value (e.g., 2C), V, representing the feedback capacitance_refRepresents the full input voltage (e.g., 1V) of the pipelined ADC;

in the formula (2), the first and second groups,

the dc gain a and the capacitance mismatch of the OPA can be expressed as the influence coefficients on the transmission characteristics of the stage.

As shown in fig. 4a and 4b, in one possible implementation, the circuit 40 further includes an analog-to-digital conversion ADC module 406, the ADC module 406 is connected to the MDAC module 402 and the control and measurement module 405, and the input end inputs the residual difference signal V_resAnd the output end outputs a third digital signal D after analog-to-digital conversion₃；

Wherein, the input end of the control and measurement module 405 inputs a third digital signal D₃。

For example, the ADC module 406 may be used to correct the residual signal V_resQuantization (analog-to-digital conversion) is performed to obtain a third digital signal D₃Is inputted into the correction module 403 so that the correction module 403 is based on the third digital signal D₃Calculating a capacitance mismatch parameter D₄。

In one possible implementation, the ADC module 406 may include an SADC module 401 of a next stage analog-to-digital conversion circuit of the pipeline analog-to-digital converter. That is, when the currently tested analog-to-digital conversion circuit is not the last stage of the pipeline ADC, the ADC module 406 may multiplex the SADC module 401 of the next stage analog-to-digital conversion circuit, and if the current analog-to-digital conversion circuit is not the last stage of the pipeline ADC, the ADC module 406 may multiplex the SADC module 401 of the next stage analog-to-digital conversion circuit, and may also use the whole of each stage after the current stage of the pipeline ADC as the ADC module 406, so as to implement the compensation signal V_resQuantization of (2); if the current analog-to-digital conversion circuit is the last stage of a pipelined ADC, a separate ADC stage may be usedADC block 406 to implement the residual signal V_resQuantization of (2). ADC module 406 may also be added to each stage of the analog-to-digital conversion circuit of the pipelined ADC, which is not limited by this disclosure.

Due to the third digital signal D₃I.e. residual signal V_resIf m residual signals V exist as the quantization result of (1)_res，jIn this case, equation (2) can be expressed as:

in the formula (3), D_3，jIs shown for the residual signal V_res，jThe quantized digital signal (third digital signal).

In a possible implementation manner, when the output end of the MUX module outputs the control signal, the correction module may determine the capacitance mismatch parameter according to the control signal and the third digital signal.

Fig. 5a is a flowchart illustrating steps for determining a capacitance mismatch parameter according to an exemplary embodiment of the present disclosure. As shown in fig. 5a, in a possible implementation manner, the determining, by the control and measurement module, the capacitance mismatch parameter according to the control signal and the third digital signal includes:

step S61, measuring the third digital signal output by the ADC module for multiple times during the period when the MUX module outputs the current digital signal of the control signal, and obtaining multiple measured signal values;

a step S62 of determining an average value of the plurality of measurement signal values as a measurement signal corresponding to the current digital signal;

step S63, determining the capacitance mismatch parameter according to the plurality of digital signals of the control signal and the plurality of measurement signals respectively corresponding to the plurality of digital signals of the control signal.

For example, during calibration test, the enable signal of the control and measurement module 405 changes (e.g., the enable signal Cali _ en ═ 1), and the control signal D is gated_ctrl. In this case, controlThe system and measurement module 405 may generate a plurality of digital signals D sequentially output through an internal state machine thereof_ctrl，j(j takes a value of 1-m) and inputs it into the MDAC module 402. Wherein each digital signal D_ctrl，jThe output is held for a certain time. It should be understood that the time can be preset according to actual needs, and the disclosure is not limited thereto.

As shown in FIGS. 4a and 4b, the current digital signal D is output at the MUX block 404_ctrl，jMeanwhile, the MDAC module 402 outputs a corresponding residual signal V_res，jThe ADC module 406 then processes the residual signal V_res，jQuantizing to obtain quantized third digital signal D_3，j。

In a possible implementation manner, the control and measurement module 405 may measure the third digital signal output by the ADC module 406 for multiple times to obtain multiple measurement signal values; further, an average value of a plurality of measurement signal values may be obtained, and the average value may be used as a final measurement signal (third digital signal D)_3，j). In this way, the accuracy of the measurement signal can be improved.

Fig. 5b is a schematic diagram illustrating the determination of a capacitance mismatch parameter according to an exemplary embodiment of the present disclosure. As shown in fig. 5b, for a plurality of digital signals D sequentially output_ctrl，j(j takes a value of 1 to m), steps S61 and S62 may be performed for each digital signal D_ctrl，jThe measurements were performed separately. If the number of the measured digital signals is less than the total number (m) of the digital signals, not completing the measurement of all the digital signals, returning to continue to execute the steps S61 and S62; if the number of the measured digital signals has reached the total number (m) of the digital signals, the measurement of all the digital signals has been completed, and step S63 may be performed.

Thus, a plurality of digital signals D are sequentially output_ctrl，j(j takes a value of 1 to m) are measured respectively, that is, after steps S61 and S62 are executed m times in a loop, the control and measurement module 405 may obtain m control signals D_ctrl，jCorresponding m measurement signals (third digital signal D)_3，j) And according to the m control signals D in step S63_ctrl，jAnd m third digital signals D_3，jA capacitance mismatch parameter is determined.

wherein m is a natural number greater than 1.

The first signal, the second signal, the third signal and the fourth signal in the m digital signals can be adjusted in any order.

The following is a pipelined ADC with an effective precision of 2-bit, where m is 8 and the sampling capacitor C_S,iThe capacitance nominal value of C is taken as an example to illustrate a specific calculation manner of the capacitance mismatch parameter of the analog-to-digital conversion circuit according to the present disclosure.

Can set 8 groups of control signals D in sequence_ctrl，j(1. ltoreq. j. ltoreq.8) as shown in Table 1:

TABLE 1

In one possible implementation, the control signal D may be made_ctrl，jEach digit of (d)_ijValues are sequentially taken according to the table 1 and substituted into the formula (3), so that the following can be obtained:

the definitions of the respective physical quantities in the formula (4) have been explained previously, and are not described repeatedly herein.

In one possible implementation, step S63 may include:

determining the second mismatch parameter as the capacitive mismatch parameter,

For example, the various equations in equation (4) may be differenced to retain a common sampling capacitance value (the first capacitance described above) (e.g., retain C)_S,8) It is possible to obtain:

in the formula (5), Δ D_3，j(1. ltoreq. j. ltoreq.8) represents the normalized third digital signal D₃(residual signal V)_resQuantized result of (D), where Δ D_3，8And may be defined as 0. It should be understood that other subtraction orders may be used, and the present disclosure is not limited thereto.

For equation (5), C_FThe capacitance value of the feedback capacitor is expressed by 2C, and each formula of formula (5) is substituted to obtain:

for equation (6), in a practical circuit, the operational amplifier DC gain A>>1, thus having K _A1, and C_S,iC, so that:

substituting the formula (7) into the formula (6) to simplify the formula, can obtain:

according to the formula (8), the respective capacitances C can be obtained_S,iRelative to C_S,8Obtaining a first mismatch parameter of the plurality of sampling capacitances relative to a first capacitance of the plurality of sampling capacitances):

normalization processing is carried out on the formula (9), and each sampling capacitor C can be obtained_S,iRatio B relative to the average of all sampled capacitances_i(i.e., obtaining a second mismatch parameter of the plurality of sampled capacitances relative to a mean of the capacitances of the plurality of sampled capacitances), and dividing the ratio B_iAs respective sampling capacitors C_S,iThe capacitance mismatch parameter of (a). As follows:

capacitance mismatch parameter B in equation (10)_iMay be greater than 1 or less than 1. If B is present_i>1, then represents the corresponding sampling capacitance C _S,i2, partial enlargement; on the contrary, if B_i<1, then represents the corresponding sampling capacitance C_S,iIs small.

It will be understood by those skilled in the art that the foregoing is merely illustrative of the principles of calculating the capacitance mismatch parameter according to the present disclosure and is not to be construed as limiting the present disclosure.

It will be understood by those skilled in the art that the control and measurement module may implement the mismatch parameter B in various hardware or software manners known in the art_iThe present disclosure is not limited thereto.

In a possible wayIn an implementation manner, the control and measurement module 405 obtains the capacitance mismatch parameter B_iThen, the capacitance mismatch parameter B can be determined_iGenerating a correction signal D₄And will correct the signal D₄To the correction module 403. The calibration module 403 receives the calibration signal D₄Then, the capacitance mismatch parameter B can be stored therein_i。

After the calibration test is completed, the enable signal of the control and measurement module 405 may be changed (e.g., the enable signal Cali _ en ═ 0), and the first digital signal D is gated₁And make the input analog signal V_inWhen the analog voltage is changed to the normal analog voltage, the analog-to-digital conversion circuit exits the correction test mode.

In this case, a normal operation mode can be entered, the analog signal V_inConverted into a first digital signal D by an SADC module 401₁(ii) a D of MUX module 404_out1For outputting a first digital signal D₁(ii) a First digital signal D₁After entering the calibration module 403, the calibration module 403 is configured to calibrate the capacitor mismatch parameter B_iFor the first digital signals D respectively₁Each bit is correspondingly corrected. After being corrected, the corrected second digital signal D can be output₂. The present disclosure is not limited to a particular manner of correction. By the method, the precision of the pipeline analog-to-digital converter can be effectively improved.

According to the analog-to-digital conversion circuit disclosed by the embodiment of the disclosure, when the measurement is corrected, the input analog signal only needs to be a high-precision direct-current voltage signal (such as zero level) which is easy to obtain, so that the circuit complexity is reduced; moreover, the circuit complexity of the correction module and the control and measurement module is low, and the circuit complexity of the whole analog-digital conversion circuit is reduced.

According to the analog-to-digital conversion circuit disclosed by the embodiment of the disclosure, during a correction test, the voltage of a residual difference signal output by an MDAC module of a front-stage analog-to-digital conversion circuit is near 0, so that the nonlinear influence of the gain of the MDAC operational amplifier of the current stage is effectively reduced, the nonlinear effect influence of the measurement of an ADC module of a rear-stage analog-to-digital conversion circuit is effectively reduced, and the precision of effective measurement is ensured.

The analog-to-digital conversion circuit according to the embodiment of the disclosure is not limited to the MDAC module of the first stage analog-to-digital conversion circuit of the pipeline ADC, and can be applied to the MDAC modules of the analog-to-digital conversion circuits of the pipeline ADC, so as to respectively correct the MDAC modules of the stages.

According to an embodiment of the present disclosure, there is also provided a pipeline analog-to-digital converter, each stage of which includes the analog-to-digital conversion circuit described above, respectively.

The specific manner in which the various blocks perform operations with respect to the pipelined analog-to-digital converter has been described in detail in relation to embodiments of the analog-to-digital conversion circuit and will not be elaborated upon here.

Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein were chosen in order to best explain the principles of the embodiments, the practical application, or technical improvements to the techniques in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An analog-to-digital conversion circuit, wherein the circuit is a stage of a pipelined analog-to-digital converter, the circuit comprising: a sub-analog-to-digital conversion SADC module, an analog-to-digital conversion and amplification MDAC module, a control and measurement module, a multiplexer MUX module and a correction module,

the MUX module is connected between the SADC module and the MDAC module, one input end of the MUX module inputs the first digital signal, the other input end of the MUX module inputs a control signal, and an enable end of the MUX module inputs an enable signal;

the correction module corrects the first digital signal according to the capacitance mismatch parameter and outputs a corrected second digital signal;

wherein the circuit further comprises an analog-to-digital conversion (ADC) module,

the input end of the control and measurement module inputs the third digital signal;

when the output end of the MUX module outputs the control signal, the analog signal is switched to a first analog voltage, the control and measurement module determines the capacitance mismatch parameter according to the control signal and the third digital signal, and generates a correction signal comprising the capacitance mismatch parameter;

the number of bits of the control signal is the same as the number of sampling capacitors of the MDAC module.

2. The circuit of claim 1, wherein the ADC module comprises an SADC module of a next stage analog-to-digital conversion circuit of a pipeline analog-to-digital converter.

3. The circuit of claim 1, wherein the first analog voltage is at a zero level.

4. The circuit of claim 1, wherein the control signal comprises a plurality of digital signals sequentially output, and the number of the plurality of digital signals is the same as the number of sampling capacitors of the MDAC module.

5. The circuit of claim 4, wherein the control and measurement module determines the capacitance mismatch parameter from the control signal and the third digital signal, comprising:

6. A circuit as claimed in claim 4, characterized in that the sum of the digits of the bits of the normalized control signal lies in the same interval as the value of the normalized analog signal.

7. The circuit according to any of claims 5-6, wherein the control signal comprises different m digital signals,

m/2-1 third signals in the m digital signals are different from each bit of the first signal in terms of 2 bits, and other bits are the same;

m/2-1 fourth signals in the m digital signals are different from each bit of the second signal in 2 bits, and other bits are the same,

wherein m is a natural number greater than 1.

8. The circuit of claim 5, wherein determining the capacitance mismatch parameter from a plurality of digital signals of the control signal and a plurality of measurement signals respectively corresponding to the plurality of digital signals of the control signal comprises:

determining the second mismatch parameter as the capacitive mismatch parameter,

9. A pipeline analog-to-digital converter, characterized in that each stage of the pipeline analog-to-digital converter comprises an analog-to-digital conversion circuit according to any one of claims 1 to 8, respectively.