TWI851135B - Fabricating method of carrier strucure - Google Patents
Fabricating method of carrier strucure Download PDFInfo
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- TWI851135B TWI851135B TW112113498A TW112113498A TWI851135B TW I851135 B TWI851135 B TW I851135B TW 112113498 A TW112113498 A TW 112113498A TW 112113498 A TW112113498 A TW 112113498A TW I851135 B TWI851135 B TW I851135B
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Abstract
Description
本發明係有關一種半導體製程,尤指一種用以承載晶片之承載結構之製法。 The present invention relates to a semiconductor manufacturing process, in particular to a method for manufacturing a supporting structure for supporting a chip.
目前應用於晶片封裝領域之技術,包含有例如晶片尺寸構裝(Chip Scale Package,簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached,簡稱DCA)或多晶片模組封裝(Multi-Chip Module,簡稱MCM)等型態的封裝模組。隨著終端產品的功能需求增加,半導體晶片需具備更多的輸入/輸出(I/O)接點,因而用於承載半導體晶片的封裝基板之外接墊之數量亦需相對應增加。 The technologies currently used in the chip packaging field include chip scale package (CSP), direct chip attached (DCA) or multi-chip module (MCM) packaging modules. As the functional requirements of end products increase, semiconductor chips need to have more input/output (I/O) contacts, so the number of pads outside the packaging substrate used to carry semiconductor chips also needs to increase accordingly.
圖1係為習知封裝基板1之剖視圖。如圖1所示,該封裝基板1係包括一核心層10,其具有相對之第一側10a及第二側10b,且該核心層10之第一側10a與第二側10b分別形成有線路結構11,其中,該線路結構係包含複數絕緣層111及複數形成於各該絕緣層111上之線路層11a,且該核心層10係具有複數連通該第一側10a與第二側10b之導電通孔100,以電性連接該些線路層11a,另該些線路層11a係透過導電盲孔110電性連接,並於各該導電盲孔110上設有電性接觸墊112。
FIG. 1 is a cross-sectional view of a conventional package substrate 1 . As shown in FIG1 , the package substrate 1 includes a
惟,習知封裝基板1中,該電性接觸墊112之寬度大於該導電盲孔110之寬度,致使該電性接觸墊112佔用該絕緣層111之表面,使該線路層11a於該
絕緣層111上之佈設空間受限,因而不利於佈設高密度之線路層11a,故難以增加電子產品之功能。
However, in the known package substrate 1, the width of the
因此,如何克服上述習知技術的缺失,實已成目前亟欲解決的課題。 Therefore, how to overcome the above-mentioned lack of knowledge and skills has become an urgent issue to be solved.
鑑於上述習知技術之種種缺失,本發明係提供一種承載結構之製法,係包括:提供一基板本體,其最外側係配置一第一絕緣層;形成第二絕緣層於該第一絕緣層上,且該第二絕緣層係形成有至少一外露該第一絕緣層之開口;於該開口之第一絕緣層中形成盲孔,以令該開口連通該盲孔;移除該第一絕緣層於該盲孔中之部分材質,使該開口之寬度小於該盲孔之寬度;以及形成導電盲孔於該盲孔中,且形成接點線路於該開口中之該導電盲孔上,使該接點線路電性連接該導電盲孔,其中,該接點線路之寬度係小於該導電盲孔之寬度。 In view of the above-mentioned deficiencies of the prior art, the present invention provides a method for manufacturing a supporting structure, comprising: providing a substrate body, the outermost side of which is configured with a first insulating layer; forming a second insulating layer on the first insulating layer, and the second insulating layer is formed with at least one opening exposing the first insulating layer; forming a blind hole in the first insulating layer of the opening so that the first insulating layer The opening is connected to the blind hole; a portion of the material of the first insulating layer in the blind hole is removed so that the width of the opening is smaller than the width of the blind hole; and a conductive blind hole is formed in the blind hole, and a contact line is formed on the conductive blind hole in the opening so that the contact line is electrically connected to the conductive blind hole, wherein the width of the contact line is smaller than the width of the conductive blind hole.
前述之製法中,該二絕緣層上復形成有外露該第一絕緣層之溝槽,以於該溝槽中形成電性連接該接點線路之導電跡線。例如,該導電跡線之表面係低於該第二絕緣層之表面。 In the aforementioned manufacturing method, a trench is formed on the second insulating layer to expose the first insulating layer, so as to form a conductive trace electrically connected to the contact line in the trench. For example, the surface of the conductive trace is lower than the surface of the second insulating layer.
前述之製法中,該接點線路之表面係低於該第二絕緣層之表面。 In the aforementioned manufacturing method, the surface of the contact line is lower than the surface of the second insulating layer.
前述之製法中,該接點線路之寬度與該導電盲孔之寬度係相差3微米。 In the aforementioned manufacturing method, the width of the contact line and the width of the conductive blind hole differ by 3 microns.
前述之製法中,該第一絕緣層於該盲孔中之部分材質係藉由除膠製程移除。 In the aforementioned manufacturing method, part of the material of the first insulating layer in the blind hole is removed by a debonding process.
前述之製法中,復包括形成金屬材於該第二絕緣層上及該盲孔與該開口中,再移除該第二絕緣層上之該金屬材,以令該盲孔中之該金屬材作為該導電盲孔,且該開口中之該金屬材作為該接點線路。例如,該第二絕緣層上之該金屬材係採用蝕刻方式移除。進一步,該蝕刻方式係移除該金屬材之厚度4~6微米。 The aforementioned manufacturing method further includes forming a metal material on the second insulating layer and in the blind hole and the opening, and then removing the metal material on the second insulating layer so that the metal material in the blind hole serves as the conductive blind hole, and the metal material in the opening serves as the contact line. For example, the metal material on the second insulating layer is removed by etching. Furthermore, the etching method removes 4 to 6 microns of the thickness of the metal material.
前述之製法中,該基板本體復包含一核心層,其具有相對之第一側與第二側、及至少一連通該第一側與第二側之導電通孔,以令該第一絕緣層形成於該核心層之第一側及/或第二側上。 In the aforementioned manufacturing method, the substrate body further includes a core layer having a first side and a second side opposite to each other, and at least one conductive through hole connecting the first side and the second side, so that the first insulating layer is formed on the first side and/or the second side of the core layer.
由上可知,本發明之承載結構之製法,主要藉由該接點線路之寬度小於該導電盲孔之寬度,使該接點線路不會佔用該第一絕緣層之表面,以利於佈設更多導電跡線於該第一絕緣層上,故相較於習知技術,本發明能有效增加佈線密度,以利於增加電子產品之功能。 As can be seen from the above, the manufacturing method of the supporting structure of the present invention mainly makes the width of the contact line smaller than the width of the conductive blind hole, so that the contact line will not occupy the surface of the first insulating layer, so as to facilitate the layout of more conductive traces on the first insulating layer. Therefore, compared with the prior art, the present invention can effectively increase the wiring density, so as to facilitate the increase of the functions of electronic products.
1:封裝基板 1:Packaging substrate
10,20:核心層 10,20: Core layer
10a,20a:第一側 10a,20a: First side
10b,20b:第二側 10b,20b: Second side
100,200:導電通孔 100,200: Conductive vias
11:線路結構 11: Circuit structure
11a,201,202:線路層 11a,201,202: Circuit layer
110,240:導電盲孔 110,240: Conductive blind vias
111:絕緣層 111: Insulation layer
112:電性接觸墊 112: Electrical contact pad
2:承載結構 2: Load-bearing structure
2a:基板本體 2a: Substrate body
2b:佈線層 2b: Wiring layer
21:第一絕緣層 21: First insulating layer
210:盲孔 210: Blind hole
22:第二絕緣層 22: Second insulation layer
220:開口 220: Open mouth
221:溝槽 221: Groove
23:導電層 23: Conductive layer
24:金屬材 24:Metal material
25:導電跡線 25: Conductive traces
250:接點線路 250: Contact line
D1,D2,R1,R2:寬度 D1,D2,R1,R2:Width
圖1係為習知封裝基板之剖視圖。 Figure 1 is a cross-sectional view of a conventional packaging substrate.
圖2A至圖2E係為本發明之承載結構之製法之剖面示意圖。 Figures 2A to 2E are cross-sectional schematic diagrams of the manufacturing method of the supporting structure of the present invention.
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The following is a specific and concrete example to illustrate the implementation of the present invention. People familiar with this technology can easily understand other advantages and effects of the present invention from the content disclosed in this manual.
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限 定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」、「第一」、「第二」、「一」等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。 It should be noted that the structures, proportions, sizes, etc. depicted in the drawings attached to this specification are only used to match the contents disclosed in the specification for understanding and reading by people familiar with this technology, and are not used to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effect and purpose that can be achieved by the present invention. At the same time, the terms such as "above", "first", "second", "one" etc. used in this specification are only for the convenience of description and are not used to limit the scope of implementation of the present invention. Changes or adjustments in their relative relationships shall also be regarded as the scope of implementation of the present invention without substantially changing the technical content.
圖2A至圖2E係為本發明之承載結構2之製法之剖面示意圖。
Figures 2A to 2E are cross-sectional schematic diagrams of the manufacturing method of the supporting
如圖2A所示,提供一包含有核心層20與第一絕緣層21之基板本體2a,該核心層20係具有相對之第一側20a及第二側20b,並於該第一側20a及第二側20b上分別設置有該第一絕緣層21,且於該核心層20之第一側20a及第二側20b之第一絕緣層21中分別佈設有線路層201,202。接著,於最外側之第一絕緣層21上形成一第二絕緣層22。
As shown in FIG. 2A , a
於本實施例中,該核心層20可為包含雙順丁烯二酸醯亞胺/三氮阱(Bismaleimide triazine,簡稱BT)、具玻纖之預浸材(Prepreg,簡稱PP)之有機聚合板材或其它板材,且該核心層20係具有複數連通該第一側20a與第二側20b之導電通孔200,以令該導電通孔200電性連接該些線路層201,202。例如,該導電通孔200係為實心金屬柱體,其形狀為以尖端相疊接之雙錐柱;或者,該導電通孔亦可為中空柱狀,並於中空處填滿塞孔材料(圖未示),其中,該塞孔材料之種類繁多,如導電膠、油墨等,並無特別限制。應可理解地,有關該導電通孔之形狀繁多,如直圓柱、單錐狀或其它幾何形狀,並無特別限制。
In this embodiment, the
再者,該第一絕緣層21係為介電層,如聚對二唑苯(Polybenzoxazole,簡稱PBO)、聚醯亞胺(Polyimide,簡稱PI)、具玻纖之預
浸材(Prepreg,簡稱PP)或其它等介電材。應可理解地,可於該核心層20之第一側20a及第二側20b上分別設置有複數之第一絕緣層21,並於各層第一絕緣層21中係佈設層間電性相連之線路層201,202,而於本實施例中係以於該核心層20之第一側20a及第二側20b上分別設置有單一第一絕緣層21進行說明。
Furthermore, the first
又,該第二絕緣層22係為感光成像(photosensitive imaging)層,且該第二絕緣層22係形成有複數外露該第一絕緣層21之開口220及溝槽221。例如,該開口220係對應各該導電通孔200之位置。
Furthermore, the second
另外,有關該基板本體2a之種類繁多,如無核心層(coreless)之線路結構、矽中介板(interposer)或其它可供承載如晶片等電子元件之承載單元,並不限於上述。
In addition, there are many types of
如圖2B所示,於各該開口220中之最外側第一絕緣層21上以如雷射方式或其它方式形成複數盲孔210,以令該些開口220連通該些盲孔210,使該導電通孔200之墊面外露於該些開口220與盲孔210。
As shown in FIG. 2B , a plurality of
如圖2C所示,移除該第一絕緣層21於該盲孔210中之部分材質,使該開口220之寬度(孔徑)D1小於該盲孔210之寬度(孔徑)D2。
As shown in FIG. 2C , part of the material of the first insulating
於本實施例中,藉由除膠(Desmear)製程移除該盲孔210之壁面之絕緣材,使該盲孔孔徑變大。例如,該開口220之寬度D1與該盲孔210之寬度D2係相差約3微米(um)。
In this embodiment, the insulating material on the wall of the
如圖2D所示,於該第二絕緣層22上、該開口220之壁面、該溝槽221之壁面上及該盲孔210之壁面上形成一導電層23。接著,於該導電層23上形成金屬材24,以令該金屬材24填入該些盲孔210、開口220與溝槽221中,使該盲孔210中之金屬材24與導電層23作為導電盲孔240。
As shown in FIG. 2D , a
於本實施例中,該導電盲孔240係電性連接該導電通孔200,且該金屬材24係為銅材。例如,以電鍍或其它方式形成該金屬材24。
In this embodiment, the conductive
如圖2E所示,移除該第二絕緣層22上之導電層23及其上之金屬材24,以令各該溝槽221中之金屬材24與導電層23作為導電跡線25,且該些開口220中之金屬材24與導電層23作為電性連接該導電盲孔240與該導電跡線25之接點線路250,使該導電跡線25、導電盲孔240及接點線路250作為佈線層2b。
As shown in FIG. 2E , the
於本實施例中,採用快速蝕刻製程移除該金屬材24,以令該導電跡線25與該接點線路250凹入該溝槽221與該開口220中,使該導電跡線25之表面與該接點線路250之表面均低於該第二絕緣層22之表面。所述之快速蝕刻係指僅蝕刻微量該金屬材24,如蝕刻厚度為4~6微米,即停止蝕刻。
In this embodiment, a rapid etching process is used to remove the
再者,於移除該金屬材24時,該第二絕緣層22係作為阻層,且於後續製程中,該第二絕緣層22係作為防焊層,以於該導電跡線25或接點線路250上結合銲錫材料後可進行回銲作業。
Furthermore, when the
因此,本發明之承載結構2之製法主要藉由最外側之導電盲孔240之無墊式(landless)設計,使該接點線路250之寬度R1小於該導電盲孔240之寬度R2,因而該接點線路250不會佔用該第一絕緣層21之表面,以利於佈設更多導電跡線25於該第一絕緣層21上,故相較於習知技術,本發明之製法能有效增加該承載結構2之佈線層2b之佈線密度,以利於增加電子產品之功能。
Therefore, the manufacturing method of the supporting
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。 The above embodiments are used to illustrate the principles and effects of the present invention, but are not used to limit the present invention. Anyone familiar with this technology can modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the scope of the patent application described below.
2:承載結構 2: Load-bearing structure
2a:基板本體 2a: Substrate body
2b:佈線層 2b: Wiring layer
20:核心層 20: Core layer
20a:第一側 20a: First side
20b:第二側 20b: Second side
200:導電通孔 200: Conductive vias
201,202:線路層 201,202: Circuit layer
21:第一絕緣層 21: First insulating layer
22:第二絕緣層 22: Second insulation layer
210:盲孔 210: Blind hole
220:開口 220: Open mouth
221:溝槽 221: Groove
240:導電盲孔 240: Conductive blind vias
25:導電跡線 25: Conductive traces
250:接點線路 250: Contact line
R1,R2:寬度 R1, R2: Width
Claims (10)
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| TW112113498A TWI851135B (en) | 2023-04-11 | 2023-04-11 | Fabricating method of carrier strucure |
| CN202310421205.6A CN118800662A (en) | 2023-04-11 | 2023-04-19 | Method of making load-bearing structure |
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| TW112113498A TWI851135B (en) | 2023-04-11 | 2023-04-11 | Fabricating method of carrier strucure |
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| JP2005159354A (en) * | 2003-11-25 | 2005-06-16 | Internatl Business Mach Corp <Ibm> | High performance chip carrier substrate |
| US20070166944A1 (en) * | 2006-01-04 | 2007-07-19 | Endicott Interconnect Technologies, Inc. | Method of making circuitized substrate |
| TWI760272B (en) * | 2021-08-09 | 2022-04-01 | 矽品精密工業股份有限公司 | Electronic package and carrier structure |
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|---|---|---|---|---|
| JP2005159354A (en) * | 2003-11-25 | 2005-06-16 | Internatl Business Mach Corp <Ibm> | High performance chip carrier substrate |
| US20070166944A1 (en) * | 2006-01-04 | 2007-07-19 | Endicott Interconnect Technologies, Inc. | Method of making circuitized substrate |
| TWI760272B (en) * | 2021-08-09 | 2022-04-01 | 矽品精密工業股份有限公司 | Electronic package and carrier structure |
Also Published As
| Publication number | Publication date |
|---|---|
| TW202443715A (en) | 2024-11-01 |
| CN118800662A (en) | 2024-10-18 |
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