TWI696263B - Memory structure and manufacturing method therefore - Google Patents

Abstract

A memory structure including a substrate, an isolation structure, and a first memory cell is provided. The isolation structure is disposed in the substrate to define an active area. The isolation structure has a first recess. The first recess is located on one side of the active area. The first memory cell includes a first charge storage layer, a first dielectric layer, a first conductive layer, and a second dielectric layer. The first charge storage layer is disposed in the first recess. The first dielectric layer is located between the first charge storage layer and the substrate of the active area. The first conductive layer is disposed on the isolation structure. The first charge storage layer is located between the first conductive layer and the substrate of the active area. The second dielectric layer is located between the first conductive layer and the first charge storage layer.

Description

Memory structure and its manufacturing method

The invention relates to a semiconductor structure and a manufacturing method thereof, and particularly relates to a memory structure and a manufacturing method thereof.

As technology continues to change, advances in electronic components have increased the need for greater storage capacity. Therefore, in order to meet the demand for high storage density, the industry is actively developing memory devices with higher accumulation density.

The invention provides a memory structure and a manufacturing method thereof, which can effectively improve the accumulation degree of memory elements.

The invention provides a memory structure, including a substrate, an isolation structure and a first memory cell. The isolation structure is arranged in the substrate and defines the active area. The isolation structure has a first recess. The first depression is located on one side of the active area. The first memory cell includes a first charge storage layer, a first dielectric layer, a first conductor layer and a second dielectric layer. The first charge storage layer is disposed in the first recess. The first dielectric layer is located between the first charge storage layer and the substrate of the active region. The first conductor layer is disposed on the isolation structure. The first charge storage layer is located between the first conductor layer and the substrate of the active region. The second dielectric layer is located between the first conductor layer and the first charge storage layer.

According to an embodiment of the invention, in the above memory structure, the first charge storage layer may be a floating gate layer or a charge trapping layer.

According to an embodiment of the invention, in the above memory structure, the first conductor layer and the top surface of the base of the active region may not have overlapping regions.

According to an embodiment of the invention, in the above memory structure, the first conductor layer and the top surface of the base of the active region may have overlapping regions.

According to an embodiment of the invention, in the above memory structure, the isolation structure may have a second recess. The second depression is located on the other side of the active area. The memory structure may further include a second memory cell. The second memory cell may include a second charge storage layer, a third dielectric layer, a second conductor layer, and a second dielectric layer. The second charge storage layer is disposed in the second recess. The third dielectric layer is located between the second charge storage layer and the substrate of the active region. The second conductor layer is disposed on the isolation structure. The second charge storage layer is located between the second conductor layer and the base of the active region. The second dielectric layer is located between the second conductor layer and the second charge storage layer.

According to an embodiment of the invention, in the above memory structure, the first memory cell and the second memory cell may share an active area.

According to an embodiment of the invention, in the above memory structure, the first charge storage layer and the second charge storage layer may be separated from each other.

According to an embodiment of the invention, in the above memory structure, the first conductor layer and the second conductor layer may be connected to each other and extend through the active area.

According to an embodiment of the invention, the memory structure may further include a well area. The well area is located in the base of the active area. The bottom of the well region may be lower than the bottom of the first charge storage layer.

According to an embodiment of the invention, in the above memory structure, the well region may have the same doping concentration on one side and the other side of the active region.

According to an embodiment of the invention, in the above memory structure, the well region may have different doping concentrations on one side and the other side of the active region.

According to an embodiment of the invention, the above memory structure may further include a first doped region and a second doped region. The first doped region and the second doped region are separated from each other and are located in the substrate of the active region.

The invention provides a method for manufacturing a memory structure, including the following steps. An isolation structure is formed in the substrate, and an active area is defined. The isolation structure has a first recess. The first depression is located on one side of the active area. Form the first memory cell. The first memory cell includes a first charge storage layer, a first dielectric layer, a first conductor layer and a second dielectric layer. The first charge storage layer is disposed in the first recess. The first dielectric layer is located between the first charge storage layer and the substrate of the active region. The first conductor layer is disposed on the isolation structure. The first charge storage layer is located between the first conductor layer and the substrate of the active region. The second dielectric layer is located between the first conductor layer and the first charge storage layer.

According to an embodiment of the invention, in the above method of manufacturing a memory structure, the method of forming the first recess may include the following steps. A patterned photoresist layer is formed on the substrate. The patterned photoresist layer exposes a portion of the isolation structure adjacent to the active area. Remove a portion of the isolation structure exposed by the patterned photoresist layer.

According to an embodiment of the present invention, in the method for manufacturing a memory structure, the method for removing a portion of the isolation structure exposed by the patterned photoresist layer is, for example, a wet etching method or a dry etching method.

According to an embodiment of the invention, in the above method for manufacturing a memory structure, it may further include forming a well region in the substrate of the active region. The bottom of the well region may be lower than the bottom of the first charge storage layer.

According to an embodiment of the invention, in the method for manufacturing a memory structure, the well region may have the same doping concentration on one side and the other side of the active region.

According to an embodiment of the invention, in the method for manufacturing a memory structure, the well region may have different doping concentrations on one side and the other side of the active region.

According to an embodiment of the present invention, in the above-mentioned method of manufacturing the memory structure, the method of forming the well region is, for example, a tilt angle ion implantation method or first implanting dopants in the substrate on one side of the active region, Then heat process the substrate.

According to an embodiment of the invention, in the above method of manufacturing a memory structure, the isolation structure may have a second recess. The second depression is located on the other side of the active area. The manufacturing method of the memory structure may further include forming a second memory cell. The second memory cell may include a second charge storage layer, a third dielectric layer, a second conductor layer, and a second dielectric layer. The second charge storage layer is disposed in the second recess. The third dielectric layer is located between the second charge storage layer and the substrate of the active region. The second conductor layer is disposed on the isolation structure. The second charge storage layer is located between the second conductor layer and the base of the active region. The second dielectric layer is located between the second conductor layer and the second charge storage layer.

Based on the above, in the memory structure and the manufacturing method thereof proposed by the present invention, since the first charge storage layer of the first memory cell is disposed in the first recess of the isolation structure, and the first conductor layer is disposed on the isolation structure, Therefore, it is conducive to reducing the size of the memory cell, so that the chip area can be effectively used to further increase the accumulation degree of the memory device.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

FIG. 1 is a top view of a memory structure according to an embodiment of the invention. 2A to 2F are cross-sectional views of the manufacturing process of the memory structure along the I-I' section line in FIG. 1. 3 is a cross-sectional view of the memory structure taken along the line II-II' in FIG. 1. FIG. 1 is a top view of FIG. 2F, and some components in FIGS. 2A to 2F and 3 are omitted in FIG. 1 to clearly explain the positional relationship between the components of FIG. 1.

1 and 2A, an isolation structure 102 is formed in the substrate 100, and an active area AA is defined. The substrate 100 is, for example, a semiconductor substrate, such as a silicon substrate. The isolation structure 102 is, for example, a shallow trench isolation structure. The material of the isolation structure 102 is, for example, silicon oxide.

Hereinafter, the first conductivity type and the second conductivity type described may be one of the P-type conductivity type and the N-type conductivity type and the other. In this embodiment, the first conductivity type is the P-type conductivity type, and the second conductivity type is the N-type conductivity type, but the invention is not limited thereto. In another embodiment, the first conductivity type may be an N-type conductivity type, and the second conductivity type may be a P-type conductivity type.

A well region 104 is formed in the substrate 100 of the active region AA. The well region 104 may have a first conductivity type (eg, P type). The formation method of the well region 104 is, for example, an ion implantation method. The well region 104 may have the same or different doping concentration on one side and the other side of the active region AA. When the well region 104 has different doping concentrations on one side and the other side of the active region AA, the formation method of the well region 104 is, for example, a tilt angle ion implantation method or the substrate 100 on the side of the active region AA first The dopants are implanted in the middle, and then the substrate 100 is thermally processed to form well regions 104 with different doping concentrations.

A patterned photoresist layer 106 is formed on the substrate 100. The patterned photoresist layer 106 exposes a portion of the isolation structure 102 on the side adjacent to the active area AA. In addition, the patterned photoresist layer 106 can expose a part of the isolation structure 102 adjacent to the other side of the active area AA. The patterned photoresist layer 106 is formed by a lithography process, for example.

A portion of the isolation structure 102 exposed by the patterned photoresist layer 106 is removed, so that the isolation structure 102 has recesses 108a, and may have recesses 108b. The recess 108a and the recess 108b are located on one side and the other side of the active area AA, respectively. The method for removing a part of the isolation structure 102 exposed by the patterned photoresist layer 106 is, for example, a wet etching method or a dry etching method. In this embodiment, the removal method of the partial isolation structure 102 is exemplified by a wet etching method, and the shapes of the recesses 108a and 108b formed by the wet etching method may be approximately triangular (FIG. 2A ).

1 and 2B, the patterned photoresist layer 106 is removed. The method for removing the patterned photoresist layer 106 is, for example, dry stripping or wet stripping.

A dielectric material layer 110 is formed on the substrate 100. The material of the dielectric material layer 110 is, for example, silicon oxide. The method of forming the dielectric material layer 110 is, for example, a thermal oxidation method or a chemical vapor deposition method. In this embodiment, the method of forming the dielectric material layer 110 is explained by taking the thermal oxidation method as an example.

A charge storage material layer 112 covering the dielectric material layer 110 and the isolation structure 102 is formed, and the charge storage material layer 112 fills the recesses 108a and 108b. The material of the charge storage material layer 112 is, for example, a floating gate material (eg, doped polysilicon) or a charge trapping material (eg, silicon nitride). In this embodiment, the material of the charge storage material layer 112 is doped polysilicon as an example, but the invention is not limited thereto.

1 and 2C, the charge storage material layer 112 outside the recess 108a and the recess 108b is removed to form the charge storage layer 112a and the charge storage layer 112b. The charge storage layer 112a and the charge storage layer 112b may be floating gate layers or charge trapping layers, respectively. The charge storage layer 112a and the charge storage layer 112b are disposed in the recess 108a and the recess 108b, respectively. The charge storage layer 112a and the charge storage layer 112b may be separated from each other. That is, the charge storage layer 112a and the charge storage layer 112b may not be connected to each other. The bottom of the well region 104 may be lower than the bottom of the charge storage layer 112a and the bottom of the charge storage layer 112b. In this embodiment, the charge storage layer 112a and the charge storage layer 112b are exemplified by floating gate layers doped with polysilicon, but the invention is not limited thereto. The method for removing the charge storage material layer 112 outside the recess 108a and the recess 108b is, for example, using the dielectric material layer 110 as a polishing stop layer, and performing a chemical mechanical polishing process on the charge storage material layer 112.

The dielectric material layer 110 outside the recess 108a and the recess 108b is removed to form the dielectric layer 110a and the dielectric layer 110b. The dielectric layer 110a and the dielectric layer 110b can be used as tunneling dielectric layers, respectively. The dielectric layer 110a is located between the charge storage layer 112a and the substrate 100 in the active area AA. The dielectric layer 110b is located between the charge storage layer 112b and the substrate 100 in the active area AA. The method of removing the dielectric material layer 110 outside the recess 108a and the recess 108b is, for example, a chemical mechanical polishing process or a wet etching method. In some embodiments, the dielectric material layer 110 outside the recess 108a and the recess 108b may not be removed, that is, the dielectric material layer 110 on the top surface of the substrate 100 in the active area AA may remain.

1 and 2D, a dielectric layer 114 is formed on the charge storage layer 112a and the charge storage layer 112b. The dielectric layer 114 may serve as a block layer. In addition, the dielectric layer 114 can be further formed on the substrate 100 and the isolation structure 102. The material of the dielectric layer 114 is, for example, oxide-nitride-oxide (ONO), high-k material or a combination thereof. The method of forming the dielectric layer 114 is, for example, a chemical vapor deposition method.

A conductive material layer 116 is formed on the dielectric layer 114. The material of the conductive material layer 116 is, for example, doped polysilicon. The method of forming the conductive material layer 116 is, for example, a chemical vapor deposition method.

1 and 2E, a patterned photoresist layer 118 is formed on the conductive material layer 116. The patterned photoresist layer 106 is formed by a lithography process, for example.

Using the patterned photoresist layer 118 as a mask, part of the conductive material layer 116 is removed to form a conductive layer 116a and a conductive layer 116b. The conductor layer 116a and the conductor layer 116b can serve as control gates, respectively. The conductor layer 116a and the conductor layer 116b may be separated from each other, that is, the conductor layer 116a and the conductor layer 116b may not be connected to each other, but the invention is not limited thereto. The top surface of the substrate 100 of the conductive layer 116a and the active area AA may or may not have an overlapping area. In addition, the conductive layer 116b and the top surface of the substrate 100 of the active area AA may or may not have overlapping areas. In this embodiment, the top surface of the substrate 100 of the conductive layer 116a and the active area AA does not have an overlapping area, and the top surface of the substrate 100 of the conductive layer 116b and the active area AA does not have an overlapping area, but the present invention does not use this Limited.

In addition, the above method can form the memory cell 122, and can further form the memory cell 124. The memory cell 122 includes a charge storage layer 112a, a dielectric layer 110a, a conductor layer 116a and a dielectric layer 114. The charge storage layer 112a is provided in the recess 108a. The dielectric layer 110a is located between the charge storage layer 112a and the substrate 100 in the active area AA. The conductor layer 116a is provided on the isolation structure 102. The charge storage layer 112a is located between the conductor layer 116a and the substrate 100 in the active area AA. The dielectric layer 114 is located between the conductor layer 116a and the charge storage layer 112a.

The memory cell 124 may include a charge storage layer 112b, a dielectric layer 110b, a conductor layer 116b, and a dielectric layer 114. The charge storage layer 112b is provided in the recess 108b. The dielectric layer 110b is located between the charge storage layer 112b and the substrate 100 in the active area AA. The conductor layer 116b is provided on the isolation structure 102. The charge storage layer 112b is located between the conductor layer 116b and the substrate 100 in the active area AA. The dielectric layer 114 is located between the conductor layer 116b and the charge storage layer 112b.

In addition, the memory cell 122 and the memory cell 124 can share the active area AA, thereby further enhancing the accumulation degree of the memory element. In this embodiment, the memory cell 122 and the memory cell 124 can further share the well 104 and the dielectric layer 114, but the invention is not limited thereto.

In addition, the memory cell 122 and the memory cell 124 can be operated independently by different word lines or operated by the same word line. In the case where the memory cell 122 and the memory cell 124 are operated by the same word line, the conductor layer 116a of the memory cell 122 and the conductor layer 116b of the memory cell 124 are coupled to each other. For example, the conductive layer 116a of the memory cell 122 and the conductive layer 116b of the memory cell 124 may be coupled to each other by an interconnection structure (not shown), but the invention is not limited thereto.

Please refer to FIGS. 1, 2F and 3 to remove the patterned photoresist layer 118. The removal method of the patterned photoresist layer 118 is, for example, a dry photoresist removal method or a wet photoresist removal method.

A spacer 120a and a spacer 120b may be formed on the sidewall of the conductor layer 116a and the sidewall of the conductor layer 116b, respectively. The spacer 120a and the spacer 120b may have a single-layer structure or a multi-layer structure, respectively. The materials of the spacer 120a and the spacer 120b are, for example, silicon oxide, silicon nitride, or a combination thereof.

In addition, a doped region 126 and a doped region 128 separated from each other may be formed in the substrate 100 of the active region AA. The doped region 126 and the doped region 128 can serve as a source and a drain, respectively. The doped region 126 and the doped region 128 may have a second conductivity type (eg, N type). The method for forming the doped region 126 and the doped region 128 is, for example, ion implantation.

Hereinafter, the memory structure 10 of this embodiment will be described with reference to FIGS. 1, 2F, and 3. The memory structure 10 can be applied to various non-volatile memories, such as programmable read only memory (PROM), erasable programmable read only memory (EPROM) ), electrically erasable programmable read only memory (EEPROM) or flash memory (flash memory). In addition, although the method of forming the memory structure 10 is described by taking the above method as an example, the invention is not limited thereto.

Please refer to FIGS. 1, 2F and 3, the memory structure 10 includes a substrate 100, an isolation structure 102 and a memory cell 122, and may further include a memory cell 124, a well region 104, a doped region 126, a doped region 128, a gap At least one of the wall 120a and the spacer 120b. The isolation structure 102 is disposed in the substrate 100 and defines an active area AA. The isolation structure 102 has a recess 108a, and may have a recess 108b. The recess 108a and the recess 108b are located on one side and the other side of the active area AA, respectively. The memory cell 122 includes a charge storage layer 112a, a dielectric layer 110a, a conductor layer 116a and a dielectric layer 114. The memory cell 124 may include a charge storage layer 112b, a dielectric layer 110b, a conductor layer 116b, and a dielectric layer 114. The details of the memory cell 122 and the memory cell 124 have been described in the foregoing, and will not be described here. The well area 104 is located in the substrate 100 of the active area AA. The bottom of the well region 104 may be lower than the bottom of the charge storage layer 112a. The doped region 126 and the doped region 128 are separated from each other and located in the substrate 100 of the active region AA. The spacer 120a and the spacer 120b are respectively provided on the side wall of the conductor layer 116a and the side wall of the conductor layer 116b. In addition, the materials, forming methods, and arrangement relationships of the components in the memory structure 10 have been described in detail in the foregoing embodiments, and will not be described here.

Based on the above embodiment, it can be seen that in the above memory structure 10 and its manufacturing method, since the charge storage layer 112a of the memory cell 122 is disposed in the recess 108a of the isolation structure 102, and the conductor layer 116a is disposed on the isolation structure 102, it is advantageous In order to reduce the size of the memory cell, the chip area can be effectively used, thereby improving the accumulation degree of the memory device.

4 to 7 are cross-sectional views of memory structures in other embodiments of the invention.

Please refer to FIGS. 2F and 4. The difference between the memory structure 20 of FIG. 4 and the memory structure 10 of FIG. 2F is as follows. In the memory structure 20, the conductor layer 216a of the memory cell 222 and the top surface of the substrate 100 in the active area AA have overlapping areas, and the conductor layer 216b of the memory cell 224 and the top surface of the substrate 100 in the active area AA have overlapping areas. The method for forming the conductor layer 216a and the conductor layer 216a is, for example, patterning the conductor material layer 116 in FIG. 2D. In FIG. 4, the thickness of the dielectric layer 214 above the active area AA is greater than the thickness of the dielectric layer 214 above the recess 108 a and the recess 108 b. In this way, when the memory cell 222 and the memory cell 224 are operated, charges can be prevented from being directly injected into the conductor layer 216a and the conductor layer 216b in the overlapping region. The dielectric layer 214 may be a multi-layer structure, but the invention is not limited thereto. For example, the method of forming the dielectric layer 214 may first form only one dielectric layer in the active area AA, and then form another dielectric layer simultaneously on the active area AA, the recess 108a, and the recess 108b, so that the dielectric The thickness of the electrical layer 214 above the active area AA is greater than the thickness of the dielectric layer 214 above the recess 108a and the recess 108b, but the invention is not limited thereto. In other embodiments, in the step of FIG. 2C, the dielectric material layer 110 located in the active area AA may not be removed, whereby the dielectric material layer 110 in the active area AA and the subsequently formed dielectric layer 114 Dielectric layer 214 is formed. In addition, in the memory structure 20 and the memory structure 10, the same or similar members are denoted by the same or similar symbols and their description is omitted.

Based on the above embodiment, it can be seen that in the above memory structure 20 and its manufacturing method, since the charge storage layer 112a of the memory cell 222 is disposed in the recess 108a of the isolation structure 102, and the conductor layer 216a is disposed on the isolation structure 102, it is advantageous In order to reduce the size of the memory cell, the chip area can be effectively used, thereby improving the accumulation degree of the memory device.

Please refer to FIGS. 2F and 5. The difference between the memory structure 30 of FIG. 5 and the memory structure 10 of FIG. 2F is as follows. In the memory structure 30, the conductor layer 316a and the conductor layer 316b may be connected to each other and extend through the active area AA. In addition, the conductor layer 316a and the conductor layer 316b may be a part of the wire 316, respectively. In this case, the conductor layer 316a and the conductor layer 316b are coupled to each other, so the memory cell 322 and the memory cell 324 can be operated by the same word line. The method of forming the wire 316 is, for example, patterning the conductive material layer 116 in FIG. 2D. In addition, the conductive layer 316a of the memory cell 322 and the top surface of the substrate 100 of the active area AA have an overlapping area, and the conductive layer 316b of the memory cell 324 and the top surface of the substrate 100 of the active area AA have an overlapping area. In FIG. 5, the thickness of the dielectric layer 314 above the active area AA is greater than the thickness of the dielectric layer 314 above the recess 108 a and the recess 108 b. In this way, when the memory cell 322 and the memory cell 324 are operated, charges can be prevented from being directly injected into the conductor layer 316a and the conductor layer 316b in the overlapping region. The dielectric layer 314 may be a multi-layer structure, but the invention is not limited thereto. In addition, the method of forming the dielectric layer 314 can refer to the method of forming the dielectric layer 214, and will not be described here. In addition, in the memory structure 30 and the memory structure 10, the same or similar members are denoted by the same or similar symbols and their description is omitted.

Based on the above embodiment, it can be seen that in the above memory structure 30 and its manufacturing method, since the charge storage layer 112a of the memory cell 322 is disposed in the recess 108a of the isolation structure 102, and the conductor layer 316a is disposed on the isolation structure 102, it is advantageous In order to reduce the size of the memory cell, the chip area can be effectively used, thereby improving the accumulation degree of the memory device.

2F and FIG. 6, the difference between the memory structure 40 of FIG. 6 and the memory structure 10 of FIG. 2F is as follows. In the memory structure 40, the shape of the recess 408a and the shape of the recess 408b may be approximately trapezoidal. As a result, the charge storage layer 412a in the memory cell 422 and the charge storage layer 112a in the memory cell 122 will have different shapes, and the charge storage layer 412b in the memory cell 422 and the charge storage layer 112b in the memory cell 122 will With different shapes. The formation method of the recess 408a and the recess 408b is, for example, in the step of FIG. 2A, the exposed by the patterned photoresist layer 106 is removed by dry etching (eg, reactive ion etching (RIE)) Part of the isolation structure 102 so that the isolation structure 102 has trapezoidal recesses 408a and 408b. In addition, in the memory structure 40 and the memory structure 10, the same or similar members are denoted by the same or similar symbols and their description is omitted.

Based on the above embodiment, it can be seen that in the above memory structure 40 and its manufacturing method, since the charge storage layer 412a of the memory cell 422 is disposed in the recess 408a of the isolation structure 102, and the conductor layer 116a is disposed on the isolation structure 102, it is advantageous In order to reduce the size of the memory cell, the chip area can be effectively used, thereby improving the accumulation degree of the memory device.

2F and FIG. 7, the difference between the memory structure 50 of FIG. 7 and the memory structure 10 of FIG. 2F is as follows. In the memory structure 50, the charge storage layer 512a and the charge storage layer 512b may be charge trapping layers, respectively. The material of the charge storage layer 512a and the charge storage layer 512b is, for example, silicon nitride. The charge storage layer 512a and the charge storage layer 512b may be located in the recess 108a and the recess 108b, respectively. In this embodiment, the charge storage layer 512a and the charge storage layer 512b may be conformally formed in the recess 108a and the recess 108b, respectively. In this case, the partial conductive layer 516a and the partial conductive layer 516b may be filled into the recess 108a and the recess 108b, respectively. In this embodiment, the method of forming the dielectric layer 514 is formed on the substrate 100, the charge storage layer 512a, and the charge storage layer 512b by an oxidation process, for example. In addition, in the memory structure 50 and the memory structure 10, the same or similar members are denoted by the same or similar symbols and their description is omitted.

Based on the above embodiment, it can be seen that in the above memory structure 50 and the manufacturing method thereof, since the charge storage layer 512a of the memory cell 522 is disposed in the recess 108a of the isolation structure 102, and the conductor layer 516a is disposed on the isolation structure 102, it is advantageous In order to reduce the size of the memory cell, the chip area can be effectively used, thereby improving the accumulation degree of the memory device.

In some embodiments, the charge storage layer 512a and the charge storage layer 512b in the memory structure 50 of FIG. 7 may be applied to the memory structure 20 of FIG. 4, the memory structure 30 of FIG. 5, and the memory structure of FIG. 6. 40. That is, the charge storage layer 112a and the charge storage layer 112b in FIGS. 4 and 5 and the charge storage layer 412a and the charge storage layer 412b in FIG. 6 can be replaced with the charge storage layer 512a and the charge storage layer in FIG. 7, respectively 512b.

In summary, in the memory structure and manufacturing method of the above embodiment, the arrangement of the conductor layer and the charge storage layer in the memory cell can reduce the size of the memory cell, thereby improving the accumulation degree of the memory device .

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

10, 20, 30, 40, 50: memory structure 100: base 102: Isolation structure 104: Well District 106, 118: patterned photoresist layer 108a, 108b, 408a, 408b: depression 110: dielectric material layer 110a, 110b: dielectric layer 112: charge storage material layer 112a, 112b, 412a, 412b, 512a, 512b: charge storage layer 114, 214, 314, 514: dielectric layer 116: Conductor material layer 116a, 116b, 216a, 216b, 316a, 316b, 516a, 516b: conductor layer 120a, 120b: gap wall 122, 124, 222, 224, 322, 324, 422, 424, 522, 524: memory cells 126, 128: doped area AA: Active area

FIG. 1 is a top view of a memory structure according to an embodiment of the invention. 2A to 2F are cross-sectional views of the manufacturing process of the memory structure along the I-I' section line in FIG. 1. 3 is a cross-sectional view of the memory structure taken along the line II-II' in FIG. 1. 4 to 7 are cross-sectional views of memory structures in other embodiments of the invention.

10: Memory structure

100: base

102: Isolation structure

104: Well District

108a, 108b: depression

110a, 110b: dielectric layer

112a, 112b: charge storage layer

114: Dielectric layer

116a, 116b: conductor layer

120a, 120b: gap wall

122, 124: memory cell

Claims (20)

A memory structure includes: a substrate; an isolation structure, which is disposed in the substrate and defines an active area, wherein the isolation structure has a first depression, and the first depression is located on one side of the active area ; And a first memory cell, including: a first charge storage layer, disposed in the first recess; a first dielectric layer, located between the first charge storage layer and the active region of the substrate ; A first conductor layer, disposed on the isolation structure, wherein the first charge storage layer is located between the first conductor layer and the substrate of the active region; and a second dielectric layer, bit Between the first conductor layer and the first charge storage layer. The memory structure as recited in item 1 of the patent application range, wherein the first charge storage layer includes a floating gate layer or a charge trapping layer. The memory structure as recited in item 1 of the patent application range, wherein the first conductor layer does not have an overlapping area with the top surface of the base of the active area. The memory structure as described in item 1 of the patent application range, wherein the first conductor layer has an overlapping area with the top surface of the base of the active area. The memory structure according to item 1 of the patent application scope, wherein the isolation structure has a second depression, the second depression is located on the other side of the active area, and the memory structure further includes a second memory And the second memory cell includes: a second charge storage layer disposed in the second recess; a third dielectric layer located on the substrate of the second charge storage layer and the active region Between; a second conductor layer, disposed on the isolation structure, wherein the second charge storage layer is located between the second conductor layer and the active region of the substrate; and the second medium The electric layer is located between the second conductor layer and the second charge storage layer. The memory structure as described in item 5 of the patent application scope, wherein the first memory cell and the second memory cell share the active area. The memory structure as recited in item 5 of the patent application range, wherein the first charge storage layer and the second charge storage layer are separated from each other. The memory structure as recited in item 5 of the patent application range, wherein the first conductor layer and the second conductor layer are connected to each other and extend through the active region. The memory structure as described in item 1 of the patent application scope further includes: a well region located in the substrate of the active region, wherein the bottom of the well region is lower than the bottom of the first charge storage layer . The memory structure as recited in item 9 of the patent application range, wherein the well region has the same doping concentration on one side and the other side of the active region. The memory structure as described in item 9 of the patent application range, wherein the well region has different doping concentrations on one side and the other side of the active region. The memory structure as described in item 1 of the patent application scope further includes: a first doped region and a second doped region, separated from each other and located in the substrate of the active region. A method for manufacturing a memory structure includes: forming an isolation structure in a substrate, and defining an active area, wherein the isolation structure has a first depression, and the first depression is located on one side of the active area; and A first memory cell is formed, wherein the first memory cell includes: a first charge storage layer disposed in the first recess; a first dielectric layer located between the first charge storage layer and the active region Between the substrates; a first conductor layer disposed on the isolation structure, wherein the first charge storage layer is located between the first conductor layer and the substrate of the active region; and the first Two dielectric layers are located between the first conductor layer and the first charge storage layer. The method for manufacturing a memory structure as described in item 13 of the patent application range, wherein the method for forming the first recess includes: forming a patterned photoresist layer on the substrate, wherein the patterned photoresist layer is exposed A portion of the isolation structure adjacent to a side of the active region; and removing a portion of the isolation structure exposed by the patterned photoresist layer. The method for manufacturing a memory structure as recited in item 14 of the patent application range, wherein a method for removing a portion of the isolation structure exposed by the patterned photoresist layer includes a wet etching method or a dry etching method. The method for manufacturing a memory structure as described in item 13 of the patent application scope further includes: forming a well region in the substrate of the active region, wherein the bottom of the well region is lower than the first charge storage layer bottom of. The method for manufacturing a memory structure as described in item 16 of the patent application range, wherein the well region has the same doping concentration on one side and the other side of the active region. The method for manufacturing a memory structure as recited in item 16 of the patent application range, wherein the well region has different doping concentrations on one side and the other side of the active region. The method for manufacturing a memory structure as described in item 18 of the patent application range, wherein the method for forming the well area includes an oblique angle ion implantation method or is first implanted in the substrate on one side of the active area Doping, and then performing a thermal process on the substrate. The method for manufacturing a memory structure as described in item 13 of the patent application range, wherein the isolation structure has a second recess, the second recess is located on the other side of the active area, and the manufacturing of the memory structure The method further includes forming a second memory cell, and the second memory cell includes: a second charge storage layer disposed in the second recess; A third dielectric layer is located between the second charge storage layer and the substrate of the active region; a second conductor layer is disposed on the isolation structure, wherein the second charge storage layer is located at Between the second conductor layer and the substrate of the active region; and the second dielectric layer is located between the second conductor layer and the second charge storage layer.

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