TWI491331B - Printed circuit board - Google Patents
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- TWI491331B TWI491331B TW099126147A TW99126147A TWI491331B TW I491331 B TWI491331 B TW I491331B TW 099126147 A TW099126147 A TW 099126147A TW 99126147 A TW99126147 A TW 99126147A TW I491331 B TWI491331 B TW I491331B
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- 238000010168 coupling process Methods 0.000 claims description 20
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- 239000003990 capacitor Substances 0.000 claims description 3
- 238000005476 soldering Methods 0.000 claims 3
- 230000005540 biological transmission Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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Description
本發明係關於一種印刷電路板。This invention relates to a printed circuit board.
在習知的印刷電路板設計中，對於應用的彈性化要求愈見頻繁，高速差分訊號的共存佈線應用也更加廣泛。共存佈線即為以單一佈線實現兩種線路連接方式來針對不同市場規格需求，擴充產品功能之彈性。對於三路以上差分對的共存佈線設計往往會面臨走線交叉的困擾或因連接的傳輸線無傳輸作用而造成繞線殘段。In the conventional printed circuit board design, the application flexibility is more frequent, and the coexistence wiring application of the high-speed differential signal is more extensive. Coexisting wiring is to achieve two types of line connection in a single wiring to meet the needs of different market specifications, and to expand the flexibility of product functions. For a coexisting wiring design with more than three differential pairs, the wiring crossover is often faced with the problem of crossover or the transmission of the connected transmission line.
鑒於以上內容，有必要提供一種利用單一佈線來實現三路以上線路連接方式的印刷電路板。In view of the above, it is necessary to provide a printed circuit board that utilizes a single wiring to achieve a three-way or more line connection.
一種印刷電路板，包括：A printed circuit board comprising:
一第一訊號層，該第一訊號層設有一耦接一第一電子元器件的第一對焊盤及一耦接一第二電子元器件的第二對焊盤；a first signal layer, the first signal layer is provided with a first pair of pads coupled to a first electronic component and a second pair of pads coupled to a second electronic component;
一第二訊號層，該第二訊號層設有第三對至第八對焊盤，該第四對焊盤設置在該第三對焊盤與該第五對焊盤之間，且該第三對焊盤與該第二對焊盤對應耦接，該第七對焊盤設置在該第六對焊盤與該第八對焊盤之間，且該第七對焊盤與該第五對焊盤耦接，該六對焊盤與該第一對焊盤對應耦接，該第八對焊盤耦接一第三電子元器件；及a second signal layer, the second signal layer is provided with a third pair to the eighth pair of pads, and the fourth pair of pads is disposed between the third pair of pads and the fifth pair of pads, and the Three pairs of pads are correspondingly coupled to the second pair of pads, the seventh pair of pads are disposed between the sixth pair of pads and the eighth pair of pads, and the seventh pair of pads and the fifth For the pad coupling, the six pairs of pads are coupled to the first pair of pads, and the eighth pair of pads are coupled to a third electronic component;
一控制晶片，該控制晶片耦接該第四對焊盤以傳輸一訊號對；a control chip coupled to the fourth pair of pads to transmit a signal pair;
當將該第三對焊盤及第四對焊盤耦接時，該訊號對傳輸至該第二電子元器件；當將該第四及第五對焊盤耦接，且將該第六及第七對焊盤耦接時，該訊號對傳輸至該第一電子元器件；當將該第四及第五對焊盤耦接，且將該第七及第八對焊盤耦接時，該訊號傳輸至該第三電子元器件。When the third pair of pads and the fourth pair of pads are coupled, the signal pair is transmitted to the second electronic component; when the fourth and fifth pairs of pads are coupled, and the sixth When the seventh pair of pads are coupled, the signal pair is transmitted to the first electronic component; when the fourth and fifth pairs of pads are coupled, and the seventh and eighth pairs of pads are coupled, The signal is transmitted to the third electronic component.
與習知技術相比，本發明透過將該第三對焊盤及第四對焊盤耦接時，該訊號對傳輸至該第二電子元器件，或將該第四及第五對焊盤耦接，且將該第六及第七對焊盤耦接時，該訊號對傳輸至該第一電子元器件，或將該第四及第五對焊盤耦接，且將該第七及第八對焊盤耦接時，該訊號對傳輸至該第三電子元器件，從而選擇性地將第一至第三電子元器件中的一個耦接該控制晶片，從而避免了該印刷電路板上走線交叉的問題及傳輸線繞線殘段的現象。Compared with the prior art, when the third pair of pads and the fourth pair of pads are coupled, the signal pair is transmitted to the second electronic component, or the fourth and fifth pairs of pads are When the sixth and seventh pairs of pads are coupled, the signal pair is transmitted to the first electronic component, or the fourth and fifth pairs of pads are coupled, and the seventh and When the eighth pair of pads are coupled, the signal pair is transmitted to the third electronic component, thereby selectively coupling one of the first to third electronic components to the control chip, thereby avoiding the printed circuit board The problem of crossing the upper line and the phenomenon of the winding line of the transmission line.
請參考圖1，本發明印刷電路板100較佳實施方式包括一第一訊號層10、一第二訊號層20、一設於該第一訊號層10與該第二訊號層20之間的絕緣層(圖未示)、一第一對埋孔40A、40B、一第二對埋孔41A、41B及一控制晶片4。在本實施方式中，該印刷電路板100為一主機板。Referring to FIG. 1 , a preferred embodiment of the printed circuit board 100 of the present invention includes a first signal layer 10 , a second signal layer 20 , and an insulation disposed between the first signal layer 10 and the second signal layer 20 . A layer (not shown), a first pair of buried vias 40A, 40B, a second pair of buried vias 41A, 41B and a control wafer 4. In the present embodiment, the printed circuit board 100 is a motherboard.
該第一訊號層10設有一第一對焊盤11A、11B及一第二對焊盤12A、12B。該第一對焊盤11A、11B耦接一第一電子元器件1。該第二對焊盤12A、12B耦接一第二電子元器件2。The first signal layer 10 is provided with a first pair of pads 11A, 11B and a second pair of pads 12A, 12B. The first pair of pads 11A, 11B are coupled to a first electronic component 1. The second pair of pads 12A, 12B are coupled to a second electronic component 2.
該第二訊號層20設有一第三對焊盤23A、23B、一第四對焊盤24A、24B、一第五對焊盤25A、25B、一第六對焊盤26A、26B、一第七對焊盤27A、27B及一第八對焊盤28A、28B。該第四對焊盤24A、24B設置在該第三對焊盤23A、23B與該第五對焊盤25A、25B之間，且該第三對焊盤23A、23B與該第二對焊盤12A、12B相互對應且透過該第二埋孔41A、41B耦接。該第七對焊盤27A、27B設置在該第六對焊盤26A、26B與該第八對焊盤28A、28B之間，且該第七對焊盤27A、27B與該第五對焊盤25A、25B耦接，該六對焊盤26A、26B與該第一對焊盤11A、11B相互對應且透過該第一埋孔40A、40B耦接。該第七對焊盤27A、27B與該第五對焊盤25A、25B的耦接是透過在焊盤27A與25A間佈設訊號線、在27B與25B間佈設訊號線實現的。該第四對焊盤24A、24B耦接該控制晶片4以接收該控制晶片4產生的一高速訊號對如一高速差分訊號對。該第八對焊盤28A、28B耦接一第三電子元器件3。The second signal layer 20 is provided with a third pair of pads 23A, 23B, a fourth pair of pads 24A, 24B, a fifth pair of pads 25A, 25B, a sixth pair of pads 26A, 26B, and a seventh Pair of pads 27A, 27B and an eighth pair of pads 28A, 28B. The fourth pair of pads 24A, 24B are disposed between the third pair of pads 23A, 23B and the fifth pair of pads 25A, 25B, and the third pair of pads 23A, 23B and the second pair of pads 12A and 12B correspond to each other and are coupled through the second buried holes 41A and 41B. The seventh pair of pads 27A, 27B are disposed between the sixth pair of pads 26A, 26B and the eighth pair of pads 28A, 28B, and the seventh pair of pads 27A, 27B and the fifth pair of pads 25A, 25B are coupled, and the six pairs of pads 26A, 26B and the first pair of pads 11A, 11B correspond to each other and are coupled through the first buried vias 40A, 40B. The coupling of the seventh pair of pads 27A, 27B and the fifth pair of pads 25A, 25B is achieved by arranging a signal line between the pads 27A and 25A and routing the signal line between 27B and 25B. The fourth pair of pads 24A, 24B are coupled to the control chip 4 to receive a high speed signal pair generated by the control chip 4, such as a high speed differential signal pair. The eighth pair of pads 28A, 28B are coupled to a third electronic component 3.
當需要使該第二電子元器件2接收該控制晶片4輸出的高速訊號對時，將一第一被動元件21焊接在焊盤23A及焊盤24A上以實現該兩焊盤23A及24A的耦接，將一第二被動元件22焊接在焊盤23B及焊盤24B上以實現該兩焊盤23B及24B的耦接。該控制晶片4輸出的高速訊號對分別透過該第四對焊盤24A、24B、該第一及第二被動元件21、22、該第三對焊盤23A、23B、該第二埋孔41A、41B及該第二對焊盤12A、12B傳輸至該第二電子元器件2。When the second electronic component 2 needs to receive the high-speed signal pair outputted by the control chip 4, a first passive component 21 is soldered on the pad 23A and the pad 24A to realize coupling of the two pads 23A and 24A. Then, a second passive component 22 is soldered on the pad 23B and the pad 24B to achieve coupling of the two pads 23B and 24B. The high-speed signal pair outputted by the control chip 4 passes through the fourth pair of pads 24A, 24B, the first and second passive components 21, 22, the third pair of pads 23A, 23B, the second buried via 41A, 41B and the second pair of pads 12A, 12B are transferred to the second electronic component 2.
請參照圖2所示，當需要使該第一電子元器件1接收該控制晶片4輸出的高速訊號對時，將該第一被動元件21焊接在焊盤24A及焊盤25A上以實現該兩焊盤24A及25A的耦接，將該第二被動元件22焊接在焊盤24B及焊盤25B上以實現該兩焊盤24B及25B的耦接；並將一第三被動元件31焊接在焊盤26A及焊盤27A上以實現該兩焊盤26A及27A的耦接，將一第四被動元件32焊接在焊盤26B及焊盤27B上以實現該兩焊盤26B及27B的耦接。該控制晶片4輸出的高速訊號對分別透過該第四對焊盤24A、24B、該第一及第二被動元件21、22、該第五對焊盤25A、25B、該第七對焊盤27A、27B、該第三及第四被動元件31、32、該第六對焊盤26A、26B、該第一埋孔40A、40B及該第一對焊盤11A、11B傳輸至該第一電子元器件1。Referring to FIG. 2, when the first electronic component 1 needs to receive the high-speed signal pair outputted by the control chip 4, the first passive component 21 is soldered on the pad 24A and the pad 25A to implement the two. The coupling of the pads 24A and 25A, the second passive component 22 is soldered on the pad 24B and the pad 25B to achieve the coupling of the two pads 24B and 25B; and a third passive component 31 is soldered to the solder. The second passive component 32 is soldered on the pad 26B and the pad 27B to realize the coupling of the two pads 26B and 27B on the pad 26A and the pad 27A to realize the coupling of the two pads 26A and 27A. The high-speed signal pair outputted by the control chip 4 passes through the fourth pair of pads 24A, 24B, the first and second passive components 21, 22, the fifth pair of pads 25A, 25B, and the seventh pair of pads 27A, respectively. 27B, the third and fourth passive components 31, 32, the sixth pair of pads 26A, 26B, the first buried vias 40A, 40B and the first pair of pads 11A, 11B are transmitted to the first electronic component Device 1.
請參照圖3所示，當需要使該第三電子元器件3接收該控制晶片4輸出的高速訊號對時，將該第一被動元件21焊接在焊盤24A及焊盤25A上以實現該兩焊盤24A及25A的耦接，將該第二被動元件22焊接在焊盤24B及焊盤25B上以實現該兩焊盤24B及25B的耦接；並將該第三被動元件31焊接在焊盤27A及焊盤28A上以實現該兩焊盤27A及28A的耦接，將該第四被動元件32焊接在焊盤27B及焊盤28B上以實現該兩焊盤27B及28B的耦接。該控制晶片4輸出的高速訊號對分別透過該第四對焊盤24A、24B、該第一及第二被動元件21、22、該第五對焊盤25A、25B、該第七對焊盤27A、27B、該第三及第四被動元件31、32及該第八對焊盤28A、28B傳輸至該第三電子元器件3。該第一被動元件21與該第二被動元件22及該第三被動元件31與該第四被動元件32相互對應設置，且可為電容器或電阻器，在此第一被動元件21與第二被動元件22及該第三被動元件31與該第四被動元件32皆為一交流耦合電容器。Referring to FIG. 3, when the third electronic component 3 needs to receive the high-speed signal pair outputted by the control chip 4, the first passive component 21 is soldered on the pad 24A and the pad 25A to implement the two. The coupling of the pads 24A and 25A, the second passive component 22 is soldered on the pad 24B and the pad 25B to achieve coupling of the two pads 24B and 25B; and the third passive component 31 is soldered to the solder The pad 27A and the pad 28A are coupled to each other to implement the coupling of the two pads 27A and 28A, and the fourth passive component 32 is soldered to the pad 27B and the pad 28B to achieve coupling of the pads 27B and 28B. The high-speed signal pair outputted by the control chip 4 passes through the fourth pair of pads 24A, 24B, the first and second passive components 21, 22, the fifth pair of pads 25A, 25B, and the seventh pair of pads 27A, respectively. 27B, the third and fourth passive components 31, 32 and the eighth pair of pads 28A, 28B are transmitted to the third electronic component 3. The first passive component 21 and the second passive component 22 and the third passive component 31 and the fourth passive component 32 are disposed corresponding to each other, and may be a capacitor or a resistor, where the first passive component 21 and the second passive component The component 22 and the third passive component 31 and the fourth passive component 32 are both AC coupling capacitors.
在其實施方式中，該印刷電路板還可以根據實際需要增加耦接的電子元器件的數量，並按照上述相同的佈線方式來增設複數焊盤及複數過孔來滿足與增加的複數電子元器件的連接。In an embodiment thereof, the printed circuit board can further increase the number of coupled electronic components according to actual needs, and add a plurality of pads and a plurality of via holes according to the same wiring manner as described above to satisfy and increase the plurality of electronic components. Connection.
本發明印刷電路板100透過單一的佈線方式，依據不同需求改變第一被動元件21、第二被動元件22、第三及第四被動元件31、32耦接的位置，選擇性地將所需電子元器件連接至該控制晶片4上，從而避免了該印刷電路板100上走線交叉的問題及傳輸線繞線殘段的現象。The printed circuit board 100 of the present invention selectively changes the positions of the first passive component 21, the second passive component 22, the third and fourth passive components 31, 32 according to different requirements through a single wiring manner, and selectively selects the required electrons. The components are connected to the control wafer 4, thereby avoiding the problem of crossover of the printed circuit board 100 and the phenomenon of the transmission line winding stub.
綜上所述，本發明符合發明專利要件，爰依法提出專利申請。惟，以上所述者僅為本發明之較佳實施例，舉凡熟悉本案技藝之人士，在爰依本發明精神所作之等效修飾或變化，皆應涵蓋於以下之申請專利範圍內。In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims.
1．．．第一電子元器件1. . . First electronic component
10．．．第一訊號層10. . . First signal layer
11A、11B．．．第一對焊盤11A, 11B. . . First pair of pads
12A、12B．．．第二對焊盤12A, 12B. . . Second pair of pads
2．．．第二電子元器件2. . . Second electronic component
20．．．第二訊號層20. . . Second signal layer
21．．．第一被動元件twenty one. . . First passive component
22．．．第二被動元件twenty two. . . Second passive component
23A、23B．．．第三對焊盤23A, 23B. . . Third pair of pads
24A、24B．．．第四對焊盤24A, 24B. . . Fourth pair of pads
25A、25B．．．第五對焊盤25A, 25B. . . Fifth pair of pads
26A、26B．．．第六對焊盤26A, 26B. . . Sixth pair of pads
27A、27B．．．第七對焊盤27A, 27B. . . Seventh pair of pads
28A、28B．．．第八對焊盤28A, 28B. . . Eighth pair of pads
3．．．第三電子元器件3. . . Third electronic component
31．．．第三被動元件31. . . Third passive component
32．．．第四被動元件32. . . Fourth passive component
4．．．控制晶片4. . . Control chip
40A、40B．．．第一埋孔40A, 40B. . . First buried hole
41A、41B．．．第二埋孔41A, 41B. . . Second buried hole
100．．．印刷電路板100. . . A printed circuit board
圖1係本發明印刷電路板較佳實施方式實現的第一種線路連接方式的示意圖。BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic illustration of a first type of line connection implemented by a preferred embodiment of the printed circuit board of the present invention.
圖2係本發明印刷電路板較佳實施方式實現的第二種線路連接方式的示意圖。2 is a schematic diagram of a second type of line connection implemented by a preferred embodiment of the printed circuit board of the present invention.
圖3係本發明印刷電路板較佳實施方式實現的第三種線路連接方式的示意圖。3 is a schematic diagram of a third type of line connection implemented by a preferred embodiment of the printed circuit board of the present invention.
1．．．第一電子元器件1. . . First electronic component
10．．．第一訊號層10. . . First signal layer
11A、11B．．．第一對焊盤11A, 11B. . . First pair of pads
12A、12B．．．第二對焊盤12A, 12B. . . Second pair of pads
2．．．第二電子元器件2. . . Second electronic component
20．．．第二訊號層20. . . Second signal layer
21．．．第一被動元件twenty one. . . First passive component
22．．．第二被動元件twenty two. . . Second passive component
23A、23B．．．第三對焊盤23A, 23B. . . Third pair of pads
24A、24B．．．第四對焊盤24A, 24B. . . Fourth pair of pads
25A、25B．．．第五對焊盤25A, 25B. . . Fifth pair of pads
26A、26B．．．第六對焊盤26A, 26B. . . Sixth pair of pads
27A、27B．．．第七對焊盤27A, 27B. . . Seventh pair of pads
28A、28B．．．第八對焊盤28A, 28B. . . Eighth pair of pads
3．．．第三電子元器件3. . . Third electronic component
4．．．控制晶片4. . . Control chip
40A、40B．．．第一對埋孔40A, 40B. . . First pair of buried holes
41A、41B．．．第二對埋孔41A, 41B. . . Second pair of buried holes
100．．．印刷電路板100. . . A printed circuit board
Claims (6)
一第一訊號層，該第一訊號層設有一耦接一第一電子元器件的第一對焊盤及一耦接一第二電子元器件的第二對焊盤；
一第二訊號層，該第二訊號層設有第三對至第八對焊盤，該第四對焊盤設置在該第三對焊盤與該第五對焊盤之間，且該第三對焊盤與該第二對焊盤對應耦接，該第七對焊盤設置在該第六對焊盤與該第八對焊盤之間，且該第七對焊盤與該第五對焊盤耦接，該六對焊盤與該第一對焊盤對應耦接，該第八對焊盤耦接一第三電子元器件；及
一控制晶片，該控制晶片耦接該第四對焊盤以傳輸一訊號對；
當將該第三對焊盤及第四對焊盤耦接時，該訊號對傳輸至該第二電子元器件；當將該第四及第五對焊盤耦接，且將該第六及第七對焊盤耦接時，該訊號對傳輸至該第一電子元器件；當將該第四及第五對焊盤耦接，且將該第七及第八對焊盤耦接時，該訊號傳輸至該第三電子元器件。A printed circuit board comprising:
a first signal layer, the first signal layer is provided with a first pair of pads coupled to a first electronic component and a second pair of pads coupled to a second electronic component;
a second signal layer, the second signal layer is provided with a third pair to the eighth pair of pads, and the fourth pair of pads is disposed between the third pair of pads and the fifth pair of pads, and the Three pairs of pads are correspondingly coupled to the second pair of pads, the seventh pair of pads are disposed between the sixth pair of pads and the eighth pair of pads, and the seventh pair of pads and the fifth For the pad coupling, the six pairs of pads are coupled to the first pair of pads, the eighth pair of pads are coupled to a third electronic component; and a control chip is coupled to the fourth Transmitting a signal pair to the pad;
When the third pair of pads and the fourth pair of pads are coupled, the signal pair is transmitted to the second electronic component; when the fourth and fifth pairs of pads are coupled, and the sixth When the seventh pair of pads are coupled, the signal pair is transmitted to the first electronic component; when the fourth and fifth pairs of pads are coupled, and the seventh and eighth pairs of pads are coupled, The signal is transmitted to the third electronic component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW099126147A TWI491331B (en) | 2010-08-05 | 2010-08-05 | Printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW099126147A TWI491331B (en) | 2010-08-05 | 2010-08-05 | Printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201208512A TW201208512A (en) | 2012-02-16 |
| TWI491331B true TWI491331B (en) | 2015-07-01 |
Family
ID=46762523
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW099126147A TWI491331B (en) | 2010-08-05 | 2010-08-05 | Printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI491331B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007165483A (en) * | 2005-12-12 | 2007-06-28 | Canon Inc | Multilayer printed circuit board |
| TW201008407A (en) * | 2008-08-08 | 2010-02-16 | Hon Hai Prec Ind Co Ltd | Printed circuit board and coexisting layout method thereof |
| US20100051339A1 (en) * | 2008-09-02 | 2010-03-04 | Hon Hai Precision Industry Co., Ltd. | Circuit board |
-
2010
- 2010-08-05 TW TW099126147A patent/TWI491331B/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007165483A (en) * | 2005-12-12 | 2007-06-28 | Canon Inc | Multilayer printed circuit board |
| TW201008407A (en) * | 2008-08-08 | 2010-02-16 | Hon Hai Prec Ind Co Ltd | Printed circuit board and coexisting layout method thereof |
| US20100051339A1 (en) * | 2008-09-02 | 2010-03-04 | Hon Hai Precision Industry Co., Ltd. | Circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201208512A (en) | 2012-02-16 |
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| MM4A | Annulment or lapse of patent due to non-payment of fees |