TWI484594B - Integrated circuit having microelectromechanical system device and method of fabricating the same - Google Patents

Description

Integrated circuit with MEMS components and manufacturing method thereof

The present invention relates to an integrated circuit and a method of fabricating the same, and more particularly to an integrated circuit for integrating a MEMS device and a semiconductor device and a method of fabricating the same.

Microelectromechanical system device (MEMS device) is a micro-electro-mechanical component fabricated by micro-machining technology. Due to its light weight and small size, MEMS devices are very light, thin, short and small. The demand for electronic products has therefore been widely studied. The currently developed MEMS components include extremely small electromechanical components such as accelerometers, switches, capacitors, inductors, and microphones.

In addition to its light weight, small size, and good signal quality, MEMS microphones manufactured by MEMS technology have become the mainstream of micro-microphones.

The mobile phone is a widely used electronic product of the micro-microphone, and the demand for the microphone's sound quality, volume miniaturization, and circuit integration is also increasing, so that the demand for the MEMS microphone is rapidly increasing.

The present invention provides an integrated circuit in which a MEMS element and a semiconductor element are formed on the same substrate.

The invention provides an integrated circuit process, integrates a MEMS component process and a semiconductor component process, and has a simple process.

The present invention provides an integrated circuit comprising a substrate, a MOS device, a metal interconnect, and a MEMS device. The substrate includes a logic circuit region and a MEMS region. The MOS device is located on the logic circuit region of the substrate. A metal interconnect, above the substrate, is connected to the MOS device and is composed of a plurality of layers of wires and a plurality of vias. The MEMS component, located in the MEMS region, includes a diaphragm of a sandwich structure as an electrode, located between any adjacent upper and lower wires of the metal interconnect and connected to the metal interconnect.

According to an embodiment of the invention, the diaphragm of the sandwich structure comprises a first insulating layer, a second insulating layer and a conductive layer between the first insulating layer and the second insulating layer.

According to the embodiment of the invention, the material of the first insulating layer and the second insulating layer is different from the material of a dielectric layer in the metal interconnect.

According to an embodiment of the invention, the material of the first insulating layer and the second insulating layer comprises tantalum nitride or hafnium oxynitride.

According to an embodiment of the invention, the integrated circuit further includes a protective wall surrounding the MEMS area.

According to an embodiment of the invention, the integrated circuit further includes another electrode located in the substrate of the MEMS region.

The present invention further provides a method of fabricating an integrated circuit comprising providing a substrate comprising a logic circuit region and a MEMS region. Next, a MOS device is formed on the logic circuit region of the substrate. Then, a metal interconnection is formed over the substrate to connect the above-described MOS device. The metal interconnect is composed of a plurality of layers of wires and a plurality of vias. And forming a diaphragm of the sandwich structure of the MEMS element above the MEMS area. A diaphragm of a sandwich structure, which is an electrode, is located above the metal interconnect and between the next two adjacent conductors and is connected to the metal interconnect.

According to an embodiment of the present invention, the above manufacturing method includes forming a doping region in the substrate of the MEMS to serve as another electrode.

According to an embodiment of the invention, the above manufacturing method includes forming a dielectric layer on a logic circuit region and a MEMS region of the substrate. Then, the metal interconnect is formed in the dielectric layer, and the diaphragm of the sandwich structure of the MEMS element is formed in the dielectric layer between the two adjacent wires and above the metal interconnect.

According to an embodiment of the invention, the method for fabricating the integrated circuit further includes forming a protective wall in the dielectric layer around the MEMS region of the substrate, and then removing a portion of the substrate from the back surface of the substrate to form An air cavity, after which a portion of the substrate of the doped region is removed to form a plurality of openings to expose the dielectric layer, and then removing the dielectric layer in the protective wall in the MEMS region.

According to an embodiment of the invention, the method for forming the diaphragm of the sandwich structure includes forming a first insulating layer and a second insulating layer in the dielectric layer and forming a conductive between the first insulating layer and the second insulating layer. Floor.

According to an embodiment of the invention, the material of the first insulating layer and the second insulating layer is different from the material of the dielectric layer in the metal interconnect.

According to an embodiment of the invention, the material of the first insulating layer and the second insulating layer comprises tantalum nitride or hafnium oxynitride.

The invention also provides a method for manufacturing an integrated circuit, comprising performing a front-end process and a back-end process. The front stage process includes forming a semiconductor component on a substrate. The back-end process is performed after the above-mentioned front-end process, and comprises forming a metal interconnect on the substrate and forming a diaphragm of the sandwich structure of the MEMS element as an electrode. A metal interconnect connects the diaphragm of the semiconductor component to the sandwich structure.

According to an embodiment of the invention, the diaphragm of the sandwich structure is formed during the formation of the metal interconnect.

According to an embodiment of the invention, the method for fabricating the integrated circuit further includes forming another electrode in the substrate in the preceding process.

According to an embodiment of the invention, the method for manufacturing the integrated circuit further includes forming a protective wall in a peripheral portion of the diaphragm of the sandwich structure while forming the metal interconnect.

According to an embodiment of the invention, the step of forming the diaphragm of the sandwich structure is performed before the substrate is cut into crystals.

According to an embodiment of the invention, the step of forming the diaphragm of the sandwich structure is performed prior to packaging.

The present invention integrates MEMS components with semiconductor processes, such as complementary MOS processes. More specifically, the diaphragm of the sandwich structure of the MEMS element is embedded in the dielectric layer, and is integrated with the post-metal interconnecting process in the semiconductor process, and the process is simple.

The above described features and advantages of the present invention will be more apparent from the following description.

1A-1E are schematic cross-sectional views showing a method of fabricating an integrated circuit of a MEMS device and a semiconductor device according to an embodiment of the invention.

Referring to FIG. 1A, a substrate 10 is provided that includes regions 12 and 14. In an embodiment, region 12 is logic circuit region 12; region 14 is MEMS region 14. The logic circuit region 12 and the MEMS region 14 will be described below. The material of the substrate 10 is, for example, a semiconductor such as germanium or germanium. First, proceed to the front end process. The front stage process includes forming a MOS device 16 on the logic circuit region 12 of the substrate 10 and forming a doped region 200 and a guard ring 17 in the MEMS region 14. The MOS device 16 is, for example, an N-channel MOS device, a P-channel MOS device, or a complementary MOS device. The doped region 200 is used as a MEMS element such as an electrode of a microphone. A guard ring 17 surrounds the MEMS region 14 to separate the logic circuit region 12 from the MEMS region 14.

After that, a back end process is performed. The back end process includes forming a dielectric layer 18 prior to the substrate 10. Next, a via (or contact window) 20 and a protective plug 22 are formed in the logic layer region 12 and the dielectric layer 18 of the MEMS region 14. The via window 20 is longitudinally connected to the MOS device 16. A guard ring 17 surrounds the MEMS region 14. The method for forming the via 20 and the protection plug 22 is, for example, forming a vertical via opening and an annular trench in the dielectric layer 18 of the logic circuit region 12 and the MEMS region 14, respectively, and then on the dielectric layer 18. And the vertical via opening and the annular trench are filled with a conductive material, and then an etch back or chemical mechanical polishing (CMP) process is performed to remove the conductive material on the dielectric layer 18.

Thereafter, the subsequent process is continued. A wire 24 and a guard ring 26 are formed on the dielectric layer 18 of the logic circuit region 12 and the MEMS region 14, respectively. The wire 24 is electrically connected to the via 20; the guard ring 26 is disposed on and connected to the protective plug 22. The wire 24 and the guard ring 26 are formed by, for example, forming a conductive layer on the dielectric layer 18 and then patterning using a lithography and etching process.

Thereafter, a dielectric layer 28 is formed on the substrate 10 in a manner similar to that described above. Next, a via 30 and a protective plug 32 are formed in the dielectric layer 28 of the logic circuit region 12 and the MEMS region 14. Thereafter, a wire 34 and a guard ring 36 are formed on the dielectric layer 28 of the logic circuit region 12 and the MEMS region 14, respectively. The wire 34 is electrically connected to the via window 30; the guard ring 36 is electrically connected to the protection plug 32.

After that, please refer to FIG. 1B to continue the back-end process. A dielectric layer 38a is formed on the substrate 10. In one embodiment, the dielectric layer 38a has been planarized by a chemical mechanical polishing process. Next, a protective plug 42a is formed in the dielectric layer 38a of the MEMS region 14. Thereafter, a diaphragm 100 of a sandwich structure of the MEMS element is formed on the dielectric layer 38a of the MEMS region 14. The MEMS component is, for example, a MEMS microphone. The diaphragm 100 of the sandwich structure is the other electrode in the MEMS element, which is, for example, in a sandwich structure, including insulating layers 102, 106 and a conductive layer 104 covered by an insulating layer 102 and an insulating layer 106. The insulating layers 102, 106 can offset the stress from the top and bottom. The method for forming the diaphragm 100 of the sandwich structure is, for example, forming a first insulating material layer on the dielectric layer 38a, and then forming a conductive material layer on the first insulating material layer, and then performing a lithography, etching process, and patterning conductive A layer of material is formed to form patterned conductive layer 104. Thereafter, a second insulating material layer is formed on the conductive layer 104, and then a lithography and etching process is performed to pattern the second insulating material layer and the first insulating material layer to form the patterned insulating layer 106 and the insulating layer. 102, the patterned insulating layer 106 and the insulating layer 102 have through holes 107, and the lower dielectric layer 38a is exposed.

Thereafter, a dielectric layer 38b is formed on the substrate 10 in a manner similar to that described above. Next, a via 40 is formed in the dielectric layers 38a and 38b of the logic circuit region 12 to electrically connect the wires 34. Further, a protective plug 42b and a via 43 are formed around the MEMS region 14. The protective plug 42b is disposed on and connected to the diaphragm 100 of the sandwich structure. The via window 43 is electrically connected to the conductive layer 104 of the diaphragm 100 of the sandwich structure. Thereafter, wires 44 and guard rings 46 are formed on the logic layer region 12 and the dielectric layer 38b of the MEMS region 14, respectively. The wire 44 is electrically connected to the vias 40, 43; the guard ring 46 is connected to the protective plug 42b.

Thereafter, please refer to FIG. 1D to continue the back-end process. A dielectric layer 48 is formed on the substrate 10. Next, a via 50 is formed in the dielectric layer 48 of the logic circuit region 12 to electrically connect the wires 44. Also, a protective plug 52 is formed around the MEMS region 14. The protective plug 52 is connected to the guard ring 46. Thereafter, a pad 54 and a guard ring 56 are formed on the dielectric layer 48 of the logic circuit region 12 and the MEMS region 14, respectively. The pad 54 is electrically connected to the via 50. The guard ring 56 is connected to the protective plug 52.

The wires 24, 34, and 44 are laterally extended, and the vias 20, 30, 40, 43, and 50 are longitudinally extended to constitute the metal interconnect 300. The materials of the wires 24, 34, 44 may be the same or different from each other, and the material thereof is, for example, a metal including aluminum, tungsten or an alloy thereof. The materials of the vias 20, 30, 40, 43, 50 may be the same or different from each other, and the material thereof is, for example, a metal, including aluminum, copper, tungsten, titanium, tantalum, a combination of the above, a nitride of the above, or alloy.

The protection rings 17, 26, 36, 46, 56 and the protection plugs 22, 32, 42a, 42b, 52 are all around the MEMS area 14 and stacked on each other to form a protective wall 400 for separating the logic circuit area 12 and Dielectric layers 18, 28, 38a, 38b, 48 of MEMS region 14. The protective rings 17, 26, 36, 46 and the protective plugs 22, 32, 42a, 42b, 52 may be of the same or different material, such as doped polysilicon, deuterated metal, metal such as aluminum or tungsten or alloys thereof. In one embodiment, the material of the guard ring 17 is, for example, the same as the gate of the MOS device 16, such as doped polysilicon or germanium metal; and the material and interlayer of the protection plugs 22, 32, 42a, 42b, 52. The windows 20, 30, 40, 43, 50 are the same, for example, aluminum, copper, tungsten, titanium, tantalum, a combination of the above, a nitride of the above or an alloy thereof; the material of the guard rings 26, 36, 46 and the wires 24 34, 44 are the same, for example, aluminum, tungsten or an alloy thereof.

The dielectric layers 18, 28, 38a, 38b, 48 may each be a single layer or a composite layer composed of a plurality of dielectric materials. The materials may be the same or different, and the material thereof is, for example, ruthenium oxide or a low dielectric constant material having a dielectric constant of less than 4, and the formation method is, for example, chemical vapor deposition, spin coating or other suitable methods.

In the above MEMS device, the materials of the insulating layers 102 and 106 in the diaphragm (or electrode) 100 of the sandwich structure may be the same or different, but different from the materials of the dielectric layers 18, 28, 38a, 38b, and 48. The material may include tantalum nitride or hafnium oxynitride, respectively. The method of forming the insulating layers 102, 106 is, for example, a chemical vapor deposition method or other suitable method. The material of the conductive layer 104 may be a metal such as aluminum, tungsten, titanium or tantalum, and the formation method is, for example, physical vapor deposition, chemical vapor deposition or other suitable methods. In one embodiment, the insulating layers 102, 106 each have a thickness of tens of angstroms to hundreds of angstroms of tantalum nitride; the conductive layer 104 has a thickness of several hundred angstroms.

A protective layer 58 is then formed over the dielectric layer 48 of the logic circuit region 12 and the MEMS region 14. The protective layer 58 covers the pad 54 and the guard ring 56. Thereafter, a portion of the substrate 10 in the MEMS region 14 is removed to form an air cavity 60.

Thereafter, referring to FIG. 1D, a portion of the substrate 10 in the MEMS region 14 and the substrate 10 having the doped regions 200 are removed to form a plurality of openings 62 exposing the dielectric layer 18. Thereafter, the dielectric layer 18 exposed by the opening 62 and the dielectric layers 28, 38a above the opening 62 are removed by an etchant such as a vapor etch gas or a wet etchant, and are transmitted through the insulating layers 102, 106. The vias 107 are etched to remove the dielectric layers 38b, 48 of the MEMS region 14.

Subsequent processes include cutting the substrate into crystals and then packaging, or wafer-level packaging, and then cutting into crystals, as is known to those skilled in the art, and will not be described herein.

The electrode 200 in the above embodiment is illustrated by taking the doping region of the substrate 10 as an example. However, the invention is not limited thereto. The electrode 200 can also be a metal layer or an additional metal layer in the back-end process. The electrode 200 may be disposed between the diaphragm 100 of the sandwich structure and the substrate 10, or on the diaphragm 100 of the sandwich structure, and may be made of a conductive material such as metal or doped polysilicon.

Further, the diaphragm 100 shown in the cross-sectional view only exemplarily shows two through holes 107, but the diaphragm 100 may include a plurality of through holes 107 distributed therein such that the diaphragm 100 has a mesh structure.

In addition, the above description is made by taking a typical method of manufacturing a metal interconnect as an example, but the present invention is not limited thereto. Metal interconnects can also be fabricated using a dual damascene method with copper as the material for the vias (plugs), wires, and guard rings. That is, a dielectric layer is formed first, and then a dual damascene opening is formed in the dielectric layer, including: a trench and a via opening. Thereafter, a conductive material is filled in the trench and the via opening.

The integrated circuit process of the present invention integrates a MEMS component process and a semiconductor process, such as a complementary MOS process. More specifically, after the substrate is fabricated into a semiconductor component, the diaphragm process of the sandwich structure of the MEMS component is integrated with the subsequent metal interconnect process in the semiconductor process. That is, the present invention forms a dielectric layer between adjacent layers of the upper and lower layers, and inserts a step of forming a diaphragm of the sandwich structure of the MEMS element therebetween to be buried in the dielectric layer. Therefore, its process is simple.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10. . . Base

12. . . Logic circuit area

14. . . MEMS area

16. . . Semiconductor component

17, 26, 36, 46, 56. . . Protection ring

18, 28, 38a, 38b, 48. . . Dielectric layer

20, 30, 40, 43, 50. . . Via window

22, 32, 42a, 42b, 52. . . Protection plug

24, 34, 44. . . wire

54. . . Solder pad

58. . . The protective layer

60. . . Air cavity

62. . . Opening

100. . . Sandwich membrane

102, 106. . . Insulation

104. . . Conductive layer

107. . . Through hole

200. . . electrode

300. . . Metal interconnect

400. . . Protective wall

1A-1E are schematic cross-sectional views showing a method of fabricating an integrated circuit of a MEMS device and a semiconductor device according to an embodiment of the invention.

10. . . Base

12. . . Logic circuit area

14. . . MEMS area

16. . . Semiconductor component

17, 26, 36, 46, 56. . . Protection ring

18, 28, 38a, 38b, 48. . . Dielectric layer

20, 30, 40, 43, 50. . . Via window

22, 32, 42a, 42b, 52. . . Protection plug

24, 34, 44. . . wire

54. . . Solder pad

58. . . The protective layer

60. . . Air cavity

62. . . Opening

100. . . Sandwich membrane

102, 106. . . Insulation

104. . . Conductive layer

107. . . Through hole

200. . . electrode

300. . . Metal interconnect

400. . . Protective wall

Claims (17)

An integrated circuit comprising: a substrate comprising a logic circuit region and a microelectromechanical system (MEMS) region; a MOS device on the logic circuit region of the substrate; a plurality of metal interconnects on the substrate Above the logic circuit region, the MOS device is connected, and is composed of a plurality of layer wires and a plurality of via windows; a MEMS device is located in the MEMS region, and includes a sandwich structure diaphragm, An electrode is disposed between any adjacent upper and lower wires of the metal interconnect wires and connected to the metal interconnect wires; and a protective wall surrounds the MEMS region. The integrated circuit of claim 1, wherein the diaphragm of the sandwich structure comprises a first insulating layer, a second insulating layer and a conductive layer located in the first insulating layer and the second insulating layer. between. The integrated circuit of claim 2, wherein the material of the first insulating layer and the second insulating layer is different from the material of a dielectric layer of the metal interconnects. The integrated circuit of claim 2, wherein the material of the first insulating layer and the second insulating layer comprises tantalum nitride or hafnium oxynitride. The integrated circuit of claim 1, further comprising another electrode located in the substrate. A method of manufacturing an integrated circuit, comprising: Providing a substrate comprising a logic circuit region and a MEMS region; forming a MOS device on the logic circuit region of the substrate; forming a plurality of metal interconnections above the logic circuit region of the substrate, connecting the a MOS device, which is composed of a plurality of layer wires and a plurality of vias; a sandwich structure MEMS film is formed over the MEMS region as an electrode, and the metal interconnects are located An upper and lower adjacent two layers of wires are connected to the metal interconnects; and a protective wall is formed in the dielectric layer around the MEMS region of the substrate. A method of fabricating an integrated circuit as described in claim 6, comprising forming a doped region in the substrate of the MEMS region as another electrode. The manufacturing method of the integrated circuit of claim 7, comprising: forming a dielectric layer on the logic circuit region of the substrate and the MEMS region; forming the metal interconnects in the dielectric layer And a diaphragm of the sandwich structure of the MEMS element is formed in the dielectric layer between the lower two adjacent layers of the metal interconnect. The manufacturing method of the integrated circuit of claim 7, further comprising: removing a portion of the substrate on the back side of the substrate to form an air cavity in the MEMS region; Part of the substrate of the doped region is removed to form a plurality of openings to expose the dielectric layer; and the dielectric layer in the protective wall in the MEMS region is removed. The method of manufacturing the integrated circuit of claim 6, wherein the method of forming the diaphragm of the sandwich structure comprises: forming a first insulating layer and a second insulating layer in the dielectric layer; A conductive layer is formed between the first insulating layer and the second insulating layer. The method for manufacturing an integrated circuit according to claim 10, wherein a material of the first insulating layer and the second insulating layer is different from a material of the dielectric layer in the metal interconnects. The method for manufacturing an integrated circuit according to claim 10, wherein the material of the first insulating layer and the second insulating layer comprises tantalum nitride or hafnium oxynitride. A method of manufacturing an integrated circuit, comprising: performing a front-end process to form a semiconductor component on a substrate; after the front-end process, performing a back-end process to form a plurality of metal interconnects over a logic circuit region of the substrate And forming a diaphragm of a sandwich structure of the MEMS microphone element as an electrode, the metal interconnection connecting the semiconductor element and the diaphragm of the sandwich structure; and forming the metal interconnection while forming the metal interconnection A protective wall is formed in the periphery of the diaphragm of the sandwich structure. The method of manufacturing an integrated circuit according to claim 13, wherein the step of forming the diaphragm of the sandwich structure is inserted in the step of forming the metal interconnections. The method of manufacturing an integrated circuit according to claim 13, further comprising forming another electrode in the substrate in the front stage process. The method of manufacturing an integrated circuit according to claim 13, wherein the step of forming the diaphragm of the sandwich structure is performed before the substrate is cut into a crystal. The method of manufacturing an integrated circuit according to claim 13, wherein the step of forming the diaphragm of the sandwich structure is performed before the packaging process is performed.