201113979 UMUU-2009-0051 31875twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種積體電路及其製造方法，且特別 是有關於一種整合MEMS元件與半導體元件之積體電路 及其製造方法。 【先前技術】 微機電系統元件（Microelectromechanical system device，MEMS device)是一種利用微加工技術所製作的微 犁電子機械元件，由於微機電系統元件具有重量輕、體積 小等優點，非常符合目前輕、薄、短、小之電子產品的需 求，因而被廣為研究。目前已發展的微機電系統元件包括 加速度計、開關、電容器、感應器、麥克風等極小的電子 機械元件等。 .以MEMS技術製造的微機電系統麥克風(meMS rmcrophone)除了具有重量輕、體積小以及訊號品質佳等特 性’，微機電祕麥克風逐漸成為微型麥克風的主流。 订動電話是微型麥克風被廣為應用的電子產品，其對 於二克風的收音品質及體積微小化、電路整合性的要求亦 曰益提高，因此，使得微機電純麥克風的需求急速增加。 【發明内容】 ,本發明提供一種積體電路’將MEMS元件與半導體元 件形成在同一基底上。 〃 201113979 uivi^-2009-0051 31875twf.doc/n 本發明提供-種積體電路製程，整合廳細 與半導體元件製程，且製程簡易。 疋件衣私 本發明提出-種積體電路，包括基底、金氧 件、金屬内連線以及赃MS元件。基底包 ™區。金氧半導體元件位於基底之邏輯電路I ’於基底上方’其連接金氧半導體 ，=與多個介層窗所構成。職s元件，位於應疋= 區’其，括二明治結構之振膜，做為電極，位於金屬内連 線中任意相鄰的上、下兩層導線之間且與金屬内連線連接。 〜依照本發明實施_述’上述三_結構之振膜包括 弟-絕緣層、第二絕緣層以及位於第_絕 層之間的導電層。 日/、罘一、名緣 依照本發明實關所述，上料—鱗輕第二 層之材質無金屬内連線中的—介電層的材質不同。 絕緣_所述’上述第一絕緣層與上述第二 絕緣層之材質包括氦化矽或氮氧化矽。 牆 依照本發明實_所述，上述積 環繞於上述MEMS區周圍。 又〇枯保屢 極 依照本發明實施例所述，上述積體電 * 位於MEMS區的該基底之中。 已花乃电 底 本發明又提出-種積體電路的製造 ，匕基底包括邏輯電路區與贿s區。接著== 邂輯電路區上軸金氧半導體元件。錢，祕底上方 成金屬内連線，以連接上述金氧半導體元件^屬内連線 201113979 UMCD-2009-0051 31875twf.doc/n 是由多層導線與多個介層窗所構成。並且於MEMS區上方 形成MEMS元件的三明治結構之振膜。三明治結構之振 膜’其做為電極’位於上述金屬内連線之上、下相鄰兩層 導線之間且與金屬内連線連接。 依照本發明實施例所述，上述製造方法包括在上述 MEMS的上述基底中形成摻雜區，以作為另一電極。 依照本發明實施例所述，上述製造方法包括在上述基 底的邏輯電路區與MEMS區上形成介電層。然後，於介電 層中形成上述金屬内連線，並於上述金屬内連線之上、下 相鄰兩層導線之間的介電層中形成上述MEMS元件之三 明治結構之振膜。 依照本發明實施例所述，上述積體電路的製造方法， 更包括在上述基底的MEMS區周圍的上述介電層中形成 保護牆，接著，從上述基底的背面移除部份基底，以形成 氣腔，之後，齡料上述摻騎之域基底，以形成多 個開口’裸露出上述介電層，之後，移除上述腿廳 上述保護牆内的上述介電層。 依照本發明實施例所述，上述形成上述三明治結構之 振膜的方法包括於上述介電層切成第—絕緣紗第 緣層並在第-絕緣層與第二絕緣層之間形成導電^。〜 依照本發明實施例所述，上述第-絕緣層斑i述第二 絕緣層之材質與上粒屬喊線巾的㈣層的㈣不同了 依照本發明實施例所述，上述第一絕緣層與上述 絕緣層之材質包括氮化矽或氮氧化矽。 201113979 umuu-20〇9-〇〇51 31875twf.doc/n 本發明還提出一種積體電路的製造方法，包括進行前 段製程與進行後段製程。前段製程包括於基底上形成半導 體元件。後段製程在上述前段製程之後進行，包括於上述 基底上形成金屬内連線’並形成MEMS元件的三明治結構 之振膜，以做為電極。金屬内連線連接半導體元件與三明 治結構之振膜。 依照本發明實施例所述，上述三明治結構之振膜是在 鲁 形成上述金屬内連線的過程中形成的。 依照本發明實施例所述，上述積體電路的製造方法， 更包括在上述前段製程中，於上述基底中形成另一電極。 依照本發明實施例所述，上述積體電路的製造方法， 更包括在形成上述金屬内連線的同時，於上述三明治結構 之振膜周緣範圍内形成保護牆。 依照本發明實施例所述，上述形成三明治結構之振膜 之步驟是在上述基底被切割成晶方之前進行的。 依照本發明實施例所述，上述形成三明治結構之振膜 _ 之步驟是在進行封裝之前進行的。. 本發明將MEMS元件與半導體製程，例如是互補式金 氧半導體製程整合。更具體地說，MEMS元件的三明治結 構之振膜埋入於介電層中’與半導體製程中的後段金屬内 連線製程整合，製程簡易。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉實施例’並配合所附圖式作詳細說明如下。 201113979 umiu-2009-0051 31875twf.doc/n 【實施方式】 圖认至® IE是依照本發明實麵所繪衫—種整合 MEMS 7L件與半導體元件之频電路的製衫法的流程· 剖面示意圖。 .月參3圖1A ’提供基底1〇，其包括區域12與14。在 只施例中，區域12為邏輯電路區12 ;區域14為MEMS 區14。以下以邏輯電路區12與mems區14來說明之。 上述基底10之材㈣如是轉體，譬如是料是魏錯。 首先，進仃刖段製程(front end pr〇cess)。前段製程包括在 基底10的邏輯電路區12Jl形成金氧半導 體元件16，並在 MEMS區14形成摻雜區2GG與保護環17。金氧半導體元 件Μ例如是N型通道金氧半導體元件、？型通道金氧半導 體兀件或互補式金氧羊導體元件。摻雜區綱’以作為 MEMS元件例如是麥克風的一個電極。保護環17環繞於 MEMS區14周圍’用以分隔邏輯電路區12與施乂 14。 之後，進行後段製程(back end process)。後段製程包 括先於基底1G_L形齡電層18。接著，在邏輯電路區12 與MEMS區14的介電層18中形成介層窗（或稱為接觸窗） 20以及保護插塞22。介層冑20縱向連接金氧半導體元件 W。保護環17環繞於MEMS區14周圍。介層窗2〇與保 護插塞22的縣方法例如是在賴電純12與脏娜區 14的介電層18中分別形成縱向的介層窗開〇以及環形溝 渠，之後，再於介電層18上以及縱向的介層f開口以'^環 201113979 υ Μ^Ι^-2009-〇〇51 31875twf.doc/n 形溝渠之中填入導電材料，其後， 機械研磨(CMP)製程，以移除介 仃回蝕刻或是化學 其後，繼續進行後段製程。於邏曰輯電2 電:：。 區η的介電層18上分卿成導線 線24與介層窗20電性連接 及保濩％ 26。導 22上並與其連接。導線24=二=置在保護插塞 是在介電声18上带忐道+ a 、、的形成方法例如 成 然:後再利用微影與_製程 的方法’於基底1〇上形成介電層 2中電路區12與Μ_區14的介電層& 中形成”層S 3G以及保護插塞32。其後，於邏輯電路區 I2 ? MEMS區Μ的介電層μ上分別形成導線％以及保 護壞36。導線34與介層窗3〇電性連接；保護環％與保 護插塞32電性連接。 之後，請參照圖1Β，繼續進行後段製程。於基底1〇 上幵》成介電層38a。在一實施例中，介電層38a已以化學 機械研磨製程進行平坦化。接著，在MEMS區14的介電 層38a中形成保護插塞42a。其後，在MEMS區14的介 電層38a上形成MEMS元件的三明治結構之振膜100。 MEMS元件例如是MEMS麥克風。三明治結構之振膜100 是MEMS元件中的另一個電極，其例如是呈三明治結構， 包括絕緣層102、106以及被絕緣層1〇2與絕緣層106包覆 的導電層104。絕緣層102、106可以抵銷來自於上、下的 應變(stress)。三明治結構之振膜1〇〇的形成方法例如是在 201113979 uivx^jl；-2009-005 1 31875twf.doc/n 介電層38a上形成第一絕緣材料層，接著，在第一絕緣材 料層上形成導電材料層’之後，進行微影、蝕刻製裎，圖 案化導電材料層，以形成經圖案化的導電層。其後， 在導電層104上形成苐一絕緣材料層，之後，進行微景<、 钱刻製程，圖案化第二絕緣材料層與第一絕緣材料層，以 形成經圖案化的絕緣層106與絕緣層1〇2，圖案化的絕緣 層106與絕緣層102中具有貫孔107，裸露出下方的介電 層 38a。 其後，以類似於上述的方法，於基底丨〇上形成介電層 38b。接著，在邏輯電路區12的介電層38&與3此中形成 介層窗40’電性連接導線34。並且，於MEMS區14 ^圍 形成保護插塞42b以及介層窗43。保護插塞42b設置在三 明治結構之振膜100上並與其連接。介層窗43與三明治^ 構之振膜100的導電層104電性連接。其後，於邏輯電路 區12與MEMS區14的介電層38b上分別形成導線44以 及保護環46。導線44與介層窗40、43電性連接；保護環 46與保護插塞42b連接。 ^ 其後，請參照圖1D，繼續進行後段製程。於基底 上形成介電層48。接著’在邏輯電路區12的介電層48中 形成介層窗50 ’電性連接導線44。並且，於MEMS區14 周圍形成保護插塞52。保護插塞52連接保護環46。其後， 於邏輯電路區12與MEMS區14的介電層48上分別形成 做為焊墊54以及保護環56。焊墊54與介層窗5〇電性連 接。保護環56與保護插塞52連接。 上述導線24、34、44為橫向延伸，上述介層窗2〇、 201113979 UMUU-2009-0051 31875twf.doc/n 30、40、43、 50為縱向延伸 … ……傅战金屬内連線300。 導線24、34、44材質可以彼此相同或相異，其材質例如是 金屬，包括鋁、鎢或其合金。介層窗2〇、3〇、4〇、43、邓 之材質可以彼此相同或相異，其材質例如是金屬，包括結、 銅、鎮、鈦、组、上述者之組合、上述者之氣化物或其合 金。 上述保護環η、26、36、46、56與保護插塞22、32、 42a、42b、52均環繞於MEMS區14周圍且彼此堆疊共 同組成保賴400,帛以分闕輯電魏12#mems區 14的介電層18、28、38a、38b、48。上述保護環17、％、 36: 46與保護插塞22、32、仏、伽、52之材質可以相 ’例如是摻雜多晶梦、發化金屬、金屬如紹或鶴 實施例保護環17之材質例如是與金氧 ^體讀16之閘極相同者例如是摻 屬;=護插塞22、32、仏、42卜52之材質與介層窗2〇、 :〇、〇广50相同，例如是銘、銅、鎢、鈦、叙、上述 2述者之氮化物或其合金；保護環26、36、46 34、44相同，例如是銘、鶴或其合金。 或θ由^人:18、28、38a、38b、48可以分別是單層， ί疋成的複合層。其材質可以相同或相 Ζ,,Ζ貝9疋氧化矽或是介電常數低於4之低介電常 合=方=方法例如是化學氣相沈積法、旋塗法或其他 上边MEMS tl件巾，三明治結構之振膜（或稱電極） 11 201113979 umuu-2009-005 1 31875twf.doc/n 100中的絕緣層H)2、1G6之材f可以相同或相異，但是盘 上述介電層18、28、38a、38b、48之㈣相異，其材时 分別包括il化吩或氮氧化H緣層102、106的形成方法 例如是化學氣相沈積法或其他合適之方法。導電層⑽之 ，質可，是金屬，例如是叙、鶴、鈦妓，形成方法例如 疋物理軋相沈積法、化學氣相沈積法或其他合適之方法。 在-實施例巾’絕缘層102、1()6的厚度分別為數十埃至數 百埃的氮化矽；導電層1〇4為厚度為數百埃。 而後，於邏輯電路區12及MEMS區Μ的介 上=成保護層58。保護層58覆蓋焊塾54以及保護環曰％。 之後，移除MEMS區14中部分的基底1〇，以形成氣腔6〇。 之後，請參照圖1D，移除meMS區14中部分的基底 10以及具有摻雜區2〇〇的基底1〇，以形成多個開口 a : 18。其後’以蝕刻劑’例如是蒸汽式蝕刻氣 體或疋濕式蝕刻劑，移除開口 62所裸露的介電層18及其 上方的介電層28、38a，並透過絕緣層搬、觸中的貫& 107，#刻移除MEMS區14的介電層38b、48。 貝 其後的製程包括將基底切割成晶方，再進行封裝，或 者，先進行晶圓級封裝，再進行切割成晶方等， 此技藝者所知，於此不再贅述。 此為A悉 =實施例中電極是以在基底1G摻雜區為例說 。…、、而，本發明並不以此為限。電極2〇〇亦可以是後 段製程中的某—層金屬層或額外加人的金屬層 1 可以設置在三明治結構之振膜100與基底10之間，或是位 12 201113979 uivi^jLi-2009-0051 31875twf.d〇c/n 於三明治結構之振膜100之上，其材質可以是金屬或是推 雜多晶矽等可以導電的材質。 / 又，在剖面圖中所示的振膜100僅例示性地顯示出兩 個貫孔107，但振膜100中可包含複數個貫孔1〇7分佈於 其中使得振膜100為網狀結構。 ' 此外，以上是以典型的金屬内連線的製作方法為例來 說明，然而，本發明並不以此為限。金屬内連線亦可以採 用雙重金屬鑲喪的方法來製作並以銅來作為介層窗（插 塞）、導線及保護環的材料。即，先形成介電層，然後在 介電層中形成雙重金屬鑲嵌開口，包括U冓渠與介層'窗開 口。之後，再於溝渠與介層窗開口之中填入導電材^。幵 本發明之積體電路製程整合MEMS元件製程與半導 體製程，例如是互補式金氧半導體製程。更具體地說，在 基底製作半導體元件之後，將MEMS元件的三明治結 振膜製程與半導體製程中的後段金屬内連線製程敕: 即，本發明將上、下兩層相鄰的導線之間的介電=段: ^ ’將形成MEMS元件的三明治結構之振_步驟安= ，、間，使其埋入於介電層中，故，其製程簡易。 、 本發明已以實施例揭露如上，然其並_以限定 發月’任㈣屬技術領域中具有通常知識者， ==和範圍内，當可作些許之更動與潤舞，故本 " 保5蒦乾圍當視後附之申請專利範圍所界定者為準。 13 201113979 UMUJJ-2009-0051 31875twf.doc/n 【圖式簡單說明】 圖1A至圖1E是依照本發明實施例所繪示之一種整合 MEMS元件與半導體元件之積體電路的製造方法的流程 剖面示意圖。 【主要元件符號說明】 10 :基底 12 .邏輯電路區 14 : MEMS 區 16 :半導體元件 17、 26、36、46、56 :保護環 18、 28、38a、38b、48 :介電層 20、30、40、43、50 :介層窗 22、32、42a、42b、52 :保護插塞 24、34、44 :導線 54 :焊墊 58 :保護層60 :氣腔 62 :開口 100 :三明治結構之振膜 102、106 :絕緣層 104 :導電層 107 :貫孔 200 :電極 300 :金屬内連線 400 :保護牆201113979 UMUU-2009-0051 31875twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to an integrated circuit and a method of fabricating the same, and more particularly to an integrated MEMS component and a semiconductor component Integrated circuit and method of manufacturing the same. [Prior Art] Microelectromechanical system device (MEMS device) is a micro-plow electromechanical component fabricated by micromachining technology. Due to its light weight and small size, the microelectromechanical system component is very light and current. The demand for thin, short, and small electronic products has been widely studied. Currently developed MEMS components include very small electromechanical components such as accelerometers, switches, capacitors, inductors, and microphones. In addition to its light weight, small size and good signal quality, the MEMS micro-electromechanical microphone (meMS rmcrophone) has gradually become the mainstream of micro-microphones. The mobile phone is a widely used electronic product for micro-microphones. The demand for the quality, volume and circuit integration of the two-gram wind is also greatly improved. Therefore, the demand for micro-electromechanical pure microphones has increased rapidly. SUMMARY OF THE INVENTION The present invention provides an integrated circuit 'forming a MEMS element and a semiconductor element on the same substrate. 〃 201113979 uivi^-2009-0051 31875twf.doc/n The present invention provides an integrated circuit process, integrated hall and semiconductor component process, and the process is simple. The present invention proposes an integrated circuit comprising a substrate, a gold oxide member, a metal interconnect, and a 赃MS component. Substrate package TM area. The MOS device is located on the logic circuit I' of the substrate above the substrate, which is connected to the MOS, = and a plurality of vias. The s component, located in the area 疋 = zone, includes the diaphragm of the second Meiji structure, as an electrode, located between any adjacent upper and lower wires in the metal interconnect and connected to the metal interconnect. The diaphragm of the above-described three-structure includes a dipole-insulating layer, a second insulating layer, and a conductive layer between the first and second layers. Day/, 罘一, 名缘 According to the practice of the present invention, the material of the second layer of the material-scale is light-free, and the material of the dielectric layer is different. Insulation_the material of the first insulating layer and the second insulating layer includes bismuth telluride or bismuth oxynitride. Wall According to the invention, the above-mentioned product surrounds the MEMS region. Further, in accordance with an embodiment of the present invention, the integrated body* is located in the substrate of the MEMS region. The invention has also been proposed to manufacture an integrated circuit comprising a logic circuit area and a bribe area. Then == 上 电路 circuit area upper axis MOS components. Money, the top of the secret is made into a metal interconnect to connect the above-mentioned MOS semiconductor components. The internal connection line 201113979 UMCD-2009-0051 31875twf.doc/n is composed of a multi-layer wire and a plurality of via windows. And a diaphragm of the sandwich structure of the MEMS element is formed over the MEMS region. The diaphragm of the sandwich structure, which serves as an electrode, is located above the metal interconnect and between the next two adjacent conductors and is connected to the metal interconnect. According to an embodiment of the invention, the above manufacturing method comprises forming a doped region in the substrate of the MEMS as the other electrode. According to an embodiment of the invention, the above manufacturing method includes forming a dielectric layer on the logic circuit region and the MEMS region of the substrate. Then, the metal interconnect is formed in the dielectric layer, and the diaphragm of the three MEMS components of the MEMS element is formed in the dielectric layer between the two adjacent conductors above and below the metal interconnect. According to an embodiment of the invention, the method for fabricating the integrated circuit further includes forming a protective wall in the dielectric layer around the MEMS region of the substrate, and then removing a portion of the substrate from the back surface of the substrate to form The air chamber is then aged to form a plurality of openings to expose the dielectric layer, and then the dielectric layer in the protective wall of the leg room is removed. According to an embodiment of the invention, the method of forming the diaphragm of the sandwich structure comprises cutting the dielectric layer into a first insulating layer and forming a conductive layer between the first insulating layer and the second insulating layer. According to the embodiment of the present invention, the material of the second insulating layer of the first insulating layer is different from the (four) of the (four) layer of the upper squeegee, according to the embodiment of the present invention, the first insulating layer The material of the insulating layer described above includes tantalum nitride or hafnium oxynitride. 201113979 umuu-20〇9-〇〇51 31875twf.doc/n The present invention also proposes a method of manufacturing an integrated circuit, including performing a front-end process and a back-end process. The front stage process includes forming a semiconductor component on the substrate. The back-end process is performed after the above-described front-end process, and includes a film in which a metal interconnection is formed on the above substrate and a sandwich structure of a MEMS element is formed as an electrode. The metal interconnect connects the diaphragm of the semiconductor component and the three-construction structure. According to an embodiment of the invention, the diaphragm of the sandwich structure is formed during the formation of the metal interconnect. According to an embodiment of the invention, the method for fabricating the integrated circuit further includes forming another electrode in the substrate in the preceding process. According to an embodiment of the invention, the method of manufacturing the integrated circuit further includes forming a protective wall in a peripheral portion of the diaphragm of the sandwich structure while forming the metal interconnect. According to an embodiment of the invention, the step of forming the diaphragm of the sandwich structure is performed before the substrate is cut into crystals. According to an embodiment of the invention, the step of forming the diaphragm of the sandwich structure is performed prior to packaging. The present invention integrates MEMS components with semiconductor processes, such as complementary MOS processes. More specifically, the diaphragm of the sandwich structure of the MEMS element is embedded in the dielectric layer' to be integrated with the post-metal interconnection process in the semiconductor process, and the process is simple. The above described features and advantages of the present invention will become more apparent from the description of the appended claims. 201113979 umiu-2009-0051 31875twf.doc/n [Embodiment] Fig. IE is a flow chart of a shirt-making method for integrating a MEMS 7L device and a frequency circuit of a semiconductor component according to the present invention. . The ginseng 3 Figure 1A' provides a substrate 1 〇 comprising regions 12 and 14. In the example only, region 12 is logic circuit region 12; region 14 is MEMS region 14. The logic circuit area 12 and the mems area 14 are explained below. If the material (4) of the above substrate 10 is a rotating body, for example, it is Wei wrong. First, enter the front end pr〇cess. The front stage process includes forming a gold-oxygen semiconductor element 16 in the logic circuit region 12J1 of the substrate 10, and forming a doped region 2GG and a guard ring 17 in the MEMS region 14. The MOS device is, for example, an N-channel MOS device, ? Type channel MOS conductor or complementary MOS conductor element. The doped region is used as a MEMS element such as an electrode of a microphone. A guard ring 17 surrounds the periphery of the MEMS region 14 to separate the logic circuit region 12 from the device 14. After that, a back end process is performed. The back end process includes prior to the substrate 1G_L age electrical layer 18. Next, a via (or contact window) 20 and a protective plug 22 are formed in the dielectric layer 18 of the logic circuit region 12 and the MEMS region 14. The via layer 20 is longitudinally connected to the MOS device W. A guard ring 17 surrounds the MEMS region 14. The county method of the via 2 and the protection plug 22 is, for example, forming a vertical via opening and an annular trench in the dielectric layer 18 of the Laiquan 12 and the Dirna region 14, respectively, and then dielectrically The layer 18 is open on the layer 18 and in the longitudinal direction, and the conductive material is filled in the ^^ ring 201113979 υ Μ^Ι^-2009-〇〇51 31875 twf.doc/n-shaped trench, followed by a mechanical polishing (CMP) process. After removing the dielectric etchback or chemically, the subsequent processing is continued. In the logic of the circuit 2 electricity::. The dielectric layer 18 of the region η is electrically connected to the via 20 and electrically connected to the via 20 . Guide 22 and connect with it. Wire 24 = two = placed on the protective plug is formed on the dielectric sound 18 with a ramp + a, , for example, the method of forming a dielectric on the substrate 1 using a method of lithography and _process A layer S 3G and a protection plug 32 are formed in the dielectric layer & of the circuit region 12 and the Μ-region 14 in the layer 2. Thereafter, wires are respectively formed on the dielectric layer μ of the logic circuit region I2 MEMS region Μ % and protection fault 36. The wire 34 is electrically connected to the via 3 ;; the guard ring % is electrically connected to the protection plug 32. Thereafter, please refer to Fig. 1 Β, continue the back-end process. Dielectric layer 38a. In one embodiment, dielectric layer 38a has been planarized by a chemical mechanical polishing process. Next, a protective plug 42a is formed in dielectric layer 38a of MEMS region 14. Thereafter, in MEMS region 14 The diaphragm 100 of the sandwich structure of the MEMS element is formed on the dielectric layer 38a. The MEMS element is, for example, a MEMS microphone. The diaphragm 100 of the sandwich structure is the other electrode in the MEMS element, which is, for example, in a sandwich structure, including the insulating layer 102. And a conductive layer 104 covered with the insulating layer 106 and the insulating layer 106. The edge layers 102, 106 can offset the stress from the upper and lower sides. The formation method of the diaphragm 1〇〇 of the sandwich structure is, for example, at 201113979 uivx^jl; -2009-005 1 31875twf.doc/n dielectric A first insulating material layer is formed on the layer 38a, and then, after the conductive material layer ' is formed on the first insulating material layer, lithography, etching, and patterning of the conductive material layer are performed to form a patterned conductive layer. Thereafter, a layer of insulating material is formed on the conductive layer 104, and then, a micro-view, a process of engraving, patterning the second layer of insulating material and the first layer of insulating material to form the patterned insulating layer 106 and The insulating layer 1 〇 2, the patterned insulating layer 106 and the insulating layer 102 have through holes 107 to expose the underlying dielectric layer 38a. Thereafter, a dielectric layer is formed on the substrate raft in a manner similar to that described above. 38b. Next, the dielectric layer 38& and the dielectric layer 38' of the logic circuit region 12 are electrically connected to the vial 40'. Further, the protective plug 42b and the via 43 are formed in the MEMS region 14. The protective plug 42b is disposed on the diaphragm 100 of the sandwich structure Connected thereto, the via 43 is electrically connected to the conductive layer 104 of the sandwich diaphragm 100. Thereafter, a wire 44 and a guard ring 46 are formed on the logic layer region 12 and the dielectric layer 38b of the MEMS region 14, respectively. The wire 44 is electrically connected to the vias 40, 43; the guard ring 46 is connected to the protective plug 42b. ^ Thereafter, referring to FIG. 1D, the subsequent process is continued. A dielectric layer 48 is formed on the substrate. A via 50' is formed in the dielectric layer 48 of the circuit region 12 to electrically connect the wires 44. Also, a protective plug 52 is formed around the MEMS region 14. The protective plug 52 is connected to the guard ring 46. Thereafter, a pad 54 and a guard ring 56 are formed on the dielectric layer 48 of the logic circuit region 12 and the MEMS region 14, respectively. The pad 54 is electrically connected to the via 5 . The guard ring 56 is connected to the protective plug 52. The above-mentioned wires 24, 34, 44 are laterally extended, and the above-mentioned vias 2〇, 201113979 UMUU-2009-0051 31875 twf.doc/n 30, 40, 43, 50 are longitudinal extensions ... ... Fu war metal interconnects 300. The materials of the wires 24, 34, 44 may be the same or different from each other, and the material thereof is, for example, a metal including aluminum, tungsten or an alloy thereof. The materials of the vias 2〇, 3〇, 4〇, 43, and Deng may be the same or different from each other, and the material thereof is, for example, metal, including junction, copper, town, titanium, group, combination of the above, the above-mentioned gas a compound or an alloy thereof. The protection rings η, 26, 36, 46, 56 and the protection plugs 22, 32, 42a, 42b, 52 are all surrounded by the MEMS area 14 and stacked on each other to form a Guardian 400, which is divided into 阙 阙 电 电 Wei 12# Dielectric layers 18, 28, 38a, 38b, 48 of mems region 14. The protective ring 17, %, 36: 46 and the protective plugs 22, 32, 仏, gamma, 52 may be made of, for example, a doped polycrystalline dream, a metallized metal, a metal such as a shovel or a crane. The material is, for example, the same as the gate of the gold oxide body read 16, for example, the doped; the material of the plugs 22, 32, 仏, 42 b 52 is the same as that of the via 2 〇, 〇, 〇 50 50 For example, it is a nitride of copper, tungsten, titanium, or the like, or an alloy thereof, and the guard rings 26, 36, 46 34, and 44 are the same, for example, a seal, a crane, or an alloy thereof. Or θ by ^ people: 18, 28, 38a, 38b, 48 can be a single layer, a composite layer. The material may be the same or opposite, the mussel 9 疋 疋 or the low dielectric constant of the dielectric constant less than 4 = square = method such as chemical vapor deposition, spin coating or other upper MEMS tl pieces Diaphragm, sandwich structure diaphragm (or electrode) 11 201113979 umuu-2009-005 1 31875twf.doc/n 100 insulation layer H) 2, 1G6 material f can be the same or different, but the above dielectric layer The (four) of 18, 28, 38a, 38b, and 48 are different, and the method for forming the illuminating phenoxide or the oxynitride H-edge layer 102, 106, respectively, is, for example, a chemical vapor deposition method or other suitable method. The conductive layer (10) may be a metal such as a ruthenium, a crane or a titanium ruthenium, and is formed by a method such as a physical physical vapor deposition method, a chemical vapor deposition method or the like. In the embodiment, the insulating layers 102, 1 (6) have a thickness of tens of angstroms to several hundred angstroms, respectively; the conductive layer 1 〇 4 has a thickness of several hundred angstroms. Then, in the logic circuit region 12 and the MEMS region Μ, the protective layer 58 is formed. The protective layer 58 covers the solder bumps 54 and the protective ring 曰%. Thereafter, a portion of the substrate 1〇 in the MEMS region 14 is removed to form an air cavity 6〇. Thereafter, referring to FIG. 1D, a portion of the substrate 10 in the meMS region 14 and a substrate 1 having a doped region 2 are removed to form a plurality of openings a: 18. Thereafter, the 'etching agent' is, for example, a vapor etch gas or a wet etchant, and the dielectric layer 18 exposed by the opening 62 and the dielectric layers 28 and 38a above it are removed and moved through the insulating layer. The dielectric layers 38b, 48 of the MEMS region 14 are removed. The subsequent processes include cutting the substrate into crystals and then packaging, or wafer-level packaging, and then cutting into crystals, which is known to those skilled in the art and will not be described herein. This is A. The electrode in the embodiment is exemplified by the doped region of the substrate 1G. ..., and, the present invention is not limited thereto. The electrode 2〇〇 may also be a certain metal layer in the back-end process or an additional metal layer 1 may be disposed between the diaphragm 100 of the sandwich structure and the substrate 10, or at position 12 201113979 uivi^jLi-2009- 0051 31875twf.d〇c/n On the diaphragm 100 of the sandwich structure, the material may be a conductive material such as metal or push polycrystalline germanium. Further, the diaphragm 100 shown in the cross-sectional view only exemplarily shows two through holes 107, but the diaphragm 100 may include a plurality of through holes 1〇7 distributed therein such that the diaphragm 100 is a mesh structure. . In addition, the above description is made by taking a typical metal interconnection method as an example, but the present invention is not limited thereto. Metal interconnects can also be fabricated using double metal inlays with copper as the material for the vias (plugs), wires and guard rings. That is, a dielectric layer is formed first, and then a dual damascene opening is formed in the dielectric layer, including a U-channel and a via opening. After that, the conductive material is filled in the opening of the trench and the via window.幵 The integrated circuit process of the present invention integrates MEMS component process and semiconductor process, such as a complementary MOS process. More specifically, after the semiconductor device is fabricated on the substrate, the sandwich junction film process of the MEMS device and the subsequent metal interconnection process in the semiconductor process are: that is, the present invention connects the upper and lower adjacent layers of the wires Dielectric = segment: ^ 'The vibration of the sandwich structure that will form the MEMS component is stepped in, and it is buried in the dielectric layer. Therefore, the process is simple. The present invention has been disclosed above by way of example, and it is also limited to the general knowledge of the technical field in the technical field of the genus of the genus, in the range of == and within the scope, when a little change and dance can be made, therefore, this " The warranty is as defined in the scope of the patent application attached to it. 13 201113979 UMUJJ-2009-0051 31875twf.doc/n [Simplified Schematic] FIG. 1A to FIG. 1E are flow cross-sectional views showing a method of manufacturing an integrated circuit for integrating a MEMS element and a semiconductor element according to an embodiment of the invention. schematic diagram. [Major component symbol description] 10: Substrate 12. Logic circuit area 14: MEMS area 16: Semiconductor element 17, 26, 36, 46, 56: Protection ring 18, 28, 38a, 38b, 48: Dielectric layer 20, 30 , 40, 43, 50: vias 22, 32, 42a, 42b, 52: protection plugs 24, 34, 44: wire 54: pad 58: protective layer 60: air cavity 62: opening 100: sandwich structure Diaphragm 102, 106: insulating layer 104: conductive layer 107: through hole 200: electrode 300: metal interconnect 400: protective wall