TW201320129A - Metal-insulator-metal capacitor structure and method for manufacturing the same - Google Patents

Abstract

A metal-insulator-metal capacitor structure includes a first dielectric layer, a first damascene electrode layer, an etch stop layer, a second dielectric layer and a second damascene electrode layer. The first damascene electrode layer is formed in the first dielectric layer. The etch stop layer covers the first dielectric layer and the first damascene electrode layer, and is a single layer structure. The second dielectric layer is formed on the etch stop layer. The second damascene electrode layer is formed in the second dielectric layer, is located on the first damascene electrode layer, and is contacted with the etch stop layer. The metal-insulator-metal capacitor structure can further includes a dual damascene structure formed in the second dielectric layer and the etch stop layer and electrically connected to the first damascene electrode layer. A method for manufacturing the metal-insulator-metal capacitor structure is also provided.

Description

Metal-insulation layer-metal capacitor structure and manufacturing method thereof

The present invention relates to a capacitor structure, and more particularly to a Metal-Insulator-Metal Capacitor (MIMCAP) structure and a method of fabricating the same.

The metal-insulator-metal capacitor is usually composed of an insulating layer and two metal electrodes separated by an insulating layer, which have the advantages of small size, stable capacitance, and small parasitic effect.

With the development of integrated circuit technology, metal-insulator-metal capacitors have been widely used. In order to realize the electrical connection between the metal-insulating layer-metal capacitor and other electronic components in the integrated circuit, at present, the metal-insulating layer-metal capacitor is usually integrated with the internal connection structure of the integrated circuit. However, in the conventional integrated circuit technology, the process steps of integrating the metal-insulating layer-metal capacitor and the interconnect structure are numerous, and it is usually required to perform multiple depositions and etching of the insulating layer and the metal layer, thereby causing an increase in manufacturing cost. It also complicates the integrated structure of the metal-insulator-metal capacitor and the interconnect structure.

In view of this, the present invention provides a metal-insulating layer-metal capacitor structure, which has a simple structure and is advantageous for reducing manufacturing costs.

The invention provides a metal-insulating layer-metal capacitor structure manufacturing method, which has simple manufacturing steps and is advantageous for reducing the manufacturing cost.

To achieve the above and other advantages, the present invention provides a metal-insulating layer-metal capacitor structure including a first dielectric layer, a first electrode layer, an insulating barrier layer, a second dielectric layer, and a second electrode layer. The first electrode layer is embedded in the first dielectric layer. The insulating barrier layer covers the first dielectric layer and the first electrode layer, and the insulating barrier layer has a single layer structure. The second dielectric layer is on the insulating barrier layer. The second electrode layer is embedded in the second dielectric layer and is located above the first electrode layer to be in contact with the insulating barrier layer.

In an embodiment of the invention, the material of the insulating barrier layer comprises tantalum nitride (SiN), tantalum carbide (SiC), niobium oxynitride (SiCN) or niobium oxynitride (SiON).

In an embodiment of the invention, the material of the first electrode layer and the second electrode layer is copper.

To achieve the above and other advantages, the present invention provides a metal-insulating layer-metal capacitor structure including a first dielectric layer, a first electrode layer, an insulating barrier layer, a second dielectric layer, a second electrode layer, and a dual damascene ( Dual damascene) structure. The first electrode layer is embedded in the first dielectric layer. An insulating barrier layer is formed on the first dielectric layer and the first electrode layer. A second dielectric layer is formed on the insulating barrier layer. The second electrode layer is embedded in the second dielectric layer and is located above the first electrode layer to be in contact with the insulating barrier layer. The dual damascene structure is embedded in the second dielectric layer and the insulating barrier layer to be electrically connected to the first electrode layer.

In an embodiment of the invention, the insulating barrier layer is a single layer structure.

In an embodiment of the invention, the material of the insulating barrier layer comprises tantalum nitride, tantalum carbide, niobium nitrite or niobium oxynitride.

In an embodiment of the invention, the material of the first electrode layer and the second electrode layer is copper.

In an embodiment of the invention, the second electrode layer is the same material as the dual damascene structure.

In an embodiment of the invention, the insulating barrier layer is a composite layer structure. The composite layer structure includes a first insulating layer on the first dielectric layer and a second insulating layer on the first insulating layer. The material of the first insulating layer includes tantalum nitride, tantalum carbide, niobium nitrite or niobium oxynitride. The material of the second insulating layer includes undoped silicate glass (USG), yttrium oxide (Ta ₂ O ₅ ), zirconia (ZrO ₂ ) or aluminum oxide (Al ₂ O ₃ ).

To achieve the above and other advantages, the present invention provides a method of fabricating a metal-insulator-metal capacitor structure comprising the following steps. A first opening is formed in the first dielectric layer. The first electrode layer is filled in the first opening. An insulating barrier layer is formed to cover the first dielectric layer and the first electrode layer, and the insulating barrier layer has a single layer structure. A second dielectric layer is formed on the insulating barrier layer. A second opening is formed in the second dielectric layer, wherein the second opening is over the first electrode layer and exposes a portion of the insulating barrier layer. The second electrode layer is filled in the second opening to bring the second electrode layer into contact with the insulating barrier layer.

In an embodiment of the invention, the material of the insulating barrier layer comprises tantalum nitride, tantalum carbide, niobium nitrite or niobium oxynitride.

In an embodiment of the invention, the material of the first electrode layer and the second electrode layer is copper.

In an embodiment of the invention, the method further includes forming a dual damascene opening in the second dielectric layer and the insulating barrier layer, the dual damascene opening being over the first electrode layer and exposing a portion of the first electrode layer; And filling the dual damascene opening into the dual damascene opening, electrically connecting to the first electrode layer.

In an embodiment of the invention, forming the dual damascene opening described above comprises the following steps. First, when the second opening is formed, a third opening is simultaneously formed in the second dielectric layer, and the third opening is located above the first electrode layer and exposes a portion of the insulating barrier layer. Then, a portion of the insulating barrier layer exposed by the third opening is removed to form a dual damascene opening of the exposed first electrode layer.

In an embodiment of the invention, removing a portion of the insulating barrier layer exposed by the third opening includes the following steps. First, a patterned mask layer is formed on the second dielectric layer to cover the second opening and expose the third opening. Then, the portion of the insulating barrier layer exposed by the patterned mask layer is removed. After that, the patterned mask layer is removed.

The metal-insulating layer-metal capacitor structure of the embodiment of the invention and the manufacturing method thereof are formed by using a damascene technique to form the first electrode layer and the second electrode layer, and separating the first electrode layer by a single-layer insulating barrier layer And a second electrode layer. Since the insulating barrier layer of the single-layer structure is not only used as an insulating layer in the capacitor structure, but also can be used as an etching barrier layer when forming the second electrode layer, so that the formed metal-insulating layer-metal capacitor structure is simple. Helps reduce production costs. In another embodiment, the metal-insulating layer-metal capacitor structure further includes a dual damascene structure formed in the second dielectric layer and the insulating barrier layer and electrically connected to the first electrode layer. The dual damascene structure can be fabricated in the same process as the second electrode layer, thereby simplifying the integration structure of the metal-insulating layer-metal capacitor and the inner connecting structure and the manufacturing steps, thereby reducing the manufacturing cost.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

1A to 1E are schematic views showing a method of fabricating a metal-insulating layer-metal capacitor according to a first embodiment of the present invention.

Referring to FIG. 1A, in the embodiment, first, the first electrode layer 120 is inlaid in the first dielectric layer 110 by, for example, a damascene technique. Specifically, a first opening 112 is formed in the first dielectric layer 110, and a metal layer (for example, a copper layer) is deposited on the surface of the first dielectric layer 110 and filled into the first opening 112, after which the chemical mechanical mechanism is utilized. A chemical mechanical polishing (CMP) process removes a metal layer other than the first opening 112 to form a first electrode layer 120 located within the first opening 112. In the present embodiment, the first electrode layer 120 is a copper damascene layer.

Referring to FIG. 1B , an insulating barrier layer 130 is formed to cover the first dielectric layer 110 and the first electrode layer 120 . The insulating barrier layer 130 has a single layer structure, and its material includes, for example, tantalum nitride (SiN), tantalum carbide (SiC), tantalum niobium carbide (SiCN), niobium oxynitride (SiON), or other materials having a high dielectric constant. In the present embodiment, the dielectric constant of the insulating barrier layer 130 is, for example, 5. The thickness of the insulating barrier layer 130 is, for example, between 200 Å and 1500 Å.

Referring to FIG. 1C, a second dielectric layer 140 is formed on the insulating barrier layer 130. In the present embodiment, the material of the first dielectric layer 110 and the second dielectric layer 140 is, for example, an oxide.

Referring to FIGS. 1D to 1E, in the present embodiment, the second electrode layer 150 is inlaid in the second dielectric layer 140 by, for example, a damascene technique. Specifically, referring to FIG. 1D, a second opening 142 is formed in the second dielectric layer 140. The second opening 142 is located above the first electrode layer 120 and exposes a portion of the insulating barrier layer 130.

In the above, when the second opening 142 is formed in the second dielectric layer 140, the insulating barrier layer 130 can be used as an etch stop layer, that is, the etching selectivity ratio between the second dielectric layer 140 and the insulating barrier layer 130 is utilized. The insulating barrier layer 130 is stopped using an etching process that etches the second dielectric layer 140. Therefore, after the second opening 142 is formed, a portion of the insulating barrier layer 130 is exposed by the second opening 142.

Referring to FIG. 1E, a metal layer (for example, a copper layer) is deposited on the surface of the second dielectric layer 140, and is filled in the second opening 142 to cover the insulating barrier layer 130, and then the second opening is removed by a chemical mechanical polishing process. A metal layer other than 142, thereby forming a second electrode layer 150 located within the second opening 142 and in contact with the insulating barrier layer 130. In the present embodiment, the second electrode layer 150 is a copper damascene layer.

After the second electrode layer 150 is formed, the metal-insulating layer-metal capacitor structure 100 of the present embodiment is substantially formed. In detail, the metal-insulating layer-metal capacitor structure 100 includes a first dielectric layer 110, a first electrode layer 120, an insulating barrier layer 130, a second dielectric layer 140, and a second electrode layer 150. The first electrode layer 120 is embedded in the first dielectric layer 110. The insulating barrier layer 130 covers the first dielectric layer 110 and the first electrode layer 120, and the insulating barrier layer 130 has a single layer structure. The second dielectric layer 140 is on the insulating barrier layer 130. The second electrode layer 150 is embedded in the second dielectric layer 140 and is located above the first electrode layer 120 to be in contact with the insulating barrier layer 130.

In particular, in the metal-insulating layer-metal capacitor structure 100, the insulating barrier layer 130 is further used as a dielectric layer separating the first electrode layer 120 and the second electrode layer 150. Therefore, in the process of fabricating the metal-insulating layer-metal capacitor structure 100 of the embodiment, it is not necessary to additionally deposit the dielectric layer between the two electrodes, thereby not only reducing the manufacturing cost, but also fabricating the structure. Simple metal-insulator-metal capacitor structure 100.

It should be noted that in the process of forming the second opening 142, a portion of the insulating barrier layer 130 may also be etched away due to over etch. Therefore, after the second opening 142 is formed, the remaining thickness of the insulating barrier layer 130 is determined by the thickness of the original deposition and the etching rate of the etching solution for etching the second dielectric layer 140 to the insulating barrier layer 130.

According to the above-described method of fabricating the metal-insulating layer-metal capacitor structure 100, the fabrication of the metal-insulating layer-metal capacitor structure 100 can be integrated with the fabrication of the interconnect structure in the integrated circuit. 2 is a schematic view of a metal-insulating layer-metal capacitor structure and an inner connecting structure. Referring to FIG. 2, in the present embodiment, the illustrated inner connecting structure 30 is, for example, a dual damascene inner connecting structure including wire layers 31, 32 and contact plugs 33, 34. In the embodiment, the inner connecting structure 30 is formed in the first dielectric layer 110 and the second dielectric layer 140. The wire layer 31 and the contact plug 33 can be fabricated simultaneously with the first electrode layer 110, and the wire layer 32 and the contact plug 34 can be fabricated simultaneously with the second electrode layer 150. It should be noted that the insulating barrier layer 130 may not be formed between the first dielectric layer 110 and the second dielectric layer 140 in the region where the interconnect structure 30 is formed.

3A to 3H are schematic views showing a method of fabricating a metal-insulating layer-metal capacitor according to a second embodiment of the present invention.

Referring to FIG. 3A, in the embodiment, first, the first electrode layer 220 is inlaid in the first dielectric layer 210 by using a damascene technique. Specifically, a first opening 212 is formed in the first dielectric layer 210, and a metal layer (for example, a copper layer) is deposited on the surface of the first dielectric layer 210, and is filled in the first opening 212, and then chemistry is utilized. The mechanical polishing process removes the metal layer outside the first opening 212 to form the first electrode layer 220 located within the first opening 212. In the present embodiment, the first electrode layer 220 is a copper damascene layer.

Referring to FIG. 3B, an insulating barrier layer 230 is formed to cover the first dielectric layer 210 and the first electrode layer 220. The insulating barrier layer 230 may have a single layer structure. The material of the insulating barrier layer 230 includes, for example, tantalum nitride (SiN), tantalum carbide (SiC), niobium lanthanum carbide (SiCN), niobium oxynitride (SiON), or other materials having a high dielectric constant. The thickness of the insulating barrier layer 130 is, for example, between 200 Å and 1500 Å. The insulating barrier layer 230 may also be a composite layer structure, for example, including a first insulating layer formed on the first dielectric layer 210 and the first electrode layer 220, and a second insulating layer formed on the first insulating layer On an insulating layer. The material of the first insulating layer comprises tantalum nitride (SiN), tantalum carbide (SiC), niobium oxynitride (SiCN) or niobium oxynitride (SiON), and the material of the second insulating layer includes (undoped silicate galss, USG) Or other materials having a high dielectric constant such as tantalum oxide (Ta ₂ O ₅ ), zirconium oxide (ZrO ₂ ), or aluminum oxide (Al ₂ O ₃ ). The thickness of the first insulating layer is, for example, between 200 Å and 1500 Å. The thickness of the second insulating layer is, for example, between 100 angstroms and 1000 angstroms.

Referring to FIG. 3C, a second dielectric layer 240 is formed on the insulating barrier layer 230. In the present embodiment, the material of the first dielectric layer 210 and the second dielectric layer 240 is, for example, an oxide. The method of fabricating the metal-insulating layer-metal capacitor of the present embodiment is different from the method of fabricating the metal-insulating layer-metal capacitor of the first embodiment in the step after the second dielectric layer 240 is formed.

Referring to FIGS. 3D to 3H, in the present embodiment, for example, a second electrode layer 250 is inlaid in the second dielectric layer 240 by using a damascene technique, and the second dielectric layer 240 is used by using a dual damascene technique. A dual damascene structure 260 is inlaid in the insulating barrier layer 230. It should be noted that the second electrode layer 250 and the dual damascene structure 260 are substantially fabricated using the same damascene process.

Specifically, referring to FIG. 3D , in the embodiment, the second opening 242 and the third opening 244 are formed in the second dielectric layer 240 . The second opening 242 and the third opening 244 are both located above the first electrode layer 220 and respectively expose a portion of the insulating barrier layer 230. The third opening 244 includes a trench 245 and a via 246, and the trench 245 is above the via 246 and is in communication with the via 246. In this embodiment, the third opening 244 includes a trench 245 and a corresponding via 246. In other embodiments, the third opening 244 can also include a trench and a corresponding plurality of via holes. In other words, the number and arrangement of the trenches 245 and vias 246 are determined based on the actual needs of the interconnects. It should be noted that the third opening 244 may be fabricated in a trench first manner, or may be formed in a via first manner, or may be self-aligned. (self-aligned) is made and will not be described in detail here.

The method of forming the second opening 242 and the third opening 244 is, for example, a photolithography method. When the second opening 242 and the third opening 244 are formed in the second dielectric layer 240, the insulating barrier layer 230 can be utilized as an etch stop layer, that is, etching between the second dielectric layer 240 and the insulating barrier layer 230. The selection ratio is stopped using the etching process to etch the second dielectric layer 240 to the insulating barrier layer 230. Therefore, after the second opening 242 and the third opening 244 are formed, the partial insulating barrier layer 230 is exposed by the second opening 242 and the third opening 244, respectively.

It should be noted that a portion of the insulating barrier layer 230 may also be etched by over etch during the formation of the second opening 242 and the third opening 244, and thus, the second opening 242 and the third opening 244 are formed. Thereafter, the remaining thickness of the insulating barrier layer 230 is determined by the thickness of the original deposition and the etching rate of the etching solution for etching the second dielectric layer 240 for the insulating barrier layer 230.

Thereafter, a portion of the insulating barrier layer 230 exposed by the third opening 244 is removed to form a dual damascene opening 262 of the exposed first portion of the electrode layer 220. In this embodiment, referring to FIG. 3E , first, a patterned mask layer 270 is formed on the second dielectric layer 240 to cover the second dielectric layer 240 and the second opening 242 and expose the third opening 244 . In detail, the material of the patterned mask layer 270 is, for example, a photoresist material.

Referring to FIG. 3F, the insulating barrier layer 230 of the portion of the third opening 244 that is not covered by the patterned mask layer 270 is then removed. For example, the portion of the insulating barrier layer 230 exposed by the third opening 244 may be etched using an etchant capable of etching the insulating barrier layer 230, or the portion exposed by the third opening 244 may be removed by other suitable means. The insulating barrier layer 230. Referring to FIG. 3G, the patterned mask layer 270 is removed, thereby forming a dual damascene opening 262 to expose a portion of the first electrode layer 220.

Referring to FIG. 3H, a metal layer (eg, a copper layer) is deposited on the surface of the second dielectric layer 240 to fill the second opening 242 and the dual damascene opening 262. The second opening 242 and the metal layer outside the dual damascene opening 262 are then removed using a chemical mechanical polishing process to form a second electrode layer 250 at the second opening 242 and a dual damascene structure 260 at the dual damascene opening 262. The second electrode layer 250 located at the second opening 242 is in contact with the insulating barrier layer 230 , and the dual damascene structure 260 located at the dual damascene opening 262 is electrically connected to the first electrode layer 220 . In this embodiment, the second electrode layer 250 and the dual damascene structure 260 have the same material, such as copper.

Referring to FIG. 3H, the metal-insulating layer-metal capacitor structure 200 fabricated by the metal-insulating layer-metal capacitor manufacturing method of the embodiment includes a first dielectric layer 210, a first electrode layer 220, and an insulating barrier. Layer 230, second dielectric layer 240, second electrode layer 250, and dual damascene structure 260. The first electrode layer 220 is embedded in the first dielectric layer 210. The insulating barrier layer 230 is formed on the first dielectric layer 210 and the first electrode layer 220. The second dielectric layer 240 is formed on the insulating barrier layer 230. The second electrode layer 250 is embedded in the second dielectric layer 240 and is located above the first electrode layer 110 to be in contact with the insulating barrier layer 230. The dual damascene structure 260 is embedded in the second dielectric layer 240 and the insulating barrier layer 230 , and is disposed above the first electrode layer 220 and electrically connected to the first electrode layer 220 .

In this embodiment, the second electrode layer 250 and the dual damascene structure 260 are simultaneously fabricated by using damascene technology, which not only simplifies the integration of the metal-insulating layer-metal capacitor structure 200 of the interconnect structure, but also eliminates the need for additional metal layers and insulation. The deposition of layers helps to reduce the manufacturing cost. Moreover, in this embodiment, the insulating barrier layer 230 is used as the etch stop layer for forming the second opening 242 and the insulating layer between the first electrode layer 220 and the second electrode layer 250, so that no additional film deposition process is required. .

According to the above-described method of fabricating the metal-insulator-metal capacitor structure 200, the fabrication of the metal-insulator-metal capacitor structure 200 can be integrated with the fabrication of the interconnect structure in the integrated circuit. 4 is a schematic view of a metal-insulating layer-metal capacitor structure and an inner connecting structure. Referring to FIG. 4 , in the embodiment, the illustrated internal connection structure 40 is, for example, a dual damascene inner connection structure including a first wire layer 41 , a second wire layer 42 , and contact plugs 43 , 44 . In the embodiment, the inner connecting structure 40 is formed in the first dielectric layer 210 and the second dielectric layer 240. The first wire layer 41 and the contact plug 43 can be fabricated simultaneously with the second electrode layer 250 and the dual damascene structure 260, and the second wire layer 42 and the contact plug 44 can be fabricated simultaneously with the first electrode layer 220. It should be noted that the insulating barrier layer 230 may not be formed between the first dielectric layer 210 and the second dielectric layer 240 in the region where the interconnect structure 40 is formed.

The metal-insulating layer-metal capacitor structure of the embodiment of the invention and the manufacturing method thereof are to form the first electrode layer and the second electrode layer by using a damascene technique, and simultaneously use the insulating barrier layer as the etching for forming the second opening The termination layer and the insulating layer for spacing the first electrode layer and the second electrode layer make the formed metal-insulator-metal capacitor structure simple, which is advantageous for reducing the manufacturing cost. In another embodiment, the metal-insulating layer-metal capacitor structure further includes a dual damascene structure formed in the second dielectric layer and the insulating barrier layer and electrically connected to the first electrode layer. The dual damascene structure can be fabricated in the same process as the second electrode layer, thereby simplifying the integration structure of the metal-insulating layer-metal capacitor and the inner connecting structure and the manufacturing steps, thereby reducing the manufacturing cost.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

30, 40. . . Internal connection structure

31, 32. . . Wire layer

33, 34, 43, 44. . . Contact plug

41. . . First wire layer

42. . . Second wire layer

100, 200. . . Metal-insulator-metal capacitor structure

110, 210. . . First dielectric layer

112, 212. . . First opening

120, 220. . . First electrode layer

130, 230. . . Insulating barrier

140, 240. . . Second dielectric layer

142, 242. . . Second opening

244. . . Third opening

245. . . ditch

246. . . Via hole

150, 250. . . Second electrode layer

260. . . Double mosaic structure

262. . . Double inlaid opening

270. . . Patterned mask layer

1A to 1E are schematic views showing a method of fabricating a metal-insulating layer-metal capacitor structure according to a first embodiment of the present invention.

2 is a schematic view showing a metal-insulating layer-metal capacitor structure and an inner connecting structure according to a first embodiment of the present invention.

3A to 3H are schematic views showing a method of fabricating a metal-insulating layer-metal capacitor structure according to a second embodiment of the present invention.

4 is a schematic view of a metal-insulating layer-metal capacitor structure and an inner connecting structure.

100. . . Metal-insulator-metal capacitor structure

110. . . First dielectric layer

112. . . First opening

120. . . First electrode layer

130. . . Insulating barrier

140. . . Second dielectric layer

142. . . Second opening

150. . . Second electrode layer

Claims (16)

A metal-insulating layer-metal capacitor structure includes: a first dielectric layer; a first electrode layer embedded in the first dielectric layer; an insulating barrier layer covering the first dielectric layer and the first An electrode layer, the insulating barrier layer has a single layer structure; a second dielectric layer is disposed on the insulating barrier layer; and a second electrode layer is embedded in the second dielectric layer and located at the first electrode Above the layer, it is in contact with the insulating barrier layer. The metal-insulating layer-metal capacitor structure according to claim 1, wherein the material of the insulating barrier layer comprises tantalum nitride, tantalum carbide, niobium nitrite or niobium oxynitride. The metal-insulating layer-metal capacitor structure according to claim 1, wherein the first electrode layer and the second electrode layer are made of copper. A metal-insulating layer-metal capacitor structure comprising: a first dielectric layer; a first electrode layer embedded in the first dielectric layer; an insulating barrier layer on the first dielectric layer and the first An electrode layer is disposed on the insulating barrier layer; a second electrode layer is embedded in the second dielectric layer and located above the first electrode layer to be in contact with the insulating barrier layer And a dual damascene structure, embedded in the second dielectric layer and the insulating barrier layer, and located above the first electrode layer and electrically connected to the first electrode layer. The metal-insulating layer-metal capacitor structure according to claim 4, wherein the insulating barrier layer has a single layer structure. The metal-insulating layer-metal capacitor structure according to claim 4, wherein the material of the insulating barrier layer comprises tantalum nitride, tantalum carbide, niobium oxynitride or niobium oxynitride. The metal-insulating layer-metal capacitor structure according to claim 5, wherein the material of the first electrode layer and the second electrode layer is copper. The metal-insulating layer-metal capacitor structure according to claim 5, wherein the second electrode layer is made of the same material as the dual damascene structure. The metal-insulating layer-metal capacitor structure according to claim 4, wherein the insulating barrier layer is a composite layer structure. The metal-insulating layer-metal capacitor structure according to claim 9, wherein the composite layer structure is located on the first dielectric layer and the first insulating layer and the second insulating layer The insulating layer, the material of the first insulating layer comprises tantalum nitride, tantalum carbide, niobium oxynitride or niobium oxynitride, and the material of the second insulating layer comprises undoped bismuth glass, yttria or zirconia, alumina. A method for fabricating a metal-insulating layer-metal capacitor structure includes: forming a first opening in a first dielectric layer; filling a first electrode layer in the first opening; forming an insulating barrier layer, covering The first dielectric layer and the first electrode layer, the insulating barrier layer has a single layer structure; a second dielectric layer is formed on the insulating barrier layer; and a second opening is formed in the second dielectric layer. Wherein the second opening is located above the first electrode layer and exposes a portion of the insulating barrier layer; and the second opening is filled with a second electrode layer to contact the second electrode layer with the insulating barrier layer . The manufacturing method of claim 11, wherein the material of the insulating barrier layer comprises tantalum nitride, tantalum carbide, niobium nitrite or niobium oxynitride. The manufacturing method of claim 11, wherein the material of the first electrode layer and the second electrode layer is copper. The manufacturing method of claim 11, further comprising: forming a double damascene opening in the second dielectric layer and the insulating barrier layer, the dual damascene opening being located above the first electrode layer and exposing a portion The first electrode layer; and the dual damascene opening is filled with a dual damascene structure electrically connected to the first electrode layer. The method according to claim 14, wherein the forming the dual damascene opening comprises: forming a third opening simultaneously in the second dielectric layer, the third opening being located in the second opening a portion of the insulating barrier layer is exposed over an electrode layer; and a portion of the insulating barrier layer exposed by the third opening is removed to form the dual damascene opening of the exposed first electrode layer. The manufacturing method of claim 15, wherein removing the portion of the insulating barrier layer exposed by the third opening comprises: forming a patterned mask layer on the second dielectric layer to cover the second Opening and exposing the third opening; removing the portion of the insulating barrier layer exposed by the patterned mask layer; and removing the patterned mask layer.