TWI480991B - Package structure and package substrate thereof - Google Patents

Description

Package structure and package substrate thereof

The present invention relates to a package structure, and more particularly to a package structure for eliminating the use of a solder mask layer and a package substrate thereof.

With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional, high-performance research and development. In order to meet the packaging requirements of semiconductor package high integration and miniaturization, the package substrate carrying the semiconductor wafer gradually evolves from a single-layer board to a multi-layer board, which is limited to a limited space. Next, an interlayer connection technology (Interlayer Connection) is used to expand the available circuit area on the package substrate to meet the demand for the use of a high electronic density integrated circuit.

At present, a package substrate for carrying a semiconductor wafer includes a wire-bonded package substrate, a chip-scale package (CSP) substrate, and a flip-chip substrate (FCBGA); and is required for operation of a microprocessor, a wafer set, and a graphics chip. The circuit board with wiring also needs to improve the quality of the transmitted chip signal, improve the bandwidth, control the impedance, etc., in response to the development of high I/O number packages.

The wire bonding is formed by forming a corresponding wire pad on a package substrate, and the semiconductor wafer is placed on the crystallographic region of the package substrate with its non-active surface, and is wired with a wire such as a gold wire. Bonding electrically connected to the bonding pad of the package substrate and the electrode pad of the semiconductor wafer, and electrically connecting the semiconductor wafer to the package substrate.

1A and 1B are cross-sectional and top views of a conventional package substrate for wire bonding a semiconductor wafer; as shown, a wiring layer 12 is disposed on the dielectric layer 110 of the substrate body 11, and The circuit layer 12 has a plurality of wire pads 121 and conductive vias 120 (shown in FIG. 1B ) disposed in the dielectric layer 110 , such that the circuit layer 12 is electrically connected to the internal lines through the conductive vias 120 ( A solder resist layer 13 is formed on the substrate body 11 and the circuit layer 12, and the solder resist layer 13 is provided with an opening 130, so that the wire pads 121 are exposed in the opening 130, and the wires are exposed. A surface treatment layer 122 is formed on the pad 121. A soldering region 131 is further disposed on the solder resist layer 13, and the bonding pad 121 surrounds the crystallizing region 131. The semiconductor wafer 14 is connected to the crystallizing region 131. The semiconductor wafer 14 has an active surface 14a and a non-active layer. The surface 14b, and the non-active surface 14b is connected to the crystallizing area 131 by a bonding material 15, and the active surface 14a has a plurality of electrode pads 141, and is electrically connected to the semiconductor wafer 14 by a wire 16 such as a gold wire. The electrode pad 141 and the wire pad 121 electrically connect the semiconductor wafer 14 to the substrate body 11.

However, the solder resist layer 13 must be formed on the substrate body 11 and the wiring layer 12 described above, so that the thickness of the entire package substrate is increased, and the thinness cannot be achieved.

Moreover, it is known that most (greater than 80%) conductive blind holes (not shown) are away from the wire pad 121, and only a small portion of the conductive blind holes 120 (as shown in FIG. 1B) are adjacent to the wire pad 121. The inner wiring is fanned out on the dielectric layer 110 by the conductive via hole 120, that is, the dielectric layer 110 is covered with the circuit layer 12, resulting in a spacing between the bonding pads 121. The pitch is limited by the wiring requirements of the circuit layer 12, that is, some of the wires must be disposed between adjacent wire pads 121 (not shown), so that the spacing between the wire pads 121 cannot be reduced. The purpose of fine pitch.

When the solder resist layer 13 is formed on the dielectric layer 110 and the circuit layer 12, the solder resist layer 13 has a certain degree of conformity, so that the surface of the solder resist layer 13 follows the circuit layer 12. The distribution of the high and low undulations (as shown in FIG. 1A) results in uneven thickness and flatness of the surface of the solder resist layer 13; thus, when the semiconductor wafer 14 is attached to the crystallized region 131 where the surface is uneven At the same time, the semiconductor wafer 14 is easily broken, especially an ultra-thin semiconductor wafer, and thus is disadvantageous for a multilayer wafer stack or a thin package.

Therefore, how to provide a package structure to avoid the above-mentioned various defects due to the uneven thickness of the solder resist layer and the poor surface flatness in the prior art has become an urgent problem to be overcome in the industry.

In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a package structure and a package substrate thereof, which eliminates the use of a solder resist layer, thereby avoiding the thickness unevenness of the solder resist layer and the lack of surface flatness.

Another object of the present invention is to provide a package structure and a package substrate thereof, and the spacing between the wire pads is not limited to the wiring layer wiring.

To achieve the above and other objects, the present invention provides a package substrate comprising: a substrate body having an external dielectric layer on a surface thereof, and having at least one internal wiring layer, and defining on the exposed surface of the external dielectric layer Forming at least one crystallographic region; a plurality of wire bonding pads are formed on the exposed surface of the external dielectric layer and surrounding the crystallizing region, and each of the wire bonding pads has a conductive line segment, and each of the conductive wire segments has a first end and a second And the first end is electrically connected to the wire pad; and the plurality of conductive blind holes are disposed in the external dielectric layer and respectively electrically connected to the second end of each of the conductive segments and the internal circuit layer. The wire mats are fanned out by the inner circuit layer.

The present invention further provides a package structure comprising: a substrate body having an external dielectric layer on a surface thereof, and having at least one internal wiring layer, and defining at least one crystal region on the exposed surface of the external dielectric layer a plurality of wire pads are formed on the outer dielectric layer and surround the crystallographic region, and each of the wire pads has a conductive line segment, and each of the conductive segments has a first end and a second end, and the first end corresponds to Electrically connected to the wire pad; a plurality of conductive blind holes are disposed in the external dielectric layer and electrically connected to the second end of each of the conductive segments and the internal circuit layer, respectively, for each of the wire pads The inner circuit layer is fanned out; and the semiconductor wafer has an active surface and an inactive surface, and the non-active surface is disposed on the crystallographic region, and the active surface of the semiconductor wafer has a plurality of electrode pads, and the plurality of wires are electrically connected Each of the wire pads and the electrode pads corresponding to the sexual connection.

According to the above package structure and the package substrate thereof, the substrate system includes at least one internal dielectric layer, an internal circuit layer disposed on the internal dielectric layer, and is disposed in the internal dielectric layer and electrically connected to the internal The conductive structure of the circuit layer is provided with an external dielectric layer on the inner dielectric layer and the inner circuit layer of the outermost layer of the substrate body.

According to the above, the conductive line segment does not pass through the crystallographic region of the substrate body, and a solder resist layer is not formed on the substrate body.

According to the above, the package structure may include forming a surface treatment layer on the wire pad and the conductive line segment, and the material forming the surface treatment layer may be electroplated nickel/gold, electroless nickel/gold, and nickel immersion. Gold (Electroiess Ni & Immersion Gold, ENIG), Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), or Electroless Palladium/Immersion Gold (EPIG).

In addition, the package structure may include a bonding material formed between the crystallizing region and the semiconductor wafer, a wire electrically connecting each of the bonding pads and the electrode pad, and a substrate, a wire pad, and The semiconductor wafer and the encapsulating material on the wires are used to protect the semiconductor wafer and the wires.

It can be seen that the package structure and the package substrate of the present invention have better flatness by the exposed surface of the external dielectric layer, so that the semiconductor wafer is placed on the crystallographic region to maintain a better level, not only It can be used to connect ultra-thin semiconductor wafers to avoid the lack of flatness, which leads to the lack of fragility of the ultra-thin semiconductor wafer, and can avoid the deviation of the position of the electrode pads of the semiconductor wafer, so as to facilitate the wire bonding operation. Moreover, the surface of the external dielectric layer of the substrate body has better flatness, and has better flatness to provide alignment, thereby facilitating stacking and improving the reliability of the stacked package.

Moreover, since the exposed surface of the external dielectric layer is only provided with a conductive line segment having a small occupied area, the spacing between the wire bonding pads is not limited to the wiring requirement, and the spacing between the wire bonding pads is advantageously reduced; In addition, since there is no solder mask on the surface of the substrate body, the package height can be reduced to achieve a thin package.

The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily appreciate other advantages and functions of the present invention from the disclosure herein.

Please refer to FIG. 2, which is a cross-sectional view of the package substrate of the present invention. The package substrate includes a substrate body 21, a plurality of wire pads 22, and a plurality of conductive blind holes 23.

The substrate body 21 includes at least one internal dielectric layer 210, an internal wiring layer 211 disposed on the internal dielectric layer 210, and is disposed in the internal dielectric layer 210 and electrically connected to the internal wiring layer 210. The conductive structure 212 is a conductive via or an internal conductive via, and an external dielectric layer 213 is disposed on the inner dielectric layer 210 and the inner wiring layer 211 of the outermost layer of the substrate body 21, A solder resist layer is not formed on the outer dielectric layer 213, and at least one crystal region 214 is defined on the exposed surface of the outer dielectric layer 213; in short, the substrate body 21 is a multi-layer structure, and the outermost layer is The outer dielectric layer 213, while the other layers are the inner dielectric layer 210.

The wire bonding pad 22 is formed on the exposed surface of the external dielectric layer 213 and surrounds the crystallizing region 214, and each of the bonding pads 22 has a conductive segment 220, and the conductive segment 220 does not pass through the crystal region. a surface treatment layer 24 is formed on the wire pad 22 and the conductive wire segment 220, and the material forming the surface treatment layer 24 is electroplated nickel/gold, electroless nickel/gold, and nickel immersion gold (Electroless Ni & Immersion Gold, ENIG), Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), or Electroless Palladium/Immersion Gold (EPIG).

Referring to FIGS. 3A and 3B , the conductive segment 220 has a first end 220 a and a second end 220 b adjacent to the first end 220 a , and the first end 220 a is electrically connected to the wire pad 22 .

The conductive blind holes 23 are disposed in the external dielectric layer 213 and electrically connected to the second end 220b of each of the conductive segments 220 and the internal circuit layer 211, respectively, for each of the wire pads 22 The internal circuit layer 211 is fanned out.

Compared with the prior art, the outermost layer of the substrate body 21 of the present invention is an external dielectric layer 213, and the thickness of the external dielectric layer 213 is generally greater than the thickness of the solder resist layer, so that the thickness of the external dielectric layer 213 is The uniformity of the exposed surface of the external dielectric layer 213 is better, and the planarization region 214 is preferably flattened to avoid chipping of the semiconductor wafer 25.

As described above, as shown in FIGS. 3A and 3B, the package substrate is connected to the semiconductor wafer 25 to form a package structure; the package structure is attached to the crystal region 214 to bond the semiconductor wafer 25 with the bonding material 26, and The semiconductor wafer 25 has an active surface 25a and an inactive surface 25b, and the non-active surface 25b is disposed on the crystallizing region 214, and the active surface 25a of the semiconductor wafer 25 has a plurality of electrode pads 251, and is, for example, a gold wire. The wire 27 is electrically connected to each of the wire pad 22 and the electrode pad 251.

Referring to FIG. 4 , the package structure comprises a package material 28 formed on the substrate body 21 , the wire bonding pad 22 , the semiconductor wafer 25 and the wires 27 to protect the wire bonding pad 22 , the semiconductor wafer 25 and the wires 27 .

In summary, the package structure of the present invention and the package substrate thereof are mainly formed by the external surface of the external dielectric layer 213 of the substrate body 21 having a good flatness, and the wire pads 22 are formed on the external dielectric layer. The semiconductor layer 25 is mounted on the crystallization region 214. When the semiconductor wafer 25 is placed on the crystallization region 214, the semiconductor wafer 25 can be maintained at a better level due to the better flatness of the surface of the crystallization region 214. And can be used to connect the ultra-thin semiconductor wafer 25, so as to avoid the lack of thickness of the solder mask due to uneven thickness of the solder resist layer and poor surface flatness, and can effectively overcome the fragmentation of the semiconductor wafer 25. Missing. Moreover, the present invention can avoid the deviation of the position of the electrode pad 251, so as to reduce the lack of the positional deviation of the subsequent wire bonding operation.

In addition, most of the conductive blind vias 23 of the present invention are adjacent to the bonding pads 22 such that the bonding pads 22 are fanned out on the internal dielectric layer 210 by the conductive vias 23, that is, the internal dielectric layer 210. The inner circuit layer 211 is covered on the exposed surface of the outer dielectric layer 213, so that the conductive line segments 220 having a small footprint are provided on the exposed surface of the outer dielectric layer 213, so that the spacing between the wire bonding pads 22 is not limited to the wiring requirement, so as to facilitate The spacing between the wire pads 22 is reduced, and the fine pitch is effectively achieved.

Moreover, since the surface of the substrate body 21 has no solder resist layer, the package height can be reduced, and a plurality of ultra-thin wafers can be stacked to achieve a thin package.

The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the claims described below.

11,21. . . Substrate body

110. . . Dielectric layer

12. . . Circuit layer

120,23. . . Conductive blind hole

121,22. . . Line mat

122,24. . . Surface treatment layer

13. . . Solder mask

130. . . Opening

131,214. . . Crystal zone

14,25. . . Semiconductor wafer

141,251. . . Electrode pad

14a, 25a. . . Action surface

14b, 25b. . . Non-active surface

15,26. . . Bonding material

16,27. . . wire

210. . . Internal dielectric layer

211. . . Internal circuit layer

213. . . External dielectric layer

212. . . Conductive structure

220. . . Conductive line segment

220a. . . First end

220b. . . Second end

28. . . Packaging material

1A and 1B are schematic cross-sectional views and a schematic top view of a conventional package structure;

2 is a partial cross-sectional view showing a package substrate of the present invention;

3A and 3B are partial cross-sectional schematic views and a top schematic view of the package structure of the present invention;

Figure 4 is a cross-sectional view showing the package structure of the present invention.

twenty one. . . Substrate body

210. . . Internal dielectric layer

211. . . Internal circuit layer

212. . . Conductive structure

213. . . External dielectric layer

214. . . Crystal zone

twenty two. . . Line mat

220. . . Conductive line segment

twenty three. . . Conductive blind hole

twenty four. . . Surface treatment layer

Claims (10)

A package substrate includes: a substrate body having an external dielectric layer on a surface thereof, and having at least one internal wiring layer, and defining at least one crystal region on the exposed surface of the external dielectric layer, and the external portion A solder mask is not disposed on the exposed surface of the dielectric layer; a plurality of wire pads are formed on the exposed surface of the external dielectric layer and surround the crystallographic region, and each of the wire pads has conductive segments, each of which is electrically conductive The line segment has a first end and a second end, and the first end is electrically connected to the wire bonding pad; and the plurality of conductive blind holes are disposed in the external dielectric layer and respectively corresponding to the electrical connection of each of the conductive segments The two ends and the inner circuit layer are arranged such that each of the wire mats is fanned out by the inner circuit layer. The package substrate of claim 1, wherein the substrate comprises at least one internal dielectric layer, an internal wiring layer disposed on the internal dielectric layer, and is disposed in the internal dielectric layer and electrically The conductive structure of the inner circuit layer is connected, and an external dielectric layer is disposed on the inner dielectric layer and the inner circuit layer of the outermost layer of the substrate body. The package substrate of claim 1 is further comprising a surface treatment layer formed on the wire bonding pads and the conductive line segments. The package substrate of claim 1, wherein the conductive segment does not pass through the crystallographic region. A package structure includes: a substrate body having an external dielectric layer on a surface thereof, and having Having less than one internal wiring layer, and defining at least one crystallizing region on the exposed surface of the external dielectric layer, and the external dielectric layer is not provided with a solder resist layer on the exposed surface; the plurality of wire bonding pads are formed on The first dielectric layer has a first end and a second end, and the first end is electrically connected to the wire pad; a plurality of conductive vias are disposed in the external dielectric layer and electrically connected to the second end of each of the conductive segments and the internal circuit layer, respectively, for each of the wire pads to be fanned out by the internal circuit layer; The semiconductor wafer has an active surface and a non-active surface, and the non-active surface is disposed on the crystallographic region, and the active surface of the semiconductor wafer has a plurality of electrode pads, and the plurality of wires are electrically connected to the corresponding wire pads. And electrode pads. The package structure of claim 5, wherein the substrate comprises at least one internal dielectric layer, an internal wiring layer disposed on the internal dielectric layer, and is disposed in the internal dielectric layer and electrically The conductive structure of the inner circuit layer is connected, and an external dielectric layer is disposed on the inner dielectric layer and the inner circuit layer of the outermost layer of the substrate body. The package structure of claim 5, wherein the bonding material is formed between the crystallographic region and the semiconductor wafer. The package structure of claim 5, comprising a package material, is formed on the substrate body, the wire pad, the semiconductor wafer and the wire. Such as the package structure of claim 5, including surface treatment The layer is formed on the wire pads and the conductive segments. The package structure of claim 5, wherein the conductive segment does not pass through the crystallographic region.