TWI394252B - Package substrate structure - Google Patents

Description

Package substrate structure

The present invention relates to a semiconductor device, and more particularly to a package substrate structure that facilitates bonding semiconductor wafers.

At present, semiconductor packaging technology includes two types of semiconductor packaging technologies, a wire bonding type and a flip chip type, wherein the flip chip package is connected to a semiconductor chip on a package substrate having an electrical contact pad on a surface thereof. And the semiconductor wafer has a plurality of electrode pads electrically connected to the electrical contact pads by solder bumps, and a primer is formed between the semiconductor wafer and the package substrate to strengthen the bonded semiconductor wafer and the package substrate; The package substrate is divided into two types: a Solder Mask Defined (SMD) and a Non-Solder Mask Defined (NSMD).

Please refer to FIG. 1A , which is a package substrate defined by a conventional insulating protective layer. The circuit board 100 is provided with a circuit layer 100 , and the circuit layer 100 has a plurality of electrical contact pads 101 , and is disposed on the substrate body 10 . a solder mask 11a covering the circuit layer 100 and the electrical contact pad 101, and the solder resist layer 11a has a plurality of openings 110a to correspondingly expose portions of the surface of each of the electrical contact pads 101. Conductive bumps 12 are disposed on the exposed electrical contact pads 101.

The circuit layer 100 on the package substrate defined by the insulating protective layer has fine pitch characteristics to form a semiconductor device having a small volume, but the opening 110a of the solder resist layer 11a is too small, and has solder bumps 130 externally. In the case of the semiconductor wafer 13, the conductive bumps 12 need to be added to the surface of the electrical contact pad 101 to facilitate the alignment, which not only increases the manufacturing cost, but also causes the unevenness of the position of the conductive bumps 12 during the fabrication, which affects the connection. The reliability of the semiconductor wafer 13 is set. Therefore, in order to reduce the cost and improve the reliability of the semiconductor wafer 13 to be mounted, a package substrate defined by a non-insulating protective layer has been developed.

Referring to FIG. 1B , a package substrate defined by a conventional non-insulating protective layer is provided with a circuit layer 100 on the substrate body 10 , and the circuit layer 100 has a plurality of electrical contact pads 101 on the substrate body 10 . A solder resist layer 11b is provided. The solder resist layer 11b has a plurality of openings 110b corresponding to the respective electrical contact pads 101, and completely exposes the upper surface and the side surface of the electrical contact pad 101; the non-insulating protective layer defines The package substrate is enlarged in size by the opening 110b of the solder resist layer 11b to completely expose the electrical contact pad 101, so that the solder bumps 130 of the semiconductor wafer 13 are aligned and bonded to the electrical contact pads 101.

However, the solder resist layer 11b is disposed between the electrical contact pads 101 on the package substrate defined by the non-insulating protective layer, which is disadvantageous for the fine pitch design; in addition, the thickness of the solder resist layer 11b is difficult to control during the process. The height of the solder resist layer 11b is uneven, and the thickness of the solder resist layer 11b is higher than the height of the electrical contact pad 101. When the semiconductor wafer 13 and the electrical contact pad 101 are multi-point bonded, the semiconductor is disadvantageous. The wafer 13 is bonded and tends to be in a non-horizontal state, which affects the electrical connection.

Moreover, when the semiconductor wafer 13 is combined with the electrical contact pad 101, the solder is made because the thickness of the solder resist layer 11b is greater than the height of the electrical contact pad 101. The bumps 130 need to be filled into the openings 110b to be electrically connected to the electrical contact pads 101, thereby causing the semiconductor wafers 13 and the substrate body 10 to have a small pitch, thereby causing the primer to be less likely to be filled in the semiconductor wafer 13 and the package substrate. Between, and easy to create a void phenomenon.

Therefore, how to avoid the problems of poor bonding of semiconductor wafers, poor electrical effects, and disadvantages to fine pitch in the prior art has become a problem that is currently being solved.

In view of the above-described deficiencies of the prior art, it is an object of the present invention to provide a package substrate structure that improves the reliability of bonding to a semiconductor wafer.

Another object of the present invention is to provide a package substrate structure that facilitates the fabrication of fine pitches in a circuit.

To achieve the above and other objects, the present invention provides a package substrate structure, comprising: a substrate body having a dielectric layer disposed on at least one surface thereof, wherein the dielectric layer is provided with a circuit layer and a crystallizing region, The circuit layer has a plurality of lines and electrical contact pads, and each of the electrical contact pads is located in the crystallizing area, and is partially electrically connected to the line; and the solder resist layer is disposed on the dielectric layer and covers the crystallized area The outer circuit has an opening corresponding to the crystallizing area to expose the electrical contact pads, and the height of the electrical contact pad is higher than the height of the line and the thickness of the solder resist layer.

According to the above package substrate structure, the substrate system can be a circuit board having an inner layer line, and some electrical contact pads not electrically connected to the line can be connected to the inner layer line; and the height of the line can be Below the thickness of the solder mask, and the line is located between each of the electrical contact pads.

The package substrate structure may include a semiconductor wafer electrically connected to each of the electrical contact pads to be disposed on the crystallized region, and the semiconductor wafer has an active surface, the active surface having a plurality of electrode pads on each of the electrode pads A solder bump is disposed to electrically connect the solder bump to each of the electrical contact pads, and a primer is disposed between the crystallographic region and the semiconductor wafer.

In addition, in an embodiment, a surface treatment layer may be disposed on the upper surface and/or the side surface or the partial side surface of the electrical contact pad; or a surface treatment layer may be disposed on the upper surface and the side surface of the circuit. The surface treatment layer may be composed of one of a group of tin (Sn), lead (Pb), silver (Ag), nickel (Ni), palladium (Pd) or gold (Au), or may be Organic soldering flux (OSP).

In summary, the package substrate structure of the present invention forms an opening by the solder resist layer, exposes the electrical contact pads in the crystal region, and covers the lines outside the crystal region, so that there is no protection between the electrical contact pads. The solder layer is separated, and compared with the prior art, when the circuit layer is fabricated, the problem that the solder resist layer in the crystallizing area occupies space is avoided, which can facilitate the fine pitch of the line. In addition, by the height of the electrical contact pad being higher than the thickness of the solder resist layer, the semiconductor wafer can be electrically connected to the electrical contact pad without being affected by the solder resist layer, so that the semiconductor wafer can be accurately electrically connected. The electrical contact pad is connected to achieve the purpose of improving the bonding reliability.

Moreover, the height of the electrical contact pad is higher than the thickness of the solder resist layer. When the primer is filled between the semiconductor wafer and the package substrate, the primer can completely fill the space between the two without creating a gap. Avoiding the high heat generated by the semiconductor wafer during operation causes the gas in the gap to expand, causing the package structure to burst.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

Referring to FIGS. 2A and 2B , the present invention provides a package substrate structure including a substrate body 20 and a solder resist layer 21 . In the embodiment, the substrate body 20 is a circuit board having an inner layer line, but Regarding the wide variety of circuit boards, and well known in the industry, the substrate body 20 is only symbolically drawn, and is not intended to limit its form, and the inner layer circuit is not a technical feature of the present invention. Therefore, the inside of the substrate body 20 is not shown. Bright.

A dielectric layer 202 is disposed on at least one surface 20a of the substrate body 20, and the dielectric layer 202 is provided with a circuit layer 200 and a crystallizing region 201. The circuit layer 200 has a plurality of lines 200b and a plurality of electrical contacts. The pad 200a, and the electrical contact pad 200a is located in the crystallizing area 201, and the partial line 200b is located between each of the electrical contact pads 200a in the crystallizing area 201, and is electrically connected to the electrical contact pad 200a. The electrical contact pads 200a are electrically connected to the inner layer of the substrate body 20 via the line 200b. In addition, a portion of the electrical contact pad 200a' that is not electrically connected to the line 200b can be directly electrically connected to the inner layer line; and the height d of the line 200b is smaller than the height h of the electrical contact pads 200a, 200a'. When the electrical contact pads 200a, 200a' are externally connected to other components, damage to the line 200b can be avoided.

The solder resist layer 21 is disposed on the dielectric layer 202 of the substrate body 20 and covers the line 200b outside the crystallographic region 201, and has an opening 210 corresponding to the crystallizing region 201 to expose the electrical properties. Contact pad 200a, 200a', and the height h of each of the electrical contact pads 200a, 200a' is higher than the thickness s of the solder resist layer 21, so that the electrical contact pads 200a, 200a' are electrically connected to other components; Preferably, the height d of the line 200b is smaller than the thickness s of the solder resist layer 21.

The opening 210 of the solder resist layer 21 is sufficient to expose all of the electrical contact pads 200a, 200a' so that there is no solder resist layer 21 between the electrical contact pads 200a, 200a' for the circuit layer 200 to be formed. There is no need to consider the space occupied by the solder resist layer 21, which can facilitate the fine pitch design of the circuit layer 200.

Referring to FIGS. 3A to 3D, the package substrate structure further includes a surface treatment layer 22 selected from the group consisting of tin (Sn), lead (Pb), silver (Ag), nickel (Ni), and palladium (Pd). Or one of the groups of gold (Au) groups. For example tin/lead (Sn/Pb), tin/silver (Sn/Ag), nickel/silver (Ni/Ag), nickel/palladium/gold (Ni/Pd/Au), silver (Ag) or gold (Au) . In addition, the surface treatment layer 22 may also be an organic solder resist (OSP), which is not particularly limited. The surface treatment layer 22 is disposed on the upper surface and the side surface of the electrical contact pads 200a, 200a', and the surface treatment The layer 22 is not disposed on the line 200b, as shown in FIG. 3A; or the surface treatment layer 22 is disposed on the upper surface and the side surface of the line 200b, the upper surface and the side surface of the electrical contact pads 200a, 200a', As shown in FIG. 3B; or the surface treatment layer 22 is provided on the upper surface and the partial side surface of the electrical contact pads 200a, 200a', as shown in FIG. 3C; or the surface treatment layer 22 is provided on the electrical layer. The top surface of the contact pads 200a, 200a' is shown in Figure 3D.

The surface treatment layer 22 is disposed on the electrical contact pads 200a, 200a' to protect the electrical contact pads 200a, 200a' by the surface treatment layer 22. It is not damaged during the process, or the electrical contact pads 200a, 200a' are not contaminated by the external environment, so that the electrical contact pads 200a, 200a' can be electrically connected to other electronic components to maintain a good electrical connection effect.

Referring to FIG. 4, the semiconductor wafer 23 is disposed on the crystallizing region 201. The semiconductor wafer 23 has an active surface 23a. The active surface 23a is provided with a plurality of electrode pads. 231, and the solder bumps 25 are disposed on the electrode pads 231, and the solder bumps 25 are electrically connected to the electrical contact pads 200a, 200a', and formed between the substrate body 20 and the semiconductor wafer 23. With a primer 24, it becomes a complete package structure.

In addition, the surface of the electrical contact pads 200a, 200a' of the substrate body 20 may not form the surface treatment layer 22 at all, and the semiconductor wafers 23 are electrically connected to complete a package structure.

The height h of the electrical contact pads 200a, 200a' of the present invention is greater than the thickness s of the solder resist layer 21, so that the solder bumps 25 are not affected by the solder resist layer 21 when they are connected to the electrical contact pads 200a, 200a'. In order to facilitate the accurate alignment of the electrode pads 231 and electrically connect the electrical contact pads 200a, 200a'; and the height h of the electrical contact pads 200a, 200a' is greater than the thickness s of the solder resist layer 21, so that the semiconductor wafer The distance between the substrate 23 and the substrate body 20 is increased so that the primer 24 is filled between the semiconductor wafer 23 and the substrate body 20 without generating voids.

Further, the height d of the line 200b is smaller than the height h of the electrical contact pads 200a, 200a' and the thickness s of the solder resist layer 21 to prevent the semiconductor wafer 23 from touching the line 200b and avoiding damage to the wiring layer 200.

In summary, the package substrate structure of the present invention forms an opening for exposing all the electrical contact pads on the substrate body, so that there is no solder mask barrier between the electrical contact pads, so as to facilitate the fine pitch of the circuit. And the height of the electrical contact pad is greater than the thickness of the solder resist layer, so that the semiconductor wafer is electrically connected to the electrical contact pad accurately, so as to improve the reliability of the bonding and the package formed by combining the semiconductor wafer and the package substrate. Product quality.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

10, 20‧‧‧ substrate body

100, 200‧‧‧ circuit layer

101, 200a‧‧‧Electrical contact pads

11a, 11b, 21‧‧‧ solder mask

110a, 110b‧‧‧ openings

12‧‧‧Electrical bumps

13, 23‧‧‧ semiconductor wafer

130, 25‧‧‧ solder bumps

200b‧‧‧ lines

201‧‧‧Setting area

20a‧‧‧ surface

210‧‧‧ openings

22‧‧‧Surface treatment layer

23a‧‧‧Action surface

231‧‧‧electrode pads

24‧‧‧Bottom

d, h‧‧‧ height

S‧‧‧thickness

1A and 1B are schematic cross-sectional views of a conventional package substrate; FIG. 2A is a schematic cross-sectional view of the package substrate structure of the present invention; FIG. 2B is a top view of the package substrate structure of the present invention; FIGS. 3A to 3D A schematic cross-sectional view of a package substrate structure of the present invention; and FIG. 4 is a cross-sectional view of the package substrate structure of the present invention in combination with a semiconductor wafer.

20‧‧‧Substrate body

20a‧‧‧ surface

200‧‧‧circuit layer

200a‧‧‧Electrical contact pads

200b‧‧‧ lines

201‧‧‧Setting area

202‧‧‧ dielectric layer

21‧‧‧ solder mask

210‧‧‧ openings

d, h‧‧‧ height

S‧‧‧thickness

Claims (14)

A package substrate structure includes: a substrate body having a dielectric layer on at least one surface, and a dielectric layer and a crystallizing region disposed on the dielectric layer, the circuit layer having a plurality of lines and a plurality of electrical contact pads And the electrical contact pads are located in the crystallizing region, and are partially electrically connected to the circuit; and the solder resist layer is disposed on the dielectric layer of the substrate body and covers the circuit outside the crystallographic region And having openings corresponding to the crystallographic regions, the electrical contact pads are exposed, and the height of each of the electrical contact pads is higher than the height of each of the lines and the thickness of the solder resist layer. The package substrate structure of claim 1, wherein the substrate system is a circuit board having an inner layer. The package substrate structure of claim 2, wherein the electrical contact pads of the electrical contact pads are electrically connected to the inner layer line. The package substrate structure of claim 1, wherein the height of the line is lower than the thickness of the solder resist layer. The package substrate structure of claim 1 further comprises a semiconductor wafer electrically connected to each of the electrical contact pads to provide the semiconductor wafer on the crystallographic region. The package substrate structure of claim 5, wherein the semiconductor wafer has an active surface, and the active surface has a plurality of electrode pads, and each of the electrode pads is provided with a solder bump to electrically connect the solder bump to Each of the electrical contact pads. The package substrate structure of claim 5, comprising a primer, disposed between the crystallographic region of the substrate body and the semiconductor wafer. The package substrate structure of claim 1, wherein the line is located between each of the electrical contact pads. The package substrate structure of claim 1 further comprises a surface treatment layer disposed on an upper surface and a side surface of the electrical contact pad. The package substrate structure of claim 1 is further comprising a surface treatment layer disposed on an upper surface and a side surface of the line. The package substrate structure of claim 1 , further comprising a surface treatment layer disposed on the upper surface and the partial side surface of the electrical contact pad. The package substrate structure of claim 1 is further comprising a surface treatment layer disposed on an upper surface of the electrical contact pad. The package substrate structure of claim 9, 10, 11 or 12, wherein the surface treatment layer is selected from the group consisting of tin (Sn), lead (Pb), silver (Ag), nickel (Ni), and palladium (Pd). Or one of the groups of gold (Au) groups. The package substrate structure of claim 9, 10, 11 or 12, wherein the surface treatment layer is an organic solder resist (OSP).