TWI478173B - Row decoding circuit - Google Patents

Description

Column decoding circuit

The present invention relates to a memory device, and more particularly to a column decoding circuit for a memory device.

The memory array in the memory device is composed of a plurality of memory cells. When a plurality of materials are to be stored in the memory array or read from the memory array, the memory device enables the corresponding column selection signal according to the memory address corresponding to each data to enable the corresponding character. The memory cells on the line can store the data into the corresponding memory cells or read the data from the corresponding memory cells. Therefore, in the application of the memory technology, a plurality of column decoders are used to generate a plurality of column selection signals, and the column decoder determines the voltage level of the column selection signals according to the memory address.

In general, a column decoder is usually constructed by using a plurality of cascode transistors, and the sub-Threshold Leakage of the transistor, the Gate Direct Tunneling Leakage, and the gate. The Gate Induce Drain Leakage (GIDL) affects the power consumption of the column decoder. Therefore, how to reduce the leakage current of the transistor becomes an important issue in the design of the column decoder of the memory device.

The invention provides a column decoding circuit which can increase the circuit area without increasing Under the condition, the leakage current phenomenon of the column decoder is effectively suppressed.

The present invention proposes a column decoding circuit that is suitable for use in a memory device and that includes a plurality of column decoding blocks. These column decoding blocks each include a plurality of column decoders. The column decoders respectively receive corresponding pre-charge signals, and each column decoder includes an inverter, a selection transistor, and at least one switching transistor. The inverter receives the corresponding precharge signal and outputs a first control signal. The first source/drain of the transistor is selected to couple the system high voltage. The gate of the selected transistor receives the first control signal and selects the column select signal corresponding to the second source/drain output of the transistor to the memory array of the memory device. The switching transistors are coupled in series with each other between the second source/drain of the selection transistor and the corresponding first reference signal, and the gates of the switching transistors respectively receive the corresponding second control signals. Wherein, when the selected transistor is controlled to be turned on by the first control signal, the first reference signal is set to a high level.

Based on the above, the embodiment of the present invention provides a column decoding circuit, which provides a high-level first reference signal when the column decoder outputs a high-level column selection signal, thereby suppressing the sub-critical leakage current of the switching transistor, thereby reducing The effect of leakage current on the voltage level of the column select signal and the power consumption of the memory device.

The above described features and advantages of the present invention will be more apparent from the following description.

1 is a schematic diagram of a column decoding circuit in accordance with an embodiment of the present invention. In this embodiment, the column decoding circuit 100 can be applied to various memory devices. For example, a dynamic random access memory or a static random access memory or the like is used to decode a memory address to generate a plurality of column selection signals (such as s_rsel11~s_rsel1n) to drive the memory array of the memory device.

Referring to FIG. 1, in the embodiment, the column decoding circuit 100 includes a plurality of column decoding blocks 110_1 110 110_m, a plurality of address setting units 120_1 120 120_m, and a plurality of block decoders 130_1 130 130_m. The block decoders 130_1~130_m respectively generate block selection signals s_blk1~s_blkm corresponding to the respective column decoding blocks 110_1~110_m according to the first part AP1 of the memory address AP. The address setting units 120_1~120_m respectively receive the corresponding block selection signals s_blk1~s_blkm and the second part AP2 of the memory address AP and correspondingly generate a plurality of address reference signals s_rd11~s_rd1q, s_rd21~s_rd2q, ..., S_rdm1~s_rdmq and a plurality of precharge signals s_prch1~s_prchm.

Here, the first part AP1 and the second part AP2 of the memory address AP may be the memory address AP of the high-order part and the memory address AP of the low-order part, for example, when the memory address AP is composed of multiple memory addresses. When the bit element (for example, A0~Ak) is formed, the first part AP1 (higher bit part) can be composed of the memory address bits A6~Ak, and the second part AP2 (lower bit part) can be composed of the memory address bit A0~ A5 is constructed, where k is a positive integer. In addition, the m and n values may be determined according to the memory array size and circuit design of the memory device.

The column decoding blocks 110_1~110_m respectively include a plurality of column decoders (such as 112_1~112_n) and a plurality of control signal generating units (such as 114_1~114_n). In this embodiment, each column decoding block The architectures of 110_1~110_m are substantially the same, so the description will be made here by the column decoding block 110_1. The column decoding block 110_1 includes column decoders 112_1 to 112_n and control signal generating units 114_1 to 114_n. Each control signal generating unit (such as 114_1~114_n) is respectively coupled to a corresponding address setting unit (such as 120_1~120_m) to receive a corresponding address reference signal (such as s_rd11~s_rd1q, s_rd21~s_rd2q, s_rdm1~) S_rdmq) outputs a plurality of second control signals (such as s_c2), wherein the value of q can be determined according to the circuit design of the column decoder (such as 112_1~112_n). Therefore, each column decoder (such as 112_1~112_n) can generate a corresponding column selection signal (such as s_rsel11~s_rsel1n) according to the corresponding pre-charge signal (such as s_prch1~s_prchm) and the corresponding second control signal (such as s_c2).

2 is a schematic diagram of a column decoder in accordance with an embodiment of FIG. 1. The circuit structures of the column decoders 112_1~112_n are substantially the same, and the column decoder 112_1 is taken as an example here. Referring to FIG. 1 and FIG. 2 simultaneously, in the embodiment, the column decoder 112_1 includes an inverter INV, a selection transistor Ms, and three switching transistors (such as M1~M3), wherein the selection transistor Ms is, for example, P. The type of transistor, the switching transistors M1 to M3 are, for example, N-type transistors. In addition, the number of the switching transistors (such as M1 to M3) may be changed to one or more according to the requirements of the circuit design, but the embodiment of the present invention is not limited thereto.

The inverter INV receives the corresponding precharge signal s_prch1 and outputs a first control signal s_c1. Selecting the first source/drain of the transistor Ms to couple the system high voltage VPP, selecting the gate of the transistor Ms to receive the first control signal s_c1, and selecting the column corresponding to the second source/drain output of the transistor Ms Select the signal r_sel11. The switching transistors M1 M M3 are coupled in series with each other between the second source/drain of the selection transistor Ms and the corresponding first reference signal s_ref1, and the gates of the respective switching transistors M1 M M3 are respectively controlled by the control signal generating unit 114_1 receives the corresponding second control signals s_c21~s_c23. The second source/drain of the switching transistor M3 receives the corresponding first reference signal s_ref1.

It should be noted that the present invention does not limit the type of the selected transistor Ms and the switching transistors M1 to M3. In other embodiments, the selection transistor Ms and the switching transistors M1 to M3 may also pass through the same type of transistor or different. Type transistor to achieve. In addition, the circuit architecture of the column decoder 112_1 illustrated in FIG. 2 is merely an example. In a practical application, each of the column decoders 112_1~112_n may share the same inverter INV to receive the first control signal s_sc1. In other words, the present invention does not limit each of the column decoders 112_1~112_n to include the inverter INV.

Specifically, the column decoding circuit 100 selects the column decoding blocks 110_1 110 110_m according to the first portion AP1 of the memory address AP, and further enables the selected column decoding block 110_1 according to the second portion AP2 of the memory address AP. One of a plurality of column selection signals (such as s_rsel11~s_rsel1n) generated by a column decoder of ~110_m (such as 112_1~112_n). In this embodiment, the enabled column select signal (such as s_rsel11~s_rsel1n) is, for example, a low level, and the disabled column select signal (such as s_rsel11~s_rsel1n) is, for example, a high level.

3A-3D are signal timing diagrams of a column decoder in accordance with an embodiment of the present invention. Please refer to FIG. 1 , FIG. 2 and FIG. 3A simultaneously, and FIG. 3A shows the column solution. An embodiment of the voltage level of each signal of the condition that the column decoding block 110_1 corresponding to the decoder 112_1 is not selected. When the column decoding block 110_1 is not selected, the block decoder 130_1 outputs the low level block selection signal s_blk1 to the address setting unit 120_1 according to the first portion AP1 of the memory address AP. At this time, the address setting unit 120_1 outputs the high-level address reference signals s_rd11~s_rd1q to the control signal generating units 114_1~114_n and outputs the high-level pre-charge signal s_prch1 (ie, the disabled pre-charge signal s_prch1) to the column. The decoders 112_1~112_n, and the control signal generating units 114_1~114_n generate high level second control signals s_c21~s_c23 according to the corresponding high level address reference signals s_rd11~s_rd1q.

In an embodiment of the present invention, the first reference signal s_ref1 may be generated by the block decoder 130_1 or the address setting unit 120_1, and set to a high level according to the high-order block selection signal s_blk1. The high level and the low level of the first reference signal s_ref1 may respectively correspond to the transistor turn-on voltage VTT and the ground voltage GND, and the high level and the low level of the pre-charge signal s_prch1 may correspond to the system high voltage VPP and the ground voltage GND, respectively. The high level and the low level of the second control signals s_c21 to s_c23 may correspond to the transistor turn-on voltage VTT and the ground voltage GND, respectively. The transistor turn-on voltage VTT is lower than the system high voltage VPP and higher than the threshold voltage of the switching transistor (eg, M1~M3).

At this time, the inverter INV receives the high-level precharge signal s_prch1 and outputs the first control signal s_c1 having the low level to the gate of the selection transistor Ms to turn on the selection transistor Ms. And, due to the switching transistor M3 The first reference signal s_ref1 received by the second source/drain is set to a high level, and the received second control signals s_c21~s_c23 of the switching transistors M1 M M3 are at a high level, so the switching transistors M1~M3 Will be closed. Therefore, the column selection signal s_rsel11 will be at a high level (ie, system high voltage VPP).

In other words, when the respective column decoders 112_1~112_n are not selected according to the first portion AP1 of the memory address AP in the corresponding column decoding block 110_1, the pre-charge signals s_prch1 corresponding to the respective column decoders 112_1~112_n correspond to The first reference signal s_ref1 and the corresponding second control signals s_c21~s_c23 will be at a high level, and the selection transistor Ms is turned on by the first control signal s_c1. At this time, the voltage difference between the first source/drain of the switching transistor M1 and the second source/drain of the switching transistor M3 is lowered, and the first source/drain of each of the switching transistors M1 to M3 is connected to the gate thereof. The voltage difference between the poles is reduced, thereby reducing leakage currents of the switching transistors M1 to M3, such as sub-critical leakage current, gate leakage current, and gate-induced drain leakage current.

FIG. 3B shows another embodiment of the voltage level of each signal of the state in which the column decoding block 110_1 corresponding to the column decoder 112_1 is not selected. In this embodiment, the difference from the foregoing embodiment of FIG. 3A is that the control signal generating unit 114_1 generates the second control signals s_c21~s_c23, which are all low level, if the column decoding block 110_1 is not selected, but In the case where the voltage difference between the first source/drain of the switching transistor M1 and the second source/drain of the switching transistor M3 is lowered, the leakage currents of the switching transistors M1 to M3 can still be improved.

Please refer to FIG. 1 , FIG. 2 and FIG. 3C simultaneously, wherein FIG. 3C shows the voltage level of each signal of the state in which the column decoding block 110_1 corresponding to the column decoder 112_1 is selected and the column decoder 112_1 is not selected. When the column decoding block 110_1 corresponding to the column decoder 112_1 is selected and the column decoder 112_1 is not selected, the block decoder 130_1 corresponding to the column decoding block 110_1 outputs a high level according to the first portion AP1 of the memory address AP. The quasi-block selection signal s_blk1 to the address setting unit 120_1.

At this time, the second portion AP2 of the output memory address AP corresponding to the address setting unit 120_1 to the corresponding control signal generating units 114_1~114_n serves as the address reference signals s_rd11~s_rd1q, and outputs the low-level pre-charge signal s_prch1 ( That is, the enabled pre-charge signal s_prch1) to the column decoding block 110_1.

The control signal generating unit 114_1 generates the second control signals s_c21~s_c23 according to the corresponding address reference signals s_rd11~s_rd1q, and the first reference signal s_ref1 is set to a low level according to the low-level pre-charge signal s_prch1. Since the column decoder 112_1 is not selected, the control signal generating unit 114_1 is controlled by at least one of the second control signals s_c21~s_c23 generated by the address reference signals s_rd11~s_rd1q to be a low level, where the second control signal is used. S_c23 is taken as an example, but the invention is not limited thereto.

When the inverter INV receives the low-level pre-charge signal s_prch1, it outputs a first control signal s_c1 having a high level to the gate of the selection transistor Ms to turn off the selection transistor Ms. At this time, the first reference signal s_ref1 received by the second source/drain of the switching transistor M3 corresponds to It is set to a low level, but since the control signal generating unit 114_1 generates at least one of the low-level second control signals s_c21 to s_c23 to turn off at least one of the switching transistors M1 M M3, the column decoder 112_1 The output column selection signal s_rsel11 will still be considered a high level.

On the other hand, if the column decoder 112_1 is selected, the column selection signal s_rsel11 outputted by it will be enabled (e.g., low level). Please refer to FIG. 1 , FIG. 2 and FIG. 3D simultaneously, wherein FIG. 3D shows the voltage level of each signal of the state in which the column decoding block 110_1 corresponding to the column decoder 112_1 is selected and the column decoder 112_1 is selected. When the column decoding block 110_1 is selected and the column decoder 112_1 is selected, the address setting unit 120_1 outputs the low level pre-charge signal s_prch1 to the column decoding block 110_1, and the control signal generating unit 114_1 according to the address reference signal S_rd11~s_rd1q generates second control signals s_c21~s_c23 which are all high level, and the first reference signal s_ref1 is set to a low level corresponding to the low level pre-charge signal s_prch1.

When the inverter INV receives the low-level pre-charge signal s_prch1, it outputs a first control signal s_c1 having a high level to the gate of the selection transistor Ms to turn off the selection transistor Ms. At this time, since the first reference signal s_ref1 is set to a low level, and the second control signals s_c21 to s_c23 are all at a high level, the switching transistors M1 to M3 are all turned on. Therefore, the voltage level of the column selection signal s_rsel1 is pulled down to the ground voltage GND (ie, the low level).

In addition, in this embodiment, the base of each of the switch transistors M1 M M3 can be coupled to the corresponding second source/drain or to the ground voltage GND. The base of the switching transistors M1 M M3 is coupled to the ground voltage GND to prevent the threshold voltage of each of the switching transistors M1 M M3 from being affected by the voltage level variation of the first reference signal s_ref1.

4 is a schematic diagram of a column decoder in accordance with another embodiment of the present invention. Referring to FIG. 4, in the embodiment, the column decoder 412 includes an inverter INV, a selection transistor Ms, and switching transistors M1 M M3, wherein the selection transistor Ms is a P-type transistor and the switching transistors M1 M M3 The structure and operation of the N-type transistor are substantially the same as those of the previous embodiment of FIG. 2. This embodiment differs from the foregoing embodiment of FIG. 2 in that the column decoder 412 is configured to receive the precharge signal s_prch1 by coupling the second source/drain of the switching transistor M3 to the input of the inverter INV. The voltage level of the first reference signal s_ref1 is set.

In other words, the first reference signal s_ref1 received by the column decoder 412 is the pre-charge signal s_prch1, so in the foregoing operation mode, the high level of the first reference signal s_ref1 corresponds to the system high voltage VPP.

Under this architecture, the voltage difference between the first source/drain of the switching transistor M1 and the second source/drain of the switching transistor M3 can further approach zero. Therefore, the problem of the sub-critical leakage current of each of the switching transistors M1 to M3 can be effectively suppressed under the circuit structure of the column decoder 512.

It should be noted that, in the case that the first reference signal s_ref is the pre-charge signal s_prch1, the high level of each of the second control signals s_c21 s s_c23 may correspond to the system high voltage VPP or the transistor turn-on voltage VTT. In addition, the signal timing and operation mode of the column decoder 412 can be referred to the description of FIG. 2 and FIG. 3A to FIG. 3D, and thus will not be further described herein.

In summary, the embodiment of the present invention provides a column decoding circuit that provides a high-level first reference signal when the column decoder outputs a high-level column selection signal, thereby suppressing a sub-critical leakage that may occur in the switching transistor. Current. In addition, the column decoding circuit of the embodiment of the present invention can also prevent the gate leakage current of each switching transistor and the gate leakage current caused by the gate by providing a high level of the second control signal to the switching transistor, thereby reducing The effect of leakage current on the voltage level of the column select signal and the power consumption of the memory device.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 500‧‧‧ column decoding circuit

110_1~110_m‧‧‧ column decoding block

112_1~112_n, 412, 512_1~512_n‧‧‧ column decoder

114_1~114_n‧‧‧Control signal generation unit

120_1~120_m‧‧‧ address setting unit

130_1~130_m‧‧‧block decoder

AG1, AG2‧‧‧ and gate

AP‧‧‧ memory address

AP1‧‧‧Part 1

AP2‧‧‧ Part II

A0‧‧‧ lowest bit

Bs_blk1‧‧‧ inverted signal

GND‧‧‧ Grounding voltage

Ms‧‧‧Selected crystal

M1, M2, M3‧‧‧ switch transistor

INV‧‧‧Inverter

H‧‧‧High voltage level

L‧‧‧Low voltage level

VPP‧‧‧ system high voltage

S_blk1~s_blkm‧‧‧block selection signal

S_c1‧‧‧First control signal

S_c21~s_c23‧‧‧second control signal

S_prch1~s_prchm‧‧‧Precharge signal

S_rd11~s_rd1q, s_rd21~s_rd2q,..., s_rdm1~s_rdmq‧‧ Address reference signal

S_ref1‧‧‧First reference signal

S_rsel11~s_rsel1n‧‧‧ column selection signal

1 is a schematic diagram of a column decoding circuit in accordance with an embodiment of the present invention.

2 is a schematic diagram of a column decoder in accordance with an embodiment of the present invention.

3A-3D are signal timing diagrams of a column decoder according to an embodiment of the present invention.

4 is a schematic diagram of a column decoder in accordance with another embodiment of the present invention.

112_1‧‧‧ column decoder

Ms‧‧‧Selected crystal

M1~M3‧‧‧Switching transistor

INV‧‧‧Inverter

VPP‧‧‧ system high voltage

S_c1‧‧‧First control signal

S_c21~s_c23‧‧‧second control signal

S_prch1‧‧‧Precharge signal

S_ref1‧‧‧First reference signal

S_rsel11‧‧‧ column selection signal

Claims (18)

A column decoding circuit is applicable to a memory device, comprising: a plurality of column decoding blocks, each comprising a plurality of column decoders, each of the column decoders comprising: a selection transistor, the first source of the selection transistor The /pole is coupled to a system high voltage, the gate of the selection transistor receives a first control signal, and the second source/drain output of the selection transistor outputs a column of selection signals to a memory of the memory device And a plurality of switching transistors, wherein the switching transistors are coupled in series between the second source/drain of the selective transistor and a corresponding first reference signal, and the gates of the switching transistors The poles respectively receive a corresponding second control signal; wherein, when the selection transistor is turned on by the first control signal, setting the first reference signal to a high level. The decoding circuit of claim 1, wherein each of the column decoding blocks further comprises: an inverter coupled to the column decoders in the corresponding column decoding block to receive a precharge Signaling and outputting the first control signal. The decoding circuit of claim 2, wherein the selection transistor is a P-type transistor, and the switching transistors are respectively an N-type transistor. The decoding circuit of claim 3, wherein each of the column decoders is not selected when a corresponding column decoding block is not selected according to a first portion of a memory address, each of the column decoders Corresponding to the pre The charging signal and the corresponding first reference signal are at a high level. The decoding circuit of claim 4, wherein when the column decoding blocks corresponding to the column decoders are selected, the pre-charging signals corresponding to the column decoders and the corresponding ones are The first reference signal is at a low level. The decoding circuit of claim 5, wherein the first reference signal corresponding to each of the column decoders is the pre-charge signal corresponding to each of the column decoders. The decoding circuit of claim 6, wherein the second control signals corresponding to the column decoders are not selected when the column decoding blocks corresponding to the column decoders are not selected. Low level. The decoding circuit of claim 6, wherein when the column decoding blocks corresponding to the column decoders are not selected, the second control signals corresponding to the column decoders are High level. The decoding circuit of claim 5, wherein a high level of the precharge signal corresponds to a high voltage of the system, a high level of the first reference signal corresponds to a transistor turn-on voltage, and the precharge signal A low level with the first reference signal corresponds to a ground voltage, wherein the transistor turn-on voltage is lower than the system high voltage and higher than a threshold voltage of the switching transistors. The decoding circuit of claim 9, wherein when the column decoding blocks corresponding to the column decoders are not selected, the second control signals corresponding to the column decoders are Low level. a decoding circuit as described in claim 9 of the patent application, wherein When the column decoding blocks corresponding to the column decoders are not selected, the second column control signals corresponding to the column decoders are at a high level. The decoding circuit of claim 5, wherein a column decoding block corresponding to each of the column decoders is selected and each of the column decoders is based on a second portion of the memory address. When selected, at least one of the second control signals corresponding to each of the column decoders is a low level. The decoding circuit of claim 12, wherein a column decoding block corresponding to each of the column decoders is selected and each of the column decoders is configured according to the second portion of the memory address. When selected, the second control signals corresponding to the column decoders are at a high level. The decoding circuit of claim 13, wherein the first part of the memory address is a high-order part of the memory address, and the second part of the memory address is one of the memory address Low bit part. The decoding circuit of claim 5, wherein each of the column decoding blocks further comprises a plurality of control signal generating units respectively coupled to corresponding column decoders, each of the plurality of control signal generating units receiving The address reference signal, and corresponding to the second control signals are output accordingly. The decoding circuit of claim 15 further includes a plurality of address setting units respectively receiving a corresponding block selection signal and a second portion of the memory address, and each of the column decoding regions When the block is selected, the address setting unit corresponding to each of the column decoding blocks is controlled by the corresponding block selection signal to output the second portion of the memory address to the corresponding The control signal generating unit is configured as the corresponding address reference signal and the output low-level pre-charge signal to the corresponding column decoding block. When each of the column decoding blocks is not selected, each of the column decoding blocks corresponds to The address setting unit controls the corresponding block selection signal to output the high level reference address reference signals to the corresponding control signal generating unit and output the high level pre-charge signal to the corresponding column decoding block. The decoding circuit of claim 16, further comprising a plurality of block decoders, receiving the first portion of the memory address and respectively outputting corresponding block selection signals, wherein the block decoders are The first portion of the memory address outputs the low level of the block selection signal to an address setting unit corresponding to the unselected column decoding block, and the block decoder outputs a high bit according to the first portion of the memory address The block selection signal is quasi-to the address setting unit corresponding to the selected column decoding block. The decoding circuit of claim 1, wherein the bases of the switch transistors of each of the column decoders are coupled to a ground voltage.