JP2010199301A - Nonvolatile semiconductor memory device - Google Patents

Abstract

In a NAND flash memory, the leakage component from the end of an active row decoder to the guard ring region is suppressed, the transfer capability of the transfer gate transistor at the inner end of the active row decoder is prevented from being lowered, and the chip yield is improved. To do.
In a NAND flash memory, transfer gate transistors 341 and 342 for transferring a voltage to a word line or a select gate line are formed in the vicinity of an end of a memory cell array 10 in a row direction and arranged in a matrix. Active row decoder 40, guard ring region 43 disposed between the active row decoder and the cell array, and dummy row decoder 44 formed between the guard ring region and the active row decoder. However, the source nodes of the dummy transfer gate transistors 461 and 462 formed in the dummy element region 45 of the dummy row decoder 44 are not connected to the word line WLi and the selection gate lines SGD and SGS.
[Selection] Figure 3

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a row decoder of a NAND flash memory.

  2. Description of the Related Art Conventionally, a NAND flash memory capable of increasing capacity and integration is known as a nonvolatile semiconductor memory capable of electrically rewriting data. In this NAND flash memory chip, a memory cell array includes a NAND memory cell (hereinafter referred to as a NAND cell) in which select gate transistors are connected to both ends of a plurality of memory cell transistors having a floating gate / control gate stacked gate structure. Are listed).

  In a conventional NAND flash memory chip, a plurality of active row decoders each having a transfer gate transistor formed in an element region are arranged in a row decoder disposed in the vicinity of the memory cell array. In this row decoder, an element isolation region having a trench structure (hereinafter referred to as an STI region) is formed between element regions, and an STI region and a guard ring region are formed at the row direction end of the row decoder. Yes. Patent Document 1 discloses that in a NAND flash memory, a transfer gate transistor region and a guard ring region are arranged in a row decoder.

  The transfer gate transistor transfers a high write voltage from the drain side to the source side to the control gate line connected to the control gate of the memory cell transistor when writing data to the NAND cell. When forming an STI region adjacent to the row decoder and an STI region between element regions in the row decoder, impurity ions are implanted to form a leak prevention layer below the bottom of the trench.

  However, the characteristics of the transfer gate transistor formed in the element region located at the end in the row direction in the conventional row decoder are different from those of the transfer gate transistors formed in other element regions in the row decoder. The phenomenon is seen. This is because the element region adjacent to the wide STI region is strongly influenced by the implantation of impurity ions into the STI region. As a result, the transfer gate transistor formed in the element region located at the end in the row direction in the row decoder has a guard ring fixed to the ground potential when transferring a write voltage for writing data to the NAND cell. There is a case where the transfer capability is deteriorated due to a leak component that escapes to the region side. In this case, it becomes difficult to transfer the write voltage without a voltage drop. As a result, there is a phenomenon that writing is delayed in the memory cell transistor to which the write voltage is supplied from the control gate line connected to the transfer gate transistor located at the row direction end in the row decoder. As a result, the yield of the chip is reduced, and the quality is deteriorated due to excessive stress applied to the transfer gate transistor that transfers a high write voltage.

JP 2008-234820 A

  The present invention has been made to solve the above-described conventional problems, and prevents the transfer gate transistor formed in the element region at the end in the row direction in the row decoder from deteriorating in transfer capability. An object of the present invention is to provide a nonvolatile semiconductor memory device that can suppress an excessive voltage stress and suppress a decrease in yield of a chip.

  The nonvolatile semiconductor memory device of the present invention includes a lower gate electrode and an inter-gate insulating film on at least one end side of a plurality of memory cell transistors having a stacked gate structure of floating gates and control gates on a semiconductor substrate via a gate insulating film. A memory cell array in which NAND cell cell arrays connected to select gate transistors having a stacked gate structure composed of an upper gate electrode are arranged in a matrix, and formed in the row direction on the memory cell array, and in the same row in the memory cell array The word lines commonly connected to the control gates of the cell transistors and the selection gate lines commonly connected to the upper gate electrodes of the selection gate transistors in the same row are formed in the vicinity of the row direction end of the memory cell array and arranged in a matrix The voltage is transferred to the word line or the selection gate line in the formed element region A plurality of first active row decoders each having a transfer gate transistor for forming the first active row decoder; a first guard ring region disposed between the first active row decoder and the memory cell array; A first dummy row decoder formed between the active row decoder and the first guard ring region, wherein the first dummy row decoder includes the first active row decoder in the dummy element region; It has a dummy transfer gate transistor formed in the same pattern as the transfer gate transistor of the decoder, and the source node of the dummy transfer gate transistor is not connected to the word line or the selection gate line.

  According to the nonvolatile semiconductor memory device of the present invention, it is possible to suppress the deterioration of the transfer capability of the transfer gate transistor of the active row decoder located at the row direction end of the row decoder and to apply an excessive voltage stress to the transfer gate transistor. It is possible to suppress and improve the yield of the chip.

1 is a plan view showing a pattern layout of a NAND flash memory chip according to a first embodiment of the present invention; FIG. 2 is a circuit diagram of a memory cell array and a row decoder in FIG. 1. FIG. 2 is a plan view showing a pattern layout in a row decoder in FIG. 1.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this description, common parts are denoted by common reference numerals throughout the drawings.

<First Embodiment>
FIG. 1 is a plan view showing a pattern layout of a NAND flash memory chip according to the first embodiment of the present invention. FIG. 2 is a circuit diagram of the memory cell array 10 and the row decoder 30 in FIG.

  In FIG. 1, 10 is a memory cell array in which a large number of memory cells are arranged, 20 is a sense amplifier, and 30 is a row decoder. Around the memory cell array 10, there are a source line driver 4 for applying a voltage to the source line of the memory cell array 10, a well driver 5 for applying a voltage to a well region where the memory cell array 10 is formed, and a voltage for generating a high voltage such as a write voltage. A generation circuit 6, a peripheral circuit 7, and the like are formed.

  The row decoder 30 is disposed on both sides so as to sandwich the memory cell array 10 in the vicinity of the memory cell array 10 in the row direction. As shown in FIG. 2, the memory cell array 10 has select gate transistors ST1 and ST2 connected to both ends of a memory cell transistor array in which a plurality of nonvolatile memory cell transistors MT (for example, 64) are connected in series. A plurality of NAND cells are arranged in a matrix. In each NAND cell 11, the number of memory cell transistors MT is not limited to 64, but 16, 32, 128, 256, etc., or 1 to 4 dummy cell transistors are added to these numbers. It may be a number, and the number is not limited. In addition, the row decoder 30 may be disposed only on one side of the memory cell array 10.

  In the following embodiment, a case where 64 memory cell transistors MT are connected in series will be described. However, a NAND cell in which 66 memory cell transistors including two dummy cell transistors are connected in series may be used. In this case, one memory cell transistor adjacent to the selection gate transistors at both ends of the NAND cell is used as the dummy cell transistors DWL1 and DWL2.

  The memory cell transistor MT has a stacked gate structure in which a control gate is formed and stacked on an inter-gate insulating film (hereinafter, IPD film) on a floating gate for charge storage. The select gate transistors ST1 and ST2 have a gate structure in which an upper gate electrode is formed on the lower gate electrode via an IPD film, and the lower gate electrode and the upper gate electrode are electrically connected. In each NAND cell 11, a plurality of memory cell transistors MT adjacent in the column direction share the source of one memory cell transistor and the drain of the other memory cell transistor, and one end side of the memory cell transistor column The drain region is connected to the source region of the first select gate transistor ST1, and the source region on the other end side of the memory cell transistor row is connected to the drain region of the second select gate transistor ST2.

  In the row direction on the memory cell array 10, word lines WLi (i = 0 to 63) connected to the control gates of the memory cell transistors MT, selection gate lines SGD and SGS connected to the selection gates of the selection gate transistors ST1 and ST2, and source lines SL is formed. A bit line BL is formed in the column direction on the memory cell array 10. Further, a power supply line and a ground line (not shown) are formed on the memory cell array 10.

  The control gates of the memory cell transistors MT in the same row are commonly connected to one of the word lines WLi, and the gates of the first selection gate transistors ST1 in the same row are commonly connected to the first selection gate line SGD. The gates of the second select gate transistors ST2 in the same row are commonly connected to the second select gate line SGS. That is, the memory cell transistor MT is formed near the region where the word line WLi and the element region intersect, and the first selection gate transistor ST1 is formed near the region where the selection gate line SGD and the element region intersect. The second select gate transistor ST2 is formed in the vicinity of the region where the select gate line SGS and the element region intersect. In the NAND cells 11 in the same column, the drains of the first selection gate transistors ST1 are commonly connected to the same bit line BL, and the sources of the second selection gate transistors ST2 are commonly connected to the source line SL.

  Data is collectively written in a plurality of memory cell transistors MT connected to the same word line WLi, and this unit is called a page. Further, data is erased collectively from a plurality of NAND cells 11 in the same row, and this unit is called a memory block.

  As shown in FIG. 2, the row decoder 30 includes a first decode region 31 formed including a MOS transistor (LV-Tr) operating at a low voltage LV, and a MOS transistor (HV-Tr operating at a high voltage HV). ) Is formed. In the second decoding area 32, a transfer gate transistor 34 (341, 342, etc., which will be described later), a block decoder 35, a word line (WL) driver 36, a first selection gate line driver (SGD driver) 37, a second selection A gate line driver (SGS driver) 38 is provided.

  The transfer gate transistor 34 is provided for each word line WLi and selection gate lines SGD and SGS, and one end of the current path is connected to the corresponding word line WLi and selection gate lines SGD and SGS. In this case, the other end of the current path of the transfer gate transistor 34 connected to the word line WLi is connected to the word line driver 36. The other ends of the current paths of the transfer gate transistors 34 connected to the selection gate lines SGD and SGS are connected to selection gate line drivers 37 and 38, respectively.

  Also, the block decoder 35 selects the gates of the select gate lines SGD and SGS connected to the select gate transistors ST1 and ST2 and the memory cell transistor MT in the same memory block and the transfer gate transistor 34 connected to the word line WLi. It is connected to the same block selection control line TG (TG1, TG2, etc. described later) to be controlled.

  The block decoder 35 decodes the block address signal and controls selection of the NAND cell 11. Then, a predetermined voltage is applied to the block selection control line TG connected to the transfer gate transistor 34 corresponding to the selected NAND cell 11, and this transfer gate transistor 34 is turned on.

  The word line driver 36 selectively drives one of the word lines WLi according to the row address, and applies a voltage via the current path of the transfer gate transistor 34 corresponding to the selected word line WLi.

  The selection gate line drivers 37 and 38 select the selection gate lines SGD and SGS according to the row address, respectively, and apply a voltage via the current path of the transfer gate transistor 34 corresponding to the selected selection gate lines SGD and SGS. .

  FIG. 3 is a plan view showing a pattern layout in the row decoder 30 in FIG. In the row decoder, element regions 41 of a plurality of active row decoders 40 are arranged in a matrix, and STI regions 42 are formed between the element regions. In this case, in this example, the plurality of element regions 41 are grouped in units of 66 corresponding to the 64 word lines WL0 to WL63 of the NAND cell and the two selection gate lines SGD and SGS.

  Each element region 41 can be operated at a high voltage by transferring a word line driving voltage from the word line driver 36 to the word line WLi, or by transferring voltages from the SGD driver 37 and SGS driver 38 to the selection gate lines SGD and SGS. A transfer gate transistor is formed. In this example, a first transfer gate transistor 341 and a second transfer gate transistor 342 are formed in the column direction as transfer gate transistors, and the two transfer gate transistors 341 and 342 share the drain region D. The shared drain region D is connected to the output node of the word line driver 36 or select gate line drivers 37 and 38.

  In the first transfer gate transistor 341, a gate electrode is formed on the channel region via a gate insulating film, and a first block selection control line TG1 is formed so as to continue to the gate electrode. The source region S1 of the first transfer gate transistor 341 is connected to one of the word lines WL0 to WL63 and select gate lines SGD and SGS of the NAND cell 11 in a predetermined block of the memory cell array 10.

  In the second transfer gate transistor 342, a gate electrode is formed on the channel region via a gate insulating film, and a second block selection control line TG2 is formed so as to be connected to the gate electrode. The source region S2 of the second transfer gate transistor 342 is connected to one of the word lines WL0 to WL63 and select gate lines SGD and SGS of the NAND cell 11 in a predetermined block of the memory cell array 10.

  The plurality of transfer gate transistors 341 and 342 located in the same row are allocated so as to be connected corresponding to the NAND cell 11 of the same memory block. That is, each of the source regions S1 of the 66 first transfer gate transistors 341 in the same group has 64 word lines WL0 to WL63 and 2 word lines of NAND cells in the odd-numbered (N) block of the memory cell array 10. The selection gate lines SGD and SGS are connected correspondingly. The source regions S2 of the 66 second transfer gate transistors 342 in the same group are connected to the 64 word lines WL0 to WL63 of the NAND cells of another odd-numbered (N + 2) block of the memory cell array 10. And two select gate lines SGD and SGS are connected to each other. Note that voltages are transferred from the 66 transfer gate transistors 34 in another same group to the NAND cells 11 in the even-numbered blocks of the memory cell array 10.

  A guard ring region 43 is disposed between one end of the active row decoder 40 in the row direction and the memory cell array 10 and between the plurality of active row decoders 40. In the guard ring region 43, the surface of the semiconductor substrate is exposed in the element region formed in a stripe shape in the column direction in the semiconductor substrate, and a predetermined voltage (in this example, the p-type semiconductor substrate is applied to the semiconductor substrate). To 0 V).

  In this embodiment, a dummy row decoder 44 is formed between the active row decoder 40 and the guard ring region 43, and an STI region 42 is formed between the dummy row decoder 44 and the active row decoder 40. A wide STI region 422 is formed between the dummy row decoder 44 and the guard ring region 43.

  A dummy element region 45 is formed in the dummy row decoder 44, and dummy transfer gate transistors 461, 462 are formed in the dummy element region 45 in the same pattern as the transfer gate transistors 341, 342 of the active row decoder 40. Is formed. That is, in the dummy element region 45, a first dummy transfer gate transistor 461 and a second dummy transfer gate transistor 462 are formed in the column direction, and the two dummy transfer gate transistors 461, 462 are drains. Share area D.

  In the first dummy transfer gate transistor 461, a gate electrode is formed on a channel region via a gate insulating film, and a first block selection control line TG1 is formed so as to be connected to the gate electrode. In the second dummy transfer gate transistor 462, a gate electrode is formed on the channel region via a gate insulating film, and a second block selection control line TG2 is formed so as to continue to the gate electrode. Yes.

  The source nodes S1 and S2 of the two dummy transfer gate transistors 461 and 462 are not connected to the word line WLi and the selection gate lines SGD and SGS. In addition, the drain nodes of the two dummy transfer gate transistors 461 and 462 are connected to nodes to which a predetermined voltage lower than the high voltage transferred by the transfer gate transistors 341 and 342 of the active row decoder 41 during data writing is applied. It is preferable to always connect. As the predetermined voltage, a value that minimizes a punch-through current flowing through the bottom of the STI is selected from intermediate voltages such as 8 V and 10 V that are used separately.

  A plurality of other active row decoders (second active row decoders) 40 are arranged on the other end side in the row direction of the plurality of active row decoders 40 via another guard ring region (second guard ring region) 43. Has been. Another dummy row decoder (second dummy row decoder) 44 is also formed between the other end in the row direction of the active row decoder 40 and the second guard ring region 43. In the second dummy row decoder 44, dummy transfer gate transistors 461, 462 formed in the same pattern as the transfer gate transistors 341, 342 of the active row decoder 40 are formed in the second dummy element region 45. Has been. Like the transfer gate transistors 341 and 342 of the active row decoder 40, the dummy transfer gate transistors 461 and 462 of the second dummy row decoder 44 have source nodes connected to the word line WLi and the selection gate lines SGD and SGS. It is not connected and is always connected to a node of a predetermined voltage.

  As described above, according to the NAND flash memory of the present embodiment, the dummy element region 45 is formed between the active row decoder 40 and the guard ring region 43, and the active row decoder 40 is formed in the dummy element region 45. Dummy transfer gate transistors 461 and 462 are formed in the same pattern as the transfer gate transistors 341 and 342 of FIG. The source nodes S1 and S2 of the dummy transfer gate transistors 461 and 462 are not connected to the word line WLi and selection gate lines SGD and SGS. With such a configuration, the transfer gate transistors 341 and 342 in the element region 41 of the active row decoder 40 located near the row direction end in the row decoder 30 and the guard ring region 43 transfer a high voltage (for example, 23 V). At this time, a leak component from the active row decoder 40 to the guard ring region 43 can be suppressed. Therefore, it is possible to prevent the transfer capability of the transfer gate transistors 341 and 342 of the active row decoder 40 near the row direction end and the guard ring region 43 from being deteriorated and excessive voltage stress is applied to the transfer gate transistors 341 and 342. The yield of the type flash memory can be improved.

341, 342 ... Transfer gate transistor, 40 ... Active row decoder, 41 ... Element region, 42 ... STI region, 422 ... Wide STI region, 43 ... Guard ring region, 44 ... Dummy row decoder, 45 ... Dummy device Area, 461, 462 ... Dummy transfer gate transistors, TG1, TG2 ... Block selection control lines.

Claims (4)

A stacked gate structure comprising a lower gate electrode, an intergate insulating film, and an upper gate electrode on at least one end side of a plurality of memory cell transistors having a stacked gate structure of floating gates and control gates on a semiconductor substrate via a gate insulating film. A memory cell array in which a cell array of NAND cells to which select gate transistors are connected is arranged in a matrix;
A word line formed in a row direction on the memory cell array and commonly connected to a control gate of a cell transistor in the same row in the memory cell array and a selection gate line commonly connected to an upper gate electrode of a selection gate transistor in the same row; ,
A plurality of first active rows in which transfer gate transistors for transferring a voltage to the word lines or selection gate lines are formed in element regions arranged in a matrix and formed in the vicinity of the row end of the memory cell array. A decoder;
A first guard ring region disposed between the first active row decoder and the memory cell array;
Comprising a first dummy row decoder formed between the first active row decoder and the first guard ring region;
The first dummy row decoder has a dummy transfer gate transistor formed in the dummy element region in the same pattern as the transfer gate transistor of the first active row decoder. A non-volatile semiconductor memory device, wherein a source node is not connected to the word line or the selection gate line.   2. The drain node of the dummy transfer gate transistor is always connected to a node having a predetermined voltage lower than the voltage transferred by the transfer gate transistor of the first active row decoder during data writing. The nonvolatile semiconductor memory device described. A plurality of second active row decoders are arranged on the other end side in the row direction of the plurality of first active row decoders via a second guard ring region. A second dummy row decoder is formed between the second guard ring region,
The second dummy row decoder has a dummy transfer gate transistor formed in the dummy element region in the same pattern as the transfer gate transistor of the first active row decoder, and the dummy transfer gate transistor The non-volatile semiconductor memory device according to claim 1, wherein the source node is not connected to the word line or the selection gate line.   The drain node of the dummy transfer gate transistor of the second dummy row decoder is always connected to a node having a predetermined voltage lower than the voltage transferred by the transfer gate transistor of the first active row decoder during data writing. The nonvolatile semiconductor memory device according to claim 3.

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