TWI450263B - Circuitry for active cable - Google Patents

Description

Circuit for active cable

The present application claims the benefit of U.S. Provisional Patent Application No. 61/360,432, filed on Jun. 30, 2010, and U.S. Provisional Patent Application Serial No. 61/446,027, filed on Feb. 23, 2011. The Power Distribution Inside Cable is related to the U.S. Patent Application Serial No. 13/___, ___ (Attorney Docket No. 20750P-025000US), which is hereby incorporated by reference.

Electronic devices often include connectors that provide power and data signals that can be shared with other devices. These connectors are often designed to conform to a standard so that the electronic devices can communicate with each other in a reliable manner. Various Universal Serial Bus (USB), Peripheral Component Fast Interconnect (PCIe), and DisplayPort (DP) standards are just a few examples.

Whenever necessary, the standard for using these connectors is replaced by newer standards. As a result, multiple connectors that provide similar functionality are often included on electronic devices. For example, many current televisions include inputs for HDMI, S-video, component video, and RCA jacks.

The inclusion of such connectors increases device size, complexity, and cost. Furthermore, the inclusion of several options can confuse and frustrate consumers as they attempt to determine the best way to configure a particular system.

If a connector can provide signals for more than one standard, some of this confusion can be reduced. For example, if a connector can provide signals for both legacy and newer standards, the number of connectors on the electronic device can be reduced, thereby enabling the device to be made smaller and simpler. flower Less fee.

In addition to this will be helpful (But as helpful as this would be), it is very difficult to implement. For example, a circuit associated with one standard can interfere with circuitry associated with another standard. This becomes even more difficult when the data rate is high because reflections and terminal mismatches caused by unused circuitry impair the performance of the circuit being used.

For example, newer and faster standards can share connectors with older, slower standards. Circuitry necessary for older standards can cause reflections and terminal mismatches for newer and faster standard circuits, thereby degrading system performance.

Therefore, there is a need for circuits, methods and apparatus that allow various standards to share a common connector.

Accordingly, embodiments of the present invention provide circuits, methods, and apparatus that allow for a common connector on a signal sharing electronic device that conforms to multiple standards. An exemplary embodiment of the present invention can provide a connector that provides signals that are compatible with older standards in one mode and newer standards in another mode. Usually, the old standard is slower, and the newer standard is faster, but this may not always be true.

In an exemplary embodiment of the invention, the pins for the newer standards can be configured to achieve at least two purposes. First, it can be configured to reduce crosstalk and interference in itself. This can be accomplished by placing a number of ground pins between the high speed differential signal paths. Second, circuitry can be added to minimize interference from circuits used in older standards. This can be done by reducing reflection and impedance mismatch.

Exemplary embodiments of the present invention are capable of providing multiple data standards by virtue of various features. In an exemplary embodiment of the invention, a device that is compatible with newer standards may be able to determine if it is communicating with a device that is compatible with legacy or newer standards. This can be done by sensing the first device of the voltage or impedance provided by the second device.

In various embodiments of the invention, when two devices in communication are capable of communicating with newer standards, the standard can be used by the two devices. In the case where a device can only operate with the old standard, the standard can be used by the two devices.

Embodiments of the present invention may provide circuitry for isolating unused circuitry for a standard from operational circuitry for another standard. In a particular example, a resistor, PiN diode, multiplexer, or other component or circuit can be used to isolate the two transmitter circuits from one another. Coupling capacitors and inductors can be used as DC blocking and AC filters to isolate the circuit.

Various embodiments of the invention may be combined with one or more of these and other features described herein. A better understanding of the nature and advantages of the present invention will be obtained in the light of the <RTIgt;

Figure 1 illustrates an older version of the system that can be modified by the incorporation of embodiments of the present invention. This figure illustrates a computer 110 that communicates with a legacy display 120 via an legacy connection 115. In a particular embodiment of the invention, legacy connection 115 is a DisplayPort connection, although other connections may be used in other embodiments of the invention.

In this figure, connection 115 is shown as a legacy connection. Other in the present invention In an embodiment, the connection 115 can also be a novel connection. Moreover, although computer 110 is shown as being in communication with display 120, other types of connections may be modified by the incorporation of embodiments of the present invention. For example, the connection can be provided between the portable media player and the display, between the computer and the portable media player, or between other types of devices. In various embodiments of the invention, computer 110, display 120, and other devices shown or discussed may be fabricated by Apple Inc. (Cupertino, California).

Again, it may be desirable for the computer 110 to be able to drive a legacy display (such as display 120) or any newer computer, display, or other type of device. Typically, this requires the addition of another connector on the computer 110. This may be undesirable because of the complexity, cost, and size of adding computer 110. The addition of another connector can also increase consumer confusion.

Thus, embodiments of the present invention may provide newer connections using the same connectors as the legacy connections 115. An example is shown in the figure below.

2 illustrates a computer system in accordance with an embodiment of the present invention. This figure is shown for illustrative purposes in conjunction with other figures, and does not limit the scope of the embodiments or claims of the invention.

This figure illustrates a computer 110 that communicates with a computer or display 220 via a high speed connection 225. The computer or display 220 communicates with the disk drive 230 via a high speed connection 235. The computer 110 can use the same connector to form the legacy connection 115 of FIG. 1 and the high speed connection 225 of FIG. As shown, the high speed connection provided by computer 110 can be daisy chained to multiple devices. In this configuration, each high speed connection 225 and 235 shares the bandwidth available at the connector of computer 110.

By providing on the computer 110 to support the old version of the connection 115 in Figure 1 and Figure 2 The high speed connection 225 connector reduces the number of connectors on the computer 110. This reduces device size, saves money and reduces consumer confusion. In this example, computer 110 is in communication with a computer or display 220 and disk drive 230. Other types of devices can be used in other embodiments of the invention. For example, computer 110 can drive a display of an all-in-one computer, a second computer, a stand-alone monitor, an expansion device, a raid drive, or other type of device.

Embodiments of the present invention may take into account at least two considerations when configuring an exit line for a high speed connection using an existing legacy connector. First, the signals in the different channels of the high speed connection can be configured such that they do not interfere with each other. That is, crosstalk between high speed signals can be reduced and the signals can be isolated. Second, the circuitry used to drive and receive new high speed signals and the circuitry associated with the legacy standards can be isolated to limit interference therebetween. An example is shown in the figure below.

Figure 3 illustrates the lead wires of a connector in accordance with an embodiment of the present invention. In this example, DisplayPort is an older version of the standard that has been overlaid by the pin for the new standard. This new standard may be referred to as T29, but is generally identified as HSIO elsewhere in this document. In other embodiments of the invention, other criteria may be used. Furthermore, one or both of these standards may be an old standard, or one or both of these standards may be a newer standard. Moreover, although the two standards are shown here as a common connector, in other embodiments of the invention, other numbers of standards may share the connector.

In various embodiments of the invention, the two criteria may be separate and unrelated. In other embodiments of the invention, it may be related. For example, HSIO can be a high-speed signaling technology that carries DisplayPort information. also That is, DisplayPort information can be tunneled using the HSIO signal. HSIO can also carry other types of signal information (such as PCIe information). In this way, the connector of Figure 3 can directly carry the DisplayPort signal, or it can carry DisplayPort information transmitted as HSIO signal. It should be noted that in various embodiments of the invention described below, HSIO is also referred to as T29.

In this configuration, the high speed input and output pins can be isolated from each other. In particular, the high-speed receiving signal can be placed on the pin 4 and the pin 6 as well as the pin 16 and the pin 18. Each of these signal pairs can be isolated by a signal that is AC grounded. For example, the high speed receiving pins 4 and 6 can be isolated by the hot plug detecting pin 2 and the grounding pin 8. Similarly, the high speed receiving pins 16 and 18 can be isolated by the ground 14 and the power pin 20. The high speed transmission pin 3 and the pin 5 and the pin 15 and the pin 17 can be isolated by the ground pins 1, 7, 13 and 19.

Some or all of the ground pins (such as pins 1 and 7) may be AC ground (as opposed to a direct DC connection to ground). That is, the pins can be coupled to ground via a capacitor. This provides a ground connection at high frequencies and an open circuit at low frequencies. This configuration allows the power supply to be received at these pins while maintaining ground at high frequencies.

In a particular embodiment of the invention, the pin 20 at the first end of the cable is connected to the pin 1 at the second end of the cable. This allows the power supplied by the host device on the pin 20 to be supplied to the pin 1 at the device connection. Since the pin 1 is coupled to ground via a capacitor, DC power can be received, but the pin 1 provides AC ground.

Also in this configuration, the high speed signal in the high speed HSIO standard can be shared with the appropriate signal of the old DisplayPort standard. In particular, the pin 4 and the high-speed receive signal on pin 6 can share the pin with the configuration signal in the DisplayPort standard. The high speed receive signal on pin 16 and pin 18 can share the pin with the auxiliary signal in the DisplayPort standard. The high-speed transmission signal on the pin 3 and the pin 5 can share the pin with the DisplayPort output signal, and the high-speed transmission signal on the pin 15 and the pin 17 can share the pin with the DisplayPort output signal.

Because these connectors support devices that use the DisplayPort or HSIO standard, there are at least four possible configurations when the two devices communicate with each other. For example, a DisplayPort host device can communicate with a DisplayPort device or a HSIO device. Furthermore, the HSIO host device can communicate with the DisplayPort device or another HSIO device. Therefore, devices that are compatible with the newer HSIO standard may be able to determine which type of device they are communicating with. Once the configuration is known, the device can be configured appropriately. An example is shown in the figure below.

4 illustrates circuitry and methods used in determining the type of device in communication with one another in accordance with an embodiment of the present invention. In line 410, the DisplayPort source or host is communicating with a DisplayPort sink or endpoint. The DisplayPort source or host provides pull-down resistors on configuration pins CFG1 and CFG2. In this example, the pull-down resistors are shown as 1 Meg size, but this may vary in accordance with embodiments of the present invention. The DisplayPort source or host is connected to the DisplayPort sink or endpoint via a passive cable. The DisplayPort sink or endpoint can operate as a DP device.

In line 420, the DisplayPort source or host communicates with the HSIO sink or endpoint. In this particular embodiment of the invention, the HSIO Meeting Point or Endpoint will not operate under these conditions, but in other embodiments of the invention, When the HSIO sink or endpoint is a display, the HSIO sink or endpoint can act as a DisplayPort sink or endpoint.

In line 430, the cable adapter is connected to the DisplayPort source or host. The cable adapter has a pull-up resistor on the configuration pin CFG2 that is much smaller than the source or the pull-down resistor in the host. Therefore, the voltage on the configuration pin CFG2 is pulled high. Cable adapters provide signals to sinks or endpoints of the HDMI or DVI type.

In line 440, the HSIO source or host communicates with the DisplayPort sink or endpoint via a passive cable. The HSIO source or host has pull-down resistors on the configuration pins CFG1 and CFG2. In this example, the pull-down resistors have a value of 1 Meg, but other sizes of resistors can be used in accordance with embodiments of the present invention. In this case, the HSIO source or host does not detect the pull-up resistor on the configuration pin CFG2, and therefore the HSIO source or host operates as a DisplayPort device.

In row 450, the HSIO source or host communicates with the HSIO sink or endpoint. In this configuration, active cables are required between the HSIO source or host and the HSIO sink or endpoint. The active cable has a 100 K pull-up resistor on the configuration pin CFG2, which provides a high voltage on pin CFG2. Both the HSIO source or host and the HSIO sink or endpoint detect this level and operate as an HSIO device.

In line 460, the cable adapter is connected to the HSIO source or host. The cable adapter has a pull-up resistor on the configuration pin CFG2 that is much smaller than the source or the pull-down resistor in the host. Therefore, the voltage on the configuration pin CFG2 is pulled high. Cable adapters provide signals to HDMI or DVI type sinks Or endpoint.

In various embodiments of the invention, it is desirable to increase the level of power provided by the source or host and the sink or endpoint. In a particular embodiment of the invention, this is accomplished using an LSx bus, as further described below. In another particular embodiment of the invention, this is accomplished by providing a 1K pull-down resistor on the configuration pin CFG1 in the cable. This is detected by the HSIO source or host and the HSIO sink or endpoint (for example) by providing a small current into the configuration pin. If the voltage remains low, the pull-down resistor is small and the high voltage mode is enabled. If the pull-down resistor's resistance is high, the resulting voltage will be high and the high voltage mode will not be enabled.

In various embodiments of the invention, this high power mode needs to be exited in some cases in order to protect the connected device. Therefore, if the cable is pulled, power is withdrawn from the device, or other conditions occur, and the high power phase can be exited. In a particular embodiment of the invention, the low power state may include providing a supply voltage of 3.3V, while the high power state may include providing a supply voltage of 12 volts. In various embodiments of the invention, the voltages may be different and may also vary depending on various conditions, such as the amount of line loss. To further conserve power, the cable can enter sleep mode once an inactivity period has been detected.

Furthermore, active cables may be required to support high speed standards. This cable may have the ability to retime data at each of its ends to provide easily recoverable data by the HSIO source or host and the HSIO Meeting Point or Endpoint. An example of this cable is shown in the figure below.

Figure 5 illustrates an active cable in accordance with an embodiment of the present invention. For simplicity See, only the circuits associated with high speed operation are shown. This cable includes two active plugs 500 and 505, one on each end of the cable 507. Each active plug includes a dual clock and data recovery circuit for retiming data. In particular, the active plug 500 provides a high speed transmission signal on the pin 3 and the pin 5, and receives a high speed signal on the pin 4 and the pin 6. Cable microcontroller 520 can be used to configure clock and data recovery circuits 510 and 530 in active plug 500.

Similarly, the active plug 505 provides a high speed transmission signal on the pin 3 and the pin 5, and receives a high speed signal on the pin 4 and the pin 6. Cable microcontroller 550 can be used to configure clock and data recovery circuits 540 and 560.

The clock and data recovery circuitry provides and receives signals in a variety of formats. For example, such circuits can include an optical receiver and transmitter such that the cable 507 becomes a mixture of optical fibers and electrical leads.

In various embodiments of the invention, the clock and data recovery circuitry may use equalizer circuitry, buffers, emphasis and de-emphasis circuitry (where appropriate). Furthermore, the return path may be included for diagnostic purposes. For example, the output of CDR 510 can be connected as an input to CDR 530, while the output of CDR 540 can be an input to CDR 560. This loopback path allows the HSIO device to determine where the transmission error occurred when a transmission error occurred. This loopback path can also be used when training or calibrating routes, as discussed below. In other embodiments, the cable can be self-communicated in an end-to-end manner for diagnostic purposes. Other features that may be included for diagnosis include eye size measurements.

In various embodiments of the invention, the cable can be configured. In this particular embodiment of the invention, the cable microcontroller 520 can be used to configure the cable plug The circuitry in head 500 can be used to configure the circuitry in cable plug 505 using cable microcontroller 550. In other embodiments of the invention, other circuits may be used to configure either or both of plugs 500 and 505.

In this particular embodiment of the invention, the operational parameters, modes, and other aspects and characteristics of the plug circuit can be configured. Information for this configuration can include parameters for control, diagnostics, testing, configuration, circuit monitoring, and other parameters. The ability to configure the cable in this manner allows the cable to adapt to new hosts and devices when the cable is used in a variety of system applications.

Information about cable types, vendor identification, and other identifying information can be obtained from the host or device and cable. This exchange of information can be used to properly configure and drive the circuitry in the host or device and cable.

In this particular embodiment of the invention, the configuration and identification information can be read from the cable and written to the cable using the LSx signals on the pins 9 and pins 11, but in other embodiments of the invention Other signal pins can be used.

In various embodiments of the invention, the code in cable microcontrollers 520 and 550 can be changed, reconfigured, upgraded, or updated. This code can be encrypted for security reasons. Furthermore, the information provided during code change, reconfiguration or update can be encrypted.

Also in various embodiments of the invention, the cable microcontroller can communicate with a helium microcontroller in a device (not shown) that is in communication via a cable. In a particular embodiment of the invention, the chirp microcontroller in the first device can be directly coupled to the cable microcontroller embedded in the plug in the first device and in the remote device attached to the remote plug.埠 Microcontroller communication. The "bounce back" message from the microcontroller in the remote device can be used with the remote or remote plug One step communication.

Such communication between the helium microcontroller and the cable microcontroller can take a variety of forms. Traditionally, interconnects have been fixed at each end, with few opportunities to discover improved performance or flexible implementation. Accordingly, embodiments of the present invention provide this communication capability such that, for example, a cable can share information about its characteristics with a host or device, and the host or device can utilize such features.

In other examples, such communication between various helium microcontrollers and cable microcontrollers may be diagnostic in nature. Such diagnostic communications may assist in fault isolation by the end user or other users, which may allow for rapid correction of problems and focus on the device that caused the failure. These communications can also be useful in testing and manufacturing. It can also be used to optimize configurations for power savings, for example, unused channels can be powered down, and low power remote devices can be powered by the host, eliminating the need for a connection to a wall outlet. Again, the power consumed by the remote device can be monitored and power up (or reduced) can be enabled as needed. It also allows the device to continue to operate regardless of various damage. It may also enable the use of copper or other conductors, or fibers in the cable itself.

Furthermore, in various embodiments of the invention, the cable can provide pull-up resistors on the configuration pins CFG1 and CFG2, and the device attached to the cable can provide pull-up resistors on its LSR2PTX pins. Device. (The pull-up resistor on the LSR2PTX pin can be attributed to the intersection of these lines in the cable by the remote device on its LSP2R RX pin, as shown). The pull-up resistor on CFG2 allows the device to determine that the cable is attached, even in the absence of a remote device. In a particular embodiment of the invention, when the cable is present In the absence of a remote device, nearby devices can communicate with the cable microcontroller in their plug, but may not be able to communicate with the cable microcontroller in the remote plug because there is no remote device to bounce back the message.

These various pull-up resistors can be used to provide other features in various embodiments of the invention. For example, in some embodiments of the invention, it can be used to detect when a host device is disconnected from one or more devices. For example, when the host device is powered down, the host device may be required to provide a power down signal to one or more devices. However, the host can disconnect before it can send this signal. In this case, the pull-up resistor on the LSR2PTX-free pin can be detected by the device and used by the device as an indication that it should be powered down.

In particular, the host device can enable its pull-up resistor on its LSR2PTX while the device pulls its pull-up resistor on its LSR2PTX low. If the device knows the pull-up resistor on its LSP2R RX pin, it knows that it is connected to the host device. It can then enable the pull-up resistor on the LSR2PTX on each of its turns, thereby notifying the daisy-chain device that there is a host connected somewhere upstream. In this way, when the host is removed, the upper pull limiter on the LSR2PTX is removed and the device again pulls its LSR2PTX pullup resistor low, thereby notifying the daisy chain device host that it has been disconnected.

As shown in this figure, the power received on the pin 20 at a connector is provided at the pin 1 of the remote connector. This prevents the power supplies of the devices connected to each end of the cable from competing with each other. The fact is that the power on the pin 20 of the first connector is supplied to the second connector on the pin 1.

In the example cable of Figure 5, a single data path is shown in each direction. In other embodiments of the invention, two or more letters may be included Number path. An example is shown in the figure below.

Figure 6 illustrates an active cable in accordance with an embodiment of the present invention. Again, only the circuitry associated with the high speed path is shown for simplicity. In this example, additional clock and data recovery circuits 615 and 635 have been added to active plug 600, and clock and data recovery circuits 645 and 665 have been added to active plug 605.

In this and other embodiments of the invention, the circuitry in the plug can be powered by one or both of the devices connected by the cable. For example, a host device connected to plug 600 can provide power for plugs 600 and 605 and a host connected to plug 605. In other examples, the device connected to plug 605 can receive a high voltage from a host connected to plug 600, which can provide power to plugs 600 and 605. In still other examples, a host connected to plug 600 can provide power to plug 600, and a device connected to plug 605 can provide power to plug 605. A specific example of this can be found in U.S. Patent Application Serial No. 13/___, ___ (Attorney Docket No. 20750P-025000US), which is incorporated herein by reference. The case is incorporated by reference.

Furthermore, embodiments of the present invention allow signals sharing the pins between the two standards to not interfere with each other. Thus, embodiments of the present invention use circuit components to help isolate signal paths. The example is shown in the figure below.

7A-7C illustrate circuitry that can be used to allow common pins of a connector from signal paths from two different standards. In various embodiments of the invention, such circuitry may be located in or associated with the connector receptacle, the connector insert, or both. In Figure 7A, the HSIO output can share a pin with the DisplayPort output. here In both cases, the two outputs can be AC coupled via a capacitor to provide DC isolation from each other. The capacitor can be connected to the connector pin via a resistor network as shown. This resistor network degrades the signal level by 6dB, but provides 12dB of isolation.

In Figure 7B, the high speed input and configuration inputs share the connector pins. In this case, the high speed receive path can be AC coupled to provide isolation to the DC voltage on the configuration pin. The configuration pins can be isolated via resistors. Additional capacitors can be included to provide further filtering as shown. In other embodiments of the invention, the configuration pins can be directly coupled to the connector pins.

In Figure 7C, the high speed input can share the pin with the auxiliary input. Again, the high speed input can be AC coupled to provide a DC block. The auxiliary pins can be isolated via an inductor that can block AC signals (such as high speed signals in 70 Mbps to 10 Gbps) while allowing DC or low frequency signals (such as signals at 1 MHz or lower) to pass. Again, additional capacitors can be included to provide further filtering as shown. Again, the AUX input can be AC coupled as shown.

8A and 8B illustrate an alternative circuit that can be used to allow common pins of a connector from two different standard signal paths. In various embodiments of the invention, such circuitry may be located in or associated with the connector receptacle, the connector insert, or both. In Figure 8A, the HSIO output can share a pin with the DisplayPort output. In this example, the two outputs can be AC coupled via capacitors C1 and C2 to provide DC isolation from each other. Capacitors C1 and C2 can be coupled to the connector pins via PiN diodes D1 and D2.

In particular, when the high speed output is active, the high speed bias signal HSBIAS is active, driving the output of buffer B3 high. This biases the PiN diode D1 to be on and connects the capacitor C1 to the connector pin. Driver B1 drives the output signal to the connector pins via capacitor C1 and diode D1.

When the DisplayPort output is active, the DisplayPort bias signal DPBIAS is active, driving the output of buffer B4 high. This biases the PiN diode D2 such that it turns "on" and connects the output of capacitor C2 to the connector pin. Driver B2 can then drive the signal to the connector pins via capacitor C2 and diode D2.

When the high speed output is active, care should be taken to avoid reflections through the DisplayPort path that can interfere with the output signal as a connector pin. For this reason, an embodiment of the invention may include an additional pad P1 between capacitor C2 and diode D2 as shown. This pad P1 can be formed by a resistor pi or t-type network or other suitable attenuator.

When the high speed output is active, the signal at the connector pin can pass through diode D2 (which is turned off), then through pad P1 and capacitor C2, thereby outputting in DisplayPort buffer B2 (which is turned off) Appeared at the place. Although the DisplayPort driver B2 is turned off at this time, a signal can be reflected at its output and travel forward again through the capacitor C2, the pad P1, and the diode D2, thereby appearing at the connector pin and interfering with the desired signal.

In a particular embodiment of the invention, the disconnected diode D2 provides approximately 6 dB of attenuation to the return signal. Pad P1 provides an additional 4dB of attenuation, while DisplayPort Buffer B2 provides an additional 10dB of signal reduction due to The signal is reflected for it and sent forward. As the signal travels forward, it encounters pad P1 and diode D2 again and is again attenuated by it. In this way, the reflected signal passes through the pad P1 twice and is thereby attenuated twice. When DisplayPort output B2 is active, pad P1 attenuates the signal but only attenuates once. Thus, in various embodiments of the invention, DisplayPort buffer B2 has an increased drive strength to account for the loss due to pad P1.

In a particular embodiment of the invention, the high speed output is approximately twice as fast as the DisplayPort output. In this case, the pad (such as P1) need not be in the high speed transmission path, but it may be included.

In various examples, such as Figure 8A, the signal path is shown as being single-ended for clarity. In various embodiments of the invention, the signal path can be single ended or differential.

In Figure 8B, the high speed input can share the pin with the auxiliary input. As previously mentioned, the high speed input can be AC coupled by capacitor C1 to provide a DC rejection. The auxiliary input pin can be isolated via an inductor L1 that blocks the AC signal while allowing the DC signal to pass. Additional capacitor C2 can be included to provide further filtering as shown. As previously mentioned, the AUX signal path can be AC coupled via capacitor C3 as shown.

In some embodiments of the invention, the auxiliary signal may be an I2C signal. In this case, the loading caused by the input resistance of capacitor C1 and buffer B1 may be sufficient to overload the driver providing the I2C signal and cause an error in the I2C signal transmission. Thus, embodiments of the invention may include a PiN diode D1 as shown. This pin diode can be used to isolate capacitor C1 when capacitor C1 is not needed.

In particular, when an I2C signal is received, the bias signal HSBIAS can be inactive (low), which drives the output of buffer B2 low. This in turn disconnects the diode D1, thereby isolating the I2C signal from the capacitor C1. The multiplexer M1 can select an I2C line.

Similarly, when an AUX signal is received, HSBIAS can be low again, which isolates capacitor C1 from the AUX line. The multiplexer M1 can select an AUX signal path that can be AC coupled again via capacitor C3.

When a high speed signal is received, HSBIAS can be active (high), thereby driving the output of buffer B2 high. The multiplexer M1 can select a resistor R3 that provides a return path from the current provided by D1 from the output of the buffer B2. This turns on the diode D1 and couples the connector pins to the capacitor C1 for reception of high speed signals.

Various displays may include a dedicated cable that is attached as part of the display. These may be referred to as cable cables. Cables can be used for DisplayPort monitors or for HSIO monitors, as well as other types of monitors. Again, these cables can be driven by a DisplayPort or HSIO source. Therefore, it is required that such devices be able to determine what they are connected to so that they can properly configure themselves. An example of this is shown in the image below.

Figure 9 illustrates the circuitry and method used by the device in determining what type of device it is connected to. In line 910, the DisplayPort source or host communicates with the DisplayPort sink or endpoint. Furthermore, the configuration pins CFG1 and CFG2 are pulled down. The cable connection can be a passive cable, and the DisplayPort sink or endpoint can operate as a DisplayPort device.

In line 920, the DisplayPort source or host communicates with the HSIO sink or endpoint. Because the sink or endpoint is an HSIO device, the cable is active. However, because the source or host is a DisplayPort device, the cable can operate in bypass mode to conserve power. That is, the included clock and data recovery circuitry can be inactive. Because the HSIO sink or endpoint does not detect a pull-up resistor on the LSx pin (which can be an LSR2P TX pin), it can operate in DisplayPort mode. The HSIO Meeting Point can also drive CFG2 low.

In line 930, the source or host is a HSIO device and the sink or endpoint is a DisplayPort device. The HSIO source or host provides pull-up resistors on the CFG1 and CFG2 lines. In this example, the pull-down resistor has a value of 1 Meg, but other resistors may be used in accordance with embodiments of the present invention. The HSIO source or host determines that the voltage on configuration pin CFG2 is low (ie, there is no pull-up resistor) and CFG1 is also low (hence, the cable is not a connector). Therefore, the HSIO source or host operates in DisplayPort mode.

In line 940, the HSIO source or host communicates with the HSIO sink or endpoint. As mentioned earlier, the HSIO source or host provides the pull-up resistor on the LSX pin and the pull-down resistor on the configuration pins CFG1 and CFG2. The HSIO sink or endpoint detects the pullup resistor on the LSx pin and therefore operates as a HSIO device. In this example, a sink or display can provide a 100 K pull-up resistor on CFG2, but in other embodiments of the invention, other sized resistors can be used. Therefore, the HSIO source or host detects that the voltage on pin CFG2 is high and therefore operates as a HSIO device.

In a particular embodiment of the invention, the cable has a circuit that can include circuitry Plug, and Y cable (which may include additional circuitry). In other embodiments of the invention, all of the circuitry may be included in the plug or Y cable portion of the cable. An example is shown in the figure below.

Figure 10 illustrates a circuit for a cable connection in accordance with an embodiment of the present invention. A plug is provided for embedding into a connector, such as the connector shown in FIG. 2. The plug is attached to a plug attached to the Y cable portion, the Y cable portion being connected to the Y cable housing portion, the Y cable housing portion further including an electrical circuit. The Y cable is attached to the monitor multilayer from that side.

In this example, the high speed signals are received by the monitor via clock and data recovery circuits 1010 and 1030, and the clock and data recovery circuits 1010 and 1030 can be located in the Y cable housing. The outputs of the clock and data recovery circuits are provided to clock and data recovery circuits 1020 and 1040. The outputs of the clock and data recovery circuits 1020 and 1040 are provided as HSIO or DisplayPort signals by the PiN diodes D1 through D4. Note that the bias resistors for the PiN diodes D1 to D4 in this figure have been omitted for clarity. Furthermore, when the cable is activated to provide a DisplayPort signal, the clock and data recovery circuitry can operate in a bypass mode to conserve power. Similarly, the high speed signals provided from the monitor clock and data recovery circuits 1050 and 1070 are received and provided to the connector via the clock and data recovery circuits 1060 and 1080 in the plug. These signals can be isolated as shown.

In the example shown, PiN diodes D1 through D4 are used to isolate the HSIO signal and the DisplayPort signal. In other embodiments of the invention, resistors, multiplexers, or other circuits or components may be used.

In various embodiments of the invention, the host, the cable, and other devices are available Calibration circuits or training circuits in the device to improve the reliability and accuracy of the data connection. This circuit may include circuitry to compensate for cable skew, crosstalk (especially in a connector), channel compensation (such as reflection equalization or cancellation), and other such circuitry. Various parameters can be used to adjust these circuits. In various embodiments of the invention, the parameters of such circuits may be calibrated or otherwise determined by the manufacturer and stored as preset values for loading during operation. In other embodiments of the invention, such parameters may be determined while the system is connected. This training or calibration can occur during power up, restart, or other period or event based time. These or other routes may be used to calibrate the path from the host to the proximal end of the cable, the path through the cable, and the path from the cable to the device or other host.

This calibration can be performed in a variety of ways. For example, the host can place the near end of the cable in loopback mode, transfer the data, and receive the data, and then adjust the transmission and reception parameters accordingly. Similarly, the device can place its proximal end in loopback mode, transmit data, and receive data, and then adjust the transmission and reception parameters accordingly. Either or both of the host or device can also place their remote end in loopback mode, thereby also including the cable in the calibration route. An example is shown in the figure below.

Figure 11 illustrates a method of calibrating a cable and associated circuitry in accordance with an embodiment of the present invention. In act 1110, a calibration or training program begins. This can be triggered by power up, cable connections, reset conditions, or other periodic or event driven criteria. In act 1120, the proximal end of the cable is placed in a loopback mode. In act 1130, signals are transmitted and received via a loopback path. In act 1140, the transmission and reception parameters of the near-end circuit can be optimized. At action 1150 The remote end of the cable can be placed in loopback mode. Furthermore, in act 1160, signals can be transmitted and received via the loopback path. In act 1170, the transmission and reception parameters of the remote circuit can be optimized. This program can be executed by either or both of the host and device circuitry.

The above description of the embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention. The embodiment was chosen and described in order to best explain the embodiments of the invention and the embodiments of the invention The invention is well utilized. Therefore, it is to be understood that the invention is not intended to

1‧‧‧ Grounding pin

2‧‧‧Hot plug detection pin

3‧‧‧High speed transmission pin

4‧‧‧High speed receiving pin

5‧‧‧High speed transmission pin

6‧‧‧High speed receiving pin

7‧‧‧ Grounding pin

8‧‧‧ Grounding pin

9‧‧‧ pin

10‧‧‧ pin

11‧‧‧ pin

12‧‧‧ pin

13‧‧‧ Grounding pin

14‧‧‧ Grounding pin

15‧‧‧High speed transmission pin

16‧‧‧High speed receiving pin

17‧‧‧High speed transmission pin

18‧‧‧High speed receiving pin

19‧‧‧ Grounding pin

20‧‧‧Power pin

110‧‧‧ computer

115‧‧‧Old version connection

120‧‧‧Old version of the display

220‧‧‧Computer or display

225‧‧‧High speed connection

230‧‧‧Disk machine

235‧‧‧High speed connection

410‧‧‧

420‧‧‧

430‧‧‧

440‧‧‧

450‧‧‧

460‧‧‧

500‧‧‧Active plug/cable plug

505‧‧‧Active plug/cable plug

507‧‧‧ cable

510‧‧‧ Clock and Data Recovery Circuit/CDR

520‧‧‧ Cable Microcontroller

530‧‧‧ Clock and Data Recovery Circuit/CDR

540‧‧‧ Clock and Data Recovery Circuit/CDR

550‧‧‧ Cable Microcontroller

560‧‧‧ Clock and Data Recovery Circuit/CDR

600‧‧‧Active plug

605‧‧‧Active plug

607‧‧‧ cable

610‧‧‧ Clock and Data Recovery Circuit/CDR

615‧‧‧ Clock and Data Recovery Circuit/CDR

620‧‧‧ Cable Microcontroller

630‧‧‧ Clock and Data Recovery Circuit/CDR

635‧‧‧ Clock and Data Recovery Circuit/CDR

640‧‧‧ Clock and Data Recovery Circuit/CDR

645‧‧‧ Clock and Data Recovery Circuit/CDR

650‧‧‧ Cable Microcontroller

660‧‧‧ Clock and Data Recovery Circuit/CDR

665‧‧‧ Clock and Data Recovery Circuit/CDR

910‧‧‧

920‧‧‧

930‧‧‧

940‧‧‧

1010‧‧‧ Clock and Data Recovery Circuit/CDR

1020‧‧‧ Clock and Data Recovery Circuit/CDR

1030‧‧‧ Clock and Data Recovery Circuit/CDR

1040‧‧‧ Clock and Data Recovery Circuit/CDR

1050‧‧‧ Clock and Data Recovery Circuit/CDR

1060‧‧‧ Clock and Data Recovery Circuit/CDR

1070‧‧‧ Clock and Data Recovery Circuit/CDR

1080‧‧‧clock and data recovery circuit/CDR

B1‧‧‧Drive/Buffer

B2‧‧‧Drive/Buffer

B3‧‧‧ buffer

B4‧‧‧ buffer

C1‧‧‧ capacitor

C2‧‧‧ capacitor

C3‧‧‧ capacitor

CFG1‧‧‧ configuration pin

CFG2‧‧‧ configuration pin

D1‧‧‧PiN diode

D2‧‧‧PiN diode

D3‧‧‧PiN diode

D4‧‧‧PiN diode

L1‧‧‧Inductors

M1‧‧‧ multiplexer

P1‧‧‧ cushion

R1‧‧‧Resistors

R2‧‧‧ resistor

R3‧‧‧Resistors

1 illustrates a legacy system that can be modified by the incorporation of embodiments of the present invention; FIG. 2 illustrates a computer system in accordance with an embodiment of the present invention; and FIG. 3 illustrates a lead wire of a connector in accordance with an embodiment of the present invention; 4 illustrates a circuit and method for determining the type of device in communication with each other in accordance with an embodiment of the present invention; FIG. 5 illustrates an active cable consistent with an embodiment of the present invention; and FIG. 6 illustrates an active embodiment consistent with an embodiment of the present invention Cables; Figures 7A-7C illustrate circuits that can be used to allow common pins of the connector from two different standard signal paths; Figures 8A and 8B illustrate signals that can be used to allow for two different standards Alternative circuitry for common pins of the path sharing connector; Figure 9 illustrates the circuitry and method used by the device in determining what type of device it is connected to; Figure 10 illustrates a cable connection in accordance with an embodiment of the present invention Circuitry; and Figure 11 illustrates a method of calibrating a cable and associated circuitry in accordance with an embodiment of the present invention.

600‧‧‧Active plug

605‧‧‧Active plug

607‧‧‧ cable

610‧‧‧ Clock and Data Recovery Circuit/CDR

615‧‧‧ Clock and Data Recovery Circuit/CDR

620‧‧‧ Cable Microcontroller

630‧‧‧ Clock and Data Recovery Circuit/CDR

635‧‧‧ Clock and Data Recovery Circuit/CDR

640‧‧‧ Clock and Data Recovery Circuit/CDR

645‧‧‧ Clock and Data Recovery Circuit/CDR

650‧‧‧ Cable Microcontroller

660‧‧‧ Clock and Data Recovery Circuit/CDR

665‧‧‧ Clock and Data Recovery Circuit/CDR

Claims (22)

An active cable comprising: a cable; a first plug connected to one of the first ends of the cable and comprising: a first clock and a data recovery circuit re-timed at the first plug a signal received at an input; a second clock and data recovery circuit that retimes the signal received from the cable; and a first microcontroller that configures the first clock and data recovery circuit And the second clock and data recovery circuit; and a second plug connected to the second end of the cable and comprising: a third clock and data recovery circuit, re-timed at the second plug a signal received at an input; a fourth clock and data recovery circuit that retimes the signal received from the cable; and a second microcontroller that configures the third clock and data recovery circuit And the fourth clock and data recovery circuit. The active cable of claim 1, wherein the cable connects the output of one of the first clock and data recovery circuits to one of the fourth clock and data recovery circuits and the third clock and An output of one of the data recovery circuits is coupled to one of the input terminals of the second clock and data recovery circuit. The active cable of claim 1, wherein the first microcontroller and the second microcontroller are programmable using the first plug and the pin on the second plug. The active cable of claim 1, wherein the first clock and data recovery circuit comprises an equalizer circuit. The active cable of claim 1, wherein the first clock and data recovery circuit includes a de-emphasis circuit. The active cable of claim 1, wherein the first microcontroller is configurable to output one of the first clock and data recovery circuits to one of the second clock and data recovery circuits. The active cable of claim 1, wherein the first microcontroller is configurable to output an output of the second clock and data recovery circuit to one of the first clock and data recovery circuits. A cable assembly comprising: a cable; a first plug coupled to one of the first ends of the cable and including a first circuit for receiving and transmitting signals; and a second plug coupled to And at a second end of the cable and including a second circuit for receiving and transmitting a signal, wherein when the cable transmits a signal conforming to a first agreement, the first circuit and the second circuit are powered, and The first circuit and the second circuit are not powered when the cable is delivered in accordance with a signal of a second agreement. The cable assembly of claim 8, wherein the first circuit includes a first clock and data recovery circuit having an input coupled to the pin of the first plug and coupled to the cable A second clock of the conductor and a data recovery circuit. The cable assembly of claim 9, further comprising the first A clock and data recovery circuit and a microcontroller for the second clock and data recovery circuit. The cable assembly of claim 10, wherein the microcontroller is programmable using at least one pin of the first plug. The cable assembly of claim 11, wherein the microcontroller is programmable using a code provided at the at least one pin of the first plug. The cable assembly of claim 12, wherein the code is encrypted. An electronic device comprising: a connector comprising a plurality of pins; a first output circuit coupled to one of the plurality of pins and comprising: a selection circuit coupled To the first pin; a first driver AC coupled to the select circuit; and a second driver AC coupled to an attenuator coupled to the select circuit. The electronic device of claim 14, wherein the connector is a connector insert. The electronic device of claim 14, wherein the connector is a connector socket. The electronic device of claim 14, wherein the attenuator is a pi network. The electronic device of claim 14, wherein the selection circuit comprises a plurality of PiN diodes. The electronic device of claim 14, wherein the selection circuit comprises a multiplexer. The electronic device of claim 14, further comprising a receiving circuit, the receiving circuit comprising: a first switch having a first terminal coupled to one of the plurality of pins; a receiving a circuit electrically coupled to the second terminal of the first switch; an inductor having a first terminal coupled to the second pin; and a capacitor coupled to the one of the inductor Between the two terminals and the ground. The electronic device of claim 20, further comprising a multiplexer coupled to the second terminal of the inductor. The electronic device of claim 20, wherein the switch comprises a PiN diode.