TWI449025B - Power distribution inside cable - Google Patents
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Description
本申請案主張2010年6月30日申請之美國臨時專利申請案第61/360,432號及2011年2月23日申請之美國臨時專利申請案第61/446,027號的權利,且與名為用於主動纜線之電路(Circuitry for Active Cable)之同在申請中的美國專利申請案第13/ , 號(代理人檔案號碼20750P-02500US)有關,該等案以引用的方式併入。The present application claims the benefit of U.S. Provisional Patent Application No. 61/360,432, filed on Jun. 30, 2010, and U.S. Provisional Patent Application Serial No. 61/446,027, filed on Feb. 23, 2011. Circuitry for Active Cable, US Patent Application Serial No. 13/ , No. (Agency file number 20750P-02500US), these cases are incorporated by reference.
電子器件常常包括連接器,該等連接器用以提供電力及資料信號可與其他器件共用所在之埠。此等連接器常常經設計以順應一標準,使得電子器件可以可靠方式彼此通信。各種通用串列匯流排(USB)、周邊組件快速互連(PCIe)及DisplayPort(DP)標準僅為幾個實例。Electronic devices often include connectors that provide power and data signals that can be shared with other devices. These connectors are often designed to conform to a standard so that the electronic devices can communicate with each other in a reliable manner. Various Universal Serial Bus (USB), Peripheral Component Fast Interconnect (PCIe), and DisplayPort (DP) standards are just a few examples.
通常,器件經由纜線通信。此等纜線可在每一端上具有插塞或嵌入物,該插塞或嵌入物插入至器件中之插座中。但此等標準之資料速率正驚人地增加,且為了使器件在此等較高之資料速率下通信,需要新型纜線。Typically, the device communicates via a cable. These cables may have plugs or inserts on each end that are inserted into the sockets in the device. However, the data rates of these standards are increasing dramatically, and new cables are needed to enable devices to communicate at these higher data rates.
為滿足此等增加之資料速率,主動電路可包括於纜線中。但此等主動電路需要被供電。通常不需要使用不同於所連接器件中之一者的源提供電力至此等纜線。亦即,可能不需要使用第二纜線對第一纜線供電。To meet these increased data rates, active circuitry can be included in the cable. But these active circuits need to be powered. It is generally not necessary to provide power to such cables using a source other than one of the connected devices. That is, it may not be necessary to use a second cable to power the first cable.
為此原因,可藉由由纜線所連接之器件將電力提供至纜線中之主動電路。但此等器件可具有不等之電力遞送能力。舉例而言,第一器件可由壁式電源插座供電,而第二器件可自第一器件得到其電力。再者,各種器件可提供各種電壓位準。For this reason, power can be supplied to the active circuitry in the cable by means of a device connected by the cable. However, such devices may have unequal power delivery capabilities. For example, the first device can be powered by a wall outlet and the second device can derive its power from the first device. Furthermore, various devices can provide various voltage levels.
因此,需要以智慧且可組態之方式對纜線中之主動電路供電的電路、方法及裝置。亦可能需要藉由提供諸如睡眠及其他較低電力狀態之各種狀態而減少電力。Therefore, there is a need for circuits, methods and apparatus for powering active circuits in a cable in a smart and configurable manner. It may also be desirable to reduce power by providing various states such as sleep and other lower power states.
因此,本發明之實施例提供以智慧且可組態之方式對纜線中之主動電路供電的電路、方法及裝置。Accordingly, embodiments of the present invention provide circuits, methods and apparatus for powering active circuits in a cable in a smart and configurable manner.
在本發明之各種實施例中,可以各種方式對在一纜線之每一端處的連接器嵌入物中之主動組件供電。舉例而言,在一主機耦接至一並非自供電之器件的情況下,該主機可為該纜線之每一端處的電路提供電力。在本發明之各種實施例中,該器件可向該主機請求較高電壓,使得可遞送更多電力。在此等狀況下,該器件可將自該主機所接收之電壓調節至一較低電壓,且接著將該較低電壓提供至該纜線之一端或兩端處的電路。在該主機連接至一為自供電之器件的情況下,該主機及該自供電器件可對其各別連接器嵌入物電路供電。In various embodiments of the invention, the active components in the connector insert at each end of a cable can be powered in a variety of ways. For example, where a host is coupled to a device that is not self-powered, the host can provide power to circuitry at each end of the cable. In various embodiments of the invention, the device can request a higher voltage from the host such that more power can be delivered. Under such conditions, the device can adjust the voltage received from the host to a lower voltage and then provide the lower voltage to circuitry at one or both ends of the cable. Where the host is connected to a self-powered device, the host and the self-powered device can power their respective connector embedded circuits.
更特定言之,在本發明之一實施例中,一主機可經耦接以與一並非由一壁式電源插座或其他外部電源供電之器件通信,但在本發明之各種實施例中,該器件可由一內部或外部電池供電。該主機可經由纜線提供一低電壓供應至該器件。可自此相同之低電壓供應對該纜線中之電路供電。纜線電路可包括在連接至該主機之一第一纜線插塞中之電路,及在連接至該器件之一第二纜線插塞中的電路。More specifically, in one embodiment of the invention, a host can be coupled to communicate with a device that is not powered by a wall outlet or other external power source, but in various embodiments of the invention, The device can be powered by an internal or external battery. The host can provide a low voltage supply to the device via a cable. The circuit in the cable can be powered from the same low voltage supply. The cable circuit can include circuitry in a first cable plug that is coupled to one of the hosts, and circuitry in a second cable plug that is coupled to the device.
在本發明之另一實施例中,一主機可提供一較高電壓至一器件。此較高電壓可提供一增加量之電力至該器件,且其可允許對該器件中或與該器件相關聯之電池較快充電。但可能不需要此較高電壓來對纜線電路供電,且使用該較高電壓可引起該纜線中之過多電力耗散。此較高電力耗散又可引起發熱及一不愉快之使用者體驗。因此,該器件可接收此較高電壓,且將該較高電壓減小至一較低電壓。此較低電壓接著可用以對纜線電路供電。以此方式,將該高電壓減小至一較低電壓所需的電路僅包括於將使用其之器件上,且其無需包括於每一主機器件上。In another embodiment of the invention, a host can provide a higher voltage to a device. This higher voltage can provide an increased amount of power to the device, and it can allow for faster charging of the battery in or associated with the device. However, this higher voltage may not be needed to power the cable circuit, and using this higher voltage may cause excessive power dissipation in the cable. This higher power dissipation can cause heat and an unpleasant user experience. Thus, the device can receive this higher voltage and reduce the higher voltage to a lower voltage. This lower voltage can then be used to power the cable circuit. In this way, the circuitry required to reduce the high voltage to a lower voltage is only included on the device that will be used, and it need not be included on each host device.
在本發明之另一實施例中,一主機可與一為自供電或由一壁式電源插座或其他電源供電之器件通信。在此狀況下,該主機及該器件可各自對其連接至的插塞中之電路供電。In another embodiment of the invention, a host can communicate with a device that is self powered or powered by a wall outlet or other power source. In this case, the host and the device can each power the circuitry in the plug to which they are connected.
在本發明之其他實施例中,可在一纜線上提供順應多個協定中之一者的信號。本發明之此等實施例可提供用以偵測正使用哪一協定的電路。再者,本發明之實施例可提供用以藉由斷開未使用之電路及在不活動週期期間提供睡眠狀態而節約電力的電路。In other embodiments of the invention, signals compliant with one of a plurality of agreements may be provided on a cable. Such embodiments of the invention may provide circuitry for detecting which protocol is being used. Furthermore, embodiments of the present invention can provide circuitry for conserving power by disconnecting unused circuitry and providing a sleep state during periods of inactivity.
本發明之各種實施例可併有本文中所描述之此等及其他特徵中之一或多者。藉由參考以下實施方式及隨附圖式,可得到對本發明之本質及優點的更好理解。Various embodiments of the invention may be combined with one or more of these and other features described herein. A better understanding of the nature and advantages of the present invention will be obtained in the light of the <RTIgt;
圖1說明可藉由本發明之實施例的併入而改良之舊版系統。此圖說明經由舊版連接115與舊版顯示器120通信之電腦110。在本發明之特定實施例中,舊版連接115為DisplayPort連接,但在本發明之其他實施例中,可使用其他連接。Figure 1 illustrates an older version of the system that can be modified by the incorporation of embodiments of the present invention. This figure illustrates a computer 110 that communicates with a legacy display 120 via an legacy connection 115. In a particular embodiment of the invention, legacy connection 115 is a DisplayPort connection, although other connections may be used in other embodiments of the invention.
在此圖中,連接115展示為舊版連接。在本發明之其他實施例中,連接115亦可為新型連接。再者,儘管電腦110展示為與顯示器120通信,但可藉由本發明之實施例的併入而改良其他類型之連接。舉例而言,連接可提供於攜帶型媒體播放器與顯示器之間、電腦與攜帶型媒體播放器之間,或其他類型之器件之間。在本發明之各種實施例中,電腦110、顯示器120及所示或所論述之其他器件可藉由Apple Inc.(Cupertino,California)來製造。In this figure, connection 115 is shown as a legacy connection. In other embodiments of the invention, the connection 115 can also be a novel connection. Moreover, although computer 110 is shown as being in communication with display 120, other types of connections may be modified by the incorporation of embodiments of the present invention. For example, the connection can be provided between the portable media player and the display, between the computer and the portable media player, or between other types of devices. In various embodiments of the invention, computer 110, display 120, and other devices shown or discussed may be fabricated by Apple Inc. (Cupertino, California).
再者,可能需要電腦110能夠驅動舊版顯示器(諸如,顯示器120)或任何較新之電腦、顯示器或其他類型的器件。通常,此需要在電腦110上添加另一連接器。此可能為不合需要的,因為其添加電腦110之複雜性、成本及大小。另一連接器之添加亦可增加消費者混亂。Again, it may be desirable for the computer 110 to be able to drive a legacy display (such as display 120) or any newer computer, display, or other type of device. Typically, this requires the addition of another connector on the computer 110. This may be undesirable because of the complexity, cost, and size of adding computer 110. The addition of another connector can also increase consumer confusion.
因此,本發明之實施例可提供使用與舊版連接115相同之連接器的較新連接。下圖中展示一實例。Thus, embodiments of the present invention may provide newer connections using the same connectors as the legacy connections 115. An example is shown in the figure below.
圖2說明根據本發明之實施例的電腦系統。此圖與其他所包括圖一起出於說明性目的而展示,且不限制本發明之實施例或申請專利範圍。2 illustrates a computer system in accordance with an embodiment of the present invention. This figure is shown for illustrative purposes in conjunction with other figures, and does not limit the scope of the embodiments or claims of the invention.
此圖說明經由高速連接225與電腦或顯示器220通信之電腦110。電腦或顯示器220經由高速連接235與磁碟機230通信。電腦110可使用相同之連接器來形成圖1中之舊版連接115及圖2中之高速連接225。如所示,由電腦110所提供之高速連接可菊鏈連接至多個器件。在此組態中,每一高速連接225及235共用可用於電腦110之連接器處的頻寬。This figure illustrates a computer 110 that communicates with a computer or display 220 via a high speed connection 225. The computer or display 220 communicates with the disk drive 230 via a high speed connection 235. The computer 110 can use the same connector to form the legacy connection 115 of FIG. 1 and the high speed connection 225 of FIG. As shown, the high speed connection provided by computer 110 can be daisy chained to multiple devices. In this configuration, each high speed connection 225 and 235 shares the bandwidth available at the connector of computer 110.
藉由在電腦110上提供可支援圖1中之舊版連接115及圖2中之高速連接225的連接器,減少電腦110上之連接器的數目。此減小器件大小、節約金錢並減輕消費者混亂。在此實例中,電腦110與電腦或顯示器220及磁碟機230通信。在本發明之其他實施例中,可使用其他類型之器件。舉例而言,電腦110可驅動一體式電腦、第二電腦、獨立監視器、膨脹器件、磁碟陣列(raid drive)或其他類型之器件的顯示器。The number of connectors on the computer 110 is reduced by providing a connector on the computer 110 that supports the legacy connection 115 of FIG. 1 and the high speed connection 225 of FIG. This reduces device size, saves money and reduces consumer confusion. In this example, computer 110 is in communication with a computer or display 220 and disk drive 230. Other types of devices can be used in other embodiments of the invention. For example, computer 110 can drive a display of an all-in-one computer, a second computer, a stand-alone monitor, an expansion device, a raid drive, or other type of device.
本發明之實施例可在使用現有舊版連接器配置高速連接之引出線時考慮至少兩個考慮因素。第一,高速連接之不同通道中的信號可經配置,使得其不會彼此干擾。亦即,可減少高速信號之間的串擾且該等信號可被隔離。第二,用以驅動並接收新的高速信號之電路及與舊版標準相關聯之電路可被隔離以限制其間的干擾。下圖中展示一實例。Embodiments of the present invention may take into account at least two considerations when configuring an exit line for a high speed connection using an existing legacy connector. First, the signals in the different channels of the high speed connection can be configured such that they do not interfere with each other. That is, crosstalk between high speed signals can be reduced and the signals can be isolated. Second, the circuitry used to drive and receive new high speed signals and the circuitry associated with the legacy standards can be isolated to limit interference therebetween. An example is shown in the figure below.
圖3說明根據本發明之實施例的連接器之引出線。在此實例中,DisplayPort為舊版標準,其已由用於新標準(此處稱為HSIO,在本文獻中之別處稱為T29)之接針上覆。在本發明之其他實施例中,可使用其他標準。再者,此等標準中之一者或兩者可為舊版標準,或此等標準中之一者或兩者可為較新之標準。再者,儘管兩項標準在此處展示為共用連接器,但在本發明之其他實施例中,其他數目項標準可共用連接器。Figure 3 illustrates the lead wires of a connector in accordance with an embodiment of the present invention. In this example, DisplayPort is an older version of the standard that has been overlaid by a pin for the new standard (herein referred to as HSIO, referred to elsewhere as T29 in this document). In other embodiments of the invention, other criteria may be used. Furthermore, one or both of these standards may be an old standard, or one or both of these standards may be a newer standard. Moreover, although the two standards are shown here as a common connector, in other embodiments of the invention, other numbers of standards may share the connector.
在本發明之各種實施例中,該兩項標準可為單獨且無關的。在本發明之其他實施例中,其可為相關的。舉例而言,HSIO可為攜載DisplayPort資訊之高速傳信技術。亦即,DisplayPort資訊可使用HSIO信號來穿隧。HSIO亦可同時攜載其他類型之信號資訊(諸如,PCIe資訊)。以此方式,圖3中之連接器可直接攜載DisplayPort信號,或其可攜載作為HSIO信號輸送之DisplayPort資訊。應注意,在下文所描述之本發明之各種實施例中,HSIO亦稱為T29。In various embodiments of the invention, the two criteria may be separate and unrelated. In other embodiments of the invention, it may be related. For example, HSIO can be a high-speed signaling technology that carries DisplayPort information. That is, DisplayPort information can be tunneled using the HSIO signal. HSIO can also carry other types of signal information (such as PCIe information). In this way, the connector of Figure 3 can directly carry the DisplayPort signal, or it can carry DisplayPort information transmitted as HSIO signal. It should be noted that in various embodiments of the invention described below, HSIO is also referred to as T29.
在此配置中,高速輸入及輸出接針可彼此隔離。特定言之,高速接收信號可置放於接針4及接針6以及接針16及接針18上。此等信號對中之每一者可藉由為AC接地之信號隔離。舉例而言,高速接收接針4及6可藉由熱插塞偵測接針2及接地接針8隔離。類似地,高速接收接針16及18可藉由接地14及電力接針20隔離。高速傳輸接針3及接針5以及接針15及接針17可藉由接地接針1、7、13及19隔離。接地接針中之一些或全部(諸如,接針1及7)可為AC接地(與至接地之直接DC連接相反)。亦即,此等接針可經由電容器耦接至接地。此在高頻下提供接地連接,而在低頻下提供開路。此配置允許在此等接針處接收電源供應器,同時在高頻下維持接地。In this configuration, the high speed input and output pins can be isolated from each other. In particular, the high-speed receiving signal can be placed on the pin 4 and the pin 6 as well as the pin 16 and the pin 18. Each of these signal pairs can be isolated by a signal that is AC grounded. For example, the high speed receiving pins 4 and 6 can be isolated by the hot plug detecting pin 2 and the grounding pin 8. Similarly, the high speed receiving pins 16 and 18 can be isolated by the ground 14 and the power pin 20. The high speed transmission pin 3 and the pin 5 and the pin 15 and the pin 17 can be isolated by the ground pins 1, 7, 13 and 19. Some or all of the ground pins (such as pins 1 and 7) may be AC ground (as opposed to a direct DC connection to ground). That is, the pins can be coupled to ground via a capacitor. This provides a ground connection at high frequencies and an open circuit at low frequencies. This configuration allows the power supply to be received at these pins while maintaining ground at high frequencies.
在本發明之特定實施例中,纜線之第一端處的接針20連接至纜線之第二端處的接針1。此允許藉由主機器件在接針20上所提供之電力被供應至器件連接處的接針1。因為接針1經由電容器耦接至接地,所以可接收DC電力,但接針1提供AC接地。In a particular embodiment of the invention, the pin 20 at the first end of the cable is connected to the pin 1 at the second end of the cable. This allows the power supplied by the host device on the pin 20 to be supplied to the pin 1 at the device connection. Since the pin 1 is coupled to ground via a capacitor, DC power can be received, but the pin 1 provides AC ground.
亦在此配置中,在高速HSIO標準中之高速信號可與舊版DisplayPort標準之適當信號共用接針。特定言之,接針4及接針6上之高速接收信號可與DisplayPort標準中之組態信號共用接針。接針16及接針18上之高速接收信號可與DisplayPort標準中之輔助信號共用接針。接針3及接針5上之高速傳輸信號可與DisplayPort輸出信號共用接針,同樣接針15及接針17上之高速傳輸信號可與DisplayPort輸出信號共用接針。Also in this configuration, the high speed signal in the high speed HSIO standard can be shared with the appropriate signal of the old DisplayPort standard. In particular, the high-speed receive signals on pins 4 and 6 can share pins with the configuration signals in the DisplayPort standard. The high speed receive signal on pin 16 and pin 18 can share the pin with the auxiliary signal in the DisplayPort standard. The high-speed transmission signal on the pin 3 and the pin 5 can share the pin with the DisplayPort output signal, and the high-speed transmission signal on the pin 15 and the pin 17 can share the pin with the DisplayPort output signal.
再者,在本發明之各種實施例中,主動纜線可輸送順應各種標準之信號。如上文所論述,在本發明之特定實施例中,此等可稱為HSIO及DisplayPort。主動纜線可能能夠藉由偵測各種上拉電阻器或下拉電阻器之狀態來判定正使用哪些標準。此之實例可在名為用於主動纜線之電路(Circuitry for Active Cable)之同在申請中的美國專利申請案第13/ , 號(代理人檔案號碼20750P-02500US)中找到,該案以引用的方式併入。Moreover, in various embodiments of the invention, the active cable can deliver signals that conform to various standards. As discussed above, in certain embodiments of the invention, these may be referred to as HSIO and DisplayPort. The active cable may be able to determine which standards are being used by detecting the status of various pull-up or pull-down resistors. An example of this can be found in U.S. Patent Application Serial No. 13/, which is incorporated herein by reference. , Found in the number (Agency File Number 20750P-02500US), the case is incorporated by reference.
在本發明之各種實施例中,主動纜線可將各種類型之電子器件連接在一起。此等電子器件可包括主機器件及其他類型之器件。此等其他類型之器件可包括其自己之電源供應器,或其可由主機器件供電。具有其自己之電源供應器之器件可自電池、壁式插口、汽車充電器或其他供應器汲取電力。此等器件可為諸如磁碟機、監視器或其他類型之器件的器件。In various embodiments of the invention, the active cable can connect various types of electronic devices together. Such electronic devices can include host devices and other types of devices. These other types of devices may include their own power supplies, or they may be powered by host devices. Devices with their own power supplies can draw power from batteries, wall outlets, car chargers or other supplies. Such devices can be devices such as disk drives, monitors, or other types of devices.
再者,根據本發明之實施例的主機可能能夠提供較高電壓,諸如12 V或15 V。在此等情況下,更多電力可提供至第二器件而不增加最大電流。纜線中之組件可不操作於高電壓下,因此第二器件可提供較低電壓至纜線電路。再者,藉由提供用於在第二器件上產生較低電壓的電路,此電路無需包括於主機中。下圖中展示一實例。Furthermore, a host in accordance with an embodiment of the present invention may be able to provide a higher voltage, such as 12 V or 15 V. In such cases, more power can be supplied to the second device without increasing the maximum current. The components in the cable may not operate at high voltages, so the second device may provide a lower voltage to the cable circuit. Furthermore, by providing a circuit for generating a lower voltage on the second device, the circuit need not be included in the host. An example is shown in the figure below.
圖4說明根據本發明之實施例的電子系統。此圖包括經由纜線410耦接至器件490之主機480。纜線410包括連接至主機480之左插塞420,及連接至器件490之右插塞450。主機480可能能夠提供一或多個電壓至器件490及纜線410中之纜線電路兩者。主機480可提供3.3 V之較低電壓,或12伏特或15伏特之較高電壓。在本發明之其他實施例中,主機480可提供各種電壓位準至器件490及纜線410中之纜線電路。Figure 4 illustrates an electronic system in accordance with an embodiment of the present invention. This figure includes a host 480 coupled to device 490 via cable 410. Cable 410 includes a left plug 420 that is coupled to host 480 and a right plug 450 that is coupled to device 490. Host 480 may be capable of providing one or more voltages to both device 490 and the cable circuitry in cable 410. Host 480 can provide a lower voltage of 3.3 V, or a higher voltage of 12 volts or 15 volts. In other embodiments of the invention, host 480 can provide various voltage levels to device 490 and cable circuitry in cable 410.
在此特定實例中,主機480提供3.3 V至纜線410中之纜線電路及器件490。因此,主機480中之開關482提供3.3 V作為電壓V1。此電壓在電晶體N1之閘極上上拉,藉此接通電晶體N1及P1。電晶體P1提供3.3 V至纜線微控制器422及開關424。此電壓進一步接通電晶體P2之本體二極體(body diode),其將線V2上之電壓拉至2.6 V,或3.3 V減去一個二極體壓降。此電壓接通電晶體N3及P3,藉此連接線V2上之電壓至纜線微控制器452及開關454。電晶體N4及P4斷開,藉此隔離線V2上之電壓與線V1上之電壓。In this particular example, host 480 provides 3.3 V to cable circuitry and device 490 in cable 410. Thus, switch 482 in host 480 provides 3.3 V as voltage V1. This voltage is pulled up on the gate of the transistor N1, thereby turning on the transistors N1 and P1. Transistor P1 provides a 3.3 V to cable microcontroller 422 and switch 424. This voltage further turns on the body diode of transistor P2, which pulls the voltage on line V2 to 2.6 V, or 3.3 V minus a diode drop. This voltage turns on transistors N3 and P3, thereby connecting the voltage on line V2 to cable microcontroller 452 and switch 454. The transistors N4 and P4 are turned off, thereby isolating the voltage on line V2 from the voltage on line V1.
電壓V1係藉由器件490中之低壓降(low-drop-out)調節器492接收,低壓降調節器492提供電力至埠微控制器494。主機埠微控制器484接著可與纜線微控制器422及452以及埠微控制器494通信以判定用於纜線之恰當組態。在本發明之特定實施例中,主機埠微控制器484可與器件埠微控制器494一致以判定器件490是否需要較高之電力位準。若其需要,則主機埠微控制器484可與纜線微控制器422一致以判定纜線是否可支援此較高之電力位準的遞送。若器件490需要較高電力,且纜線可遞送其,則主機480可提供較高之電力位準。在本發明之另一實施例中,主機埠微控制器484可判定纜線及器件490將需要的電力之量。在一些情況下,包括一對時脈及資料復原電路或其他電路之一鏈路可能需要斷電。Voltage V1 is received by low-drop-out regulator 492 in device 490, which provides power to helium microcontroller 494. Host 埠 microcontroller 484 can then communicate with cable microcontrollers 422 and 452 and 埠 microcontroller 494 to determine the proper configuration for the cable. In a particular embodiment of the invention, host 埠 microcontroller 484 can be identical to device 埠 microcontroller 494 to determine if device 490 requires a higher power level. If desired, the host 埠 microcontroller 484 can be compliant with the cable microcontroller 422 to determine if the cable can support the delivery of this higher power level. If device 490 requires higher power and the cable can deliver it, host 480 can provide a higher power level. In another embodiment of the invention, host 埠 microcontroller 484 can determine the amount of power that cable and device 490 will require. In some cases, a link including a pair of clock and data recovery circuits or other circuits may require a power outage.
在此實例中,電源供應器496接收來自主機480之線V1上的僅3.3 V。在此電壓下,電源供應器496可處於欠電壓閉鎖狀態,且因此可斷電。在此狀態中,電源供應器496不提供電力至纜線電路。In this example, power supply 496 receives only 3.3 V on line V1 from host 480. At this voltage, the power supply 496 can be in an undervoltage lockout state and can therefore be powered down. In this state, power supply 496 does not provide power to the cable circuitry.
在此實例中,纜線插塞電路包括時脈及資料復原電路426及456。此等時脈及資料復原電路可接收並重新定時自主機480、器件490及自彼此所接收之資料。此之實例可在名為用於主動纜線之電路(Circuitry for Active Cable)之同在申請中的美國專利申請案第13/ , 號(代理人檔案號碼20750P-02500US)中找到,該案以引用的方式併入。In this example, the cable plug circuit includes clock and data recovery circuits 426 and 456. The clock and data recovery circuits can receive and retime data from the host 480, the device 490, and from each other. An example of this can be found in U.S. Patent Application Serial No. 13/, which is incorporated herein by reference. , Found in the number (Agency File Number 20750P-02500US), the case is incorporated by reference.
再者,主機480能夠提供較高電壓,諸如12 V或15 V。在此等情況下,儘管可能需要提供此較高電壓至器件490,但此較高電壓可引起纜線410之電路中的過多電力耗散,且由此發熱。因此,在本發明之各種實施例中,儘管器件490接收來自主機480之較高電壓,但器件490又提供較低電壓至纜線電路。此允許纜線電力耗散保持為低。再者,藉由提供用於在器件490上產生較低電壓之電路,此電路無需包括於主機480中。因此,在主機480無需提供此較低電壓之情況下,電路不耗損。實情為,電路僅包括於需要較高電壓之器件上。下圖中展示一實例。Again, host 480 can provide a higher voltage, such as 12 V or 15 V. In such cases, although it may be desirable to provide this higher voltage to device 490, this higher voltage may cause excessive power dissipation in the circuitry of cable 410 and thereby heat. Thus, in various embodiments of the invention, although device 490 receives a higher voltage from host 480, device 490 provides a lower voltage to cable circuit. This allows cable power dissipation to remain low. Again, this circuit need not be included in host 480 by providing circuitry for generating a lower voltage on device 490. Therefore, without the host 480 having to provide this lower voltage, the circuit is not wasted. The truth is, the circuit is only included on devices that require higher voltages. An example is shown in the figure below.
圖5說明主機580經由纜線510提供高電壓至器件590之電子系統。再者,提供高電壓至纜線510中之纜線電路可引起左插塞520及右插塞550中之過多電力耗散及組件發熱。因此,在本發明之此實施例中,器件590接收來自主機580之較高電壓,且又提供較低電壓至纜線510中之纜線電路。由主機580所提供之較高電壓或由器件590所提供之較低電壓可用以對器件590供電,對器件590中或與器件590相關聯之電池充電,或用於其他目的。FIG. 5 illustrates an electronic system in which host 580 provides a high voltage to device 590 via cable 510. Moreover, providing a high voltage to the cable circuitry in cable 510 can cause excessive power dissipation in the left plug 520 and right plug 550 and component heating. Thus, in this embodiment of the invention, device 590 receives a higher voltage from host 580 and in turn provides a lower voltage to the cable circuitry in cable 510. The higher voltage provided by host 580 or the lower voltage provided by device 590 can be used to power device 590, charge the battery in device 590 or associated with device 590, or for other purposes.
特定言之,主機580中之高電壓電力開關586提供線V1上之12 V。此12 V使分路調節器522斷開電晶體N1及P1。在器件590中藉由低壓降調節器592接收高電壓,低壓降調節器592提供較低調節電壓至埠微控制器594。由器件590所接收之較高電壓經調節至較低供應(諸如,3.3 V),並由電源供應器596提供於線V2上。此又可接通電晶體P3,其提供線V2上之電壓至纜線微控制器552及開關554。因為電晶體N1為斷開的,所以電晶體N2及P2接通,藉此將線V2上之3.3 V耦合至纜線微控制器522及開關524。In particular, the high voltage power switch 586 in the host 580 provides 12 V on line V1. This 12 V causes shunt regulator 522 to turn off transistors N1 and P1. High voltage is received by low dropout regulator 592 in device 590, and low dropout regulator 592 provides a lower regulated voltage to 埠microcontroller 594. The higher voltage received by device 590 is regulated to a lower supply (such as 3.3 V) and is provided by line 596 by power supply 596. This in turn turns on transistor P3, which provides the voltage on line V2 to cable microcontroller 552 and switch 554. Because transistor N1 is open, transistors N2 and P2 are turned on, thereby coupling 3.3 V on line V2 to cable microcontroller 522 and switch 524.
以此方式,主機580提供高電壓(12 V)至器件590。此較高電壓增加主機580可提供至器件590之電力的量。此又可減少電池充電次數。器件590又將低電壓(3.3 V)傳回至纜線510中之左插塞520及右插塞550中之纜線電路。亦即,高電壓V1不用以直接對纜線電路中之任一者供電。實情為,V1上之較高電壓係藉由電源供應器596減小至較低電壓,其提供於線V2上。此較低電壓接著對左插塞520及右插塞550中之主動電路供電。In this manner, host 580 provides a high voltage (12 V) to device 590. This higher voltage increases the amount of power that host 580 can provide to device 590. This in turn reduces the number of battery charges. Device 590 in turn transmits a low voltage (3.3 V) back to the cable circuits in left plug 520 and right plug 550 in cable 510. That is, the high voltage V1 does not have to directly supply power to any of the cable circuits. The fact is that the higher voltage on V1 is reduced to a lower voltage by power supply 596, which is provided on line V2. This lower voltage then powers the active circuitry in left plug 520 and right plug 550.
再者,在本發明之一些實施例中,主機可連接至另一主機或自供電器件。在此狀況下,需要每一主機或自供電器件對其自己之相應插塞供電。以此方式,電力無需經由纜線而發送。下圖中展示一實例。Still further, in some embodiments of the invention, the host can be connected to another host or self-powered device. In this case, each host or self-powered device is required to supply its own corresponding plug. In this way, power is not transmitted via the cable. An example is shown in the figure below.
圖6說明主機680提供電力至左插塞620且主機或自供電器件690提供電力至右插塞650之電子系統。在此實例中,主機680中之電力開關682提供線V1上之3.3 V至左插塞620。此電壓接通電晶體N1及P1,藉此提供3.3 V至纜線微控制器622及開關624。類似地,主機或自供電器件690中之電力開關692提供線V2上之3.3 V至右插塞650。此電壓接通電晶體N3及P3,藉此提供3.3 V至纜線微控制器652及開關654。6 illustrates an electronic system in which host 680 provides power to left plug 620 and host or self-powered device 690 provides power to right plug 650. In this example, power switch 682 in host 680 provides 3.3 V to left plug 620 on line V1. This voltage turns on transistors N1 and P1, thereby providing 3.3 V to cable microcontroller 622 and switch 624. Similarly, power switch 692 in host or self-powered device 690 provides a 3.3 V to right plug 650 on line V2. This voltage turns on transistors N3 and P3, thereby providing 3.3 V to cable microcontroller 652 and switch 654.
當在右插塞650連接至主機或自供電器件690之前左插塞620連接至主機680時,瞬時情況可發生。在此瞬時情況期間,線V1上之3.3 V可接通電晶體N1及P1。此可經由P2之本體二極體接通P2,藉此將線V2上之電壓帶至2.6 V。當右插塞650連接至主機或自供電器件690時,電力開關692可提供線V2上之3.3 V,藉此斷開電晶體P2。An instantaneous condition can occur when the left plug 620 is connected to the host 680 before the right plug 650 is connected to the host or self-powered device 690. During this transient condition, 3.3 V on line V1 turns on transistors N1 and P1. This turns P2 on via the body diode of P2, thereby bringing the voltage on line V2 to 2.6V. When the right plug 650 is connected to the host or self-powered device 690, the power switch 692 can provide 3.3 V on line V2, thereby disconnecting the transistor P2.
在本發明之以上實施例中,展示特定電路組態。在本發明之其他實施例中,可使用其他電路組態。此等電路可使用離散組件而形成,其可部分地整合,或其可完全整合。以下圖中展示另一特定電路組態。In the above embodiments of the invention, a particular circuit configuration is shown. In other embodiments of the invention, other circuit configurations can be used. Such circuits may be formed using discrete components, which may be partially integrated, or they may be fully integrated. Another specific circuit configuration is shown in the following figure.
圖7說明根據本發明之實施例的另一電子系統。在此等實例中,使用兩個分路調節器。使用兩個分路調節器可防止如下情形:主機及器件兩者提供高電壓,且兩個插塞將其電路連接至其各別接針1(即使在該接針上提供高電壓)。使用兩個分路調節器意謂兩個插塞中之電路可斷開連接且因此被保護免受較高電力。Figure 7 illustrates another electronic system in accordance with an embodiment of the present invention. In these examples, two shunt regulators are used. The use of two shunt regulators prevents the situation where both the host and the device provide a high voltage and the two plugs connect their circuits to their respective pins 1 (even if a high voltage is provided on the pins). The use of two shunt regulators means that the circuits in the two plugs can be disconnected and thus protected from higher power.
此圖包括經由纜線710耦接至器件790之主機780。纜線710包括連接至主機780之左插塞720,及連接至器件790之右插塞750。主機780可能能夠提供一或多個電壓至器件790及纜線710中之纜線電路兩者。主機780可提供3.3 V之較低電壓,或12伏特或15伏特之較高電壓。在本發明之其他實施例中,主機780可提供各種電壓位準至器件790及纜線710中之纜線電路。This figure includes a host 780 coupled to device 790 via cable 710. Cable 710 includes a left plug 720 that is coupled to host 780 and a right plug 750 that is coupled to device 790. Host 780 may be capable of providing one or more voltages to both device 790 and the cable circuitry in cable 710. Host 780 can provide a lower voltage of 3.3 V, or a higher voltage of 12 volts or 15 volts. In other embodiments of the invention, host 780 can provide various voltage levels to device 790 and cable circuitry in cable 710.
在此特定實例中,主機780提供3.3 V至纜線710中之纜線電路及器件790。因此,主機780中之開關782提供3.3 V作為電壓V1。此電壓在電晶體P1之閘極上上拉,藉此斷開電晶體P1並接通電晶體P2。電晶體P2提供3.3 V至纜線微控制器722及開關724。此電壓進一步接通電晶體P4之本體二極體,其將線V2上之電壓拉至2.6 V,或3.3 V減去一個二極體壓降。此電壓斷開電晶體P5並接通電晶體P6,藉此連接線V2上之電壓至纜線微控制器752及開關754。電晶體P8為斷開的,藉此隔離線V2上之電壓與線V1上之電壓。In this particular example, host 780 provides 3.3 V to cable circuitry and device 790 in cable 710. Thus, switch 782 in host 780 provides 3.3 V as voltage V1. This voltage is pulled up on the gate of the transistor P1, thereby turning off the transistor P1 and turning on the transistor P2. Transistor P2 provides a 3.3 V to cable microcontroller 722 and switch 724. This voltage further turns on the body diode of transistor P4, which pulls the voltage on line V2 to 2.6 V, or 3.3 V minus a diode drop. This voltage turns off transistor P5 and turns on transistor P6, thereby connecting the voltage on line V2 to cable microcontroller 752 and switch 754. The transistor P8 is open, thereby isolating the voltage on line V2 from the voltage on line V1.
電壓V1係藉由器件790中之低壓降調節器792接收,低壓降調節器792提供電力至埠微控制器794。主機埠微控制器784接著可與纜線微控制器722及752以及器件埠微控制器794通信以判定用於纜線之恰當組態。如前所述,主機埠微控制器784可判定是否可提供較高之電力位準,及是否可能需要將一些電路斷電。Voltage V1 is received by low dropout regulator 792 in device 790, and low dropout regulator 792 provides power to helium microcontroller 794. Host 埠 microcontroller 784 can then communicate with cable microcontrollers 722 and 752 and device 埠 microcontroller 794 to determine the proper configuration for the cable. As previously mentioned, the host 埠 microcontroller 784 can determine if a higher power level can be provided and if some circuits may need to be powered down.
在此實例中,電源供應器796接收來自主機780之線V1上的僅3.3 V。在此電壓下,電源供應器796可處於欠電壓閉鎖狀態,且因此可斷電。在此狀態中,電源供應器796不提供電力至纜線電路。In this example, power supply 796 receives only 3.3 V on line V1 from host 780. At this voltage, the power supply 796 can be in an undervoltage lockout state and can therefore be powered down. In this state, power supply 796 does not provide power to the cable circuit.
再者,主機780能夠提供較高電壓,諸如12 V或15 V。在此等情況下,儘管可能需要提供此較高電壓至器件790,但此較高電壓可引起纜線710之電路中的過多電力耗散,且由此發熱。因此,在本發明之各種實施例中,儘管器件790接收來自主機780之較高電壓,但器件790又提供較低電壓至纜線電路。此允許纜線電力耗散保持為低。再者,藉由提供用於在器件790上產生較低電壓之電路,此電路無需包括於主機780中。因此,在主機780無需提供此較低電壓之情況下,電路不耗損。實情為,電路僅包括於需要較高電壓之器件上。下圖中展示一實例。Again, host 780 can provide a higher voltage, such as 12 V or 15 V. In such cases, although it may be desirable to provide this higher voltage to device 790, this higher voltage may cause excessive power dissipation in the circuitry of cable 710 and thereby generate heat. Thus, in various embodiments of the invention, although device 790 receives a higher voltage from host 780, device 790 provides a lower voltage to cable circuit. This allows cable power dissipation to remain low. Again, this circuit need not be included in host 780 by providing circuitry for generating a lower voltage on device 790. Therefore, in the case where the host 780 does not need to provide this lower voltage, the circuit is not worn out. The truth is, the circuit is only included on devices that require higher voltages. An example is shown in the figure below.
圖8說明主機880經由纜線810提供高電壓至器件890之另一電子系統。再者,提供此高電壓至纜線810中之纜線電路可引起左插塞820及右插塞850中之過多電力耗散及組件發熱。因此,在本發明之此實施例中,器件890接收來自主機880之較高電壓,且又提供較低電壓至纜線810中之纜線電路。再者,由主機880所提供之較高電壓或由器件890所產生之較低電壓可用以對器件890供電,對器件890中或與器件890相關聯之電池充電,或用於其他目的。FIG. 8 illustrates another electronic system in which host 880 provides a high voltage via cable 810 to device 890. Moreover, providing such a high voltage to the cable circuitry in cable 810 can cause excessive power dissipation in the left plug 820 and right plug 850 and component heating. Thus, in this embodiment of the invention, device 890 receives a higher voltage from host 880 and in turn provides a lower voltage to the cable circuitry in cable 810. Moreover, the higher voltage provided by host 880 or the lower voltage generated by device 890 can be used to power device 890, charge the battery in device 890 or associated with device 890, or for other purposes.
特定言之,主機880中之高電壓電力開關886提供線V1上之12 V。此12 V使分路調節器812接通電晶體P1,其斷開電晶體P2。在器件890中藉由低壓降調節器892接收高電壓,低壓降調節器892提供較低之經調節電壓至埠微控制器894。由器件890所接收之較高電壓調節至較低供應(諸如,3.3 V),並由電源供應器896提供於線V2上。此又可接通電晶體P6,其提供線V2上之電壓至纜線微控制器852及開關854。因為電晶體N1及P3為斷開的,所以電晶體P4接通,藉此將線V2上之3.3 V耦合至纜線微控制器822及開關824。In particular, the high voltage power switch 886 in the host 880 provides 12 V on line V1. This 12 V causes shunt regulator 812 to turn on transistor P1, which turns off transistor P2. In device 890, a high voltage is received by low dropout regulator 892, which provides a lower regulated voltage to 埠microcontroller 894. The higher voltage received by device 890 is regulated to a lower supply (such as 3.3 V) and is provided by power supply 896 on line V2. This in turn turns on transistor P6, which provides the voltage on line V2 to cable microcontroller 852 and switch 854. Because transistors N1 and P3 are open, transistor P4 is turned "on", thereby coupling 3.3 V on line V2 to cable microcontroller 822 and switch 824.
以此方式,主機880提供高電壓(12 V)至器件890。此較高電壓增加主機880可提供至器件890之電力的量。此又可減少電池充電次數。器件890又將低電壓(3.3 V)傳回至纜線810中之左插塞820及右插塞850中的纜線電路。亦即,高電壓V1不用以直接對此等纜線電路供電。實情為,V1上之較高電壓係藉由電源供應器896減小至較低電壓,其提供於線V2上。此較低電壓接著對左插塞820及右插塞850中之主動電路供電。In this manner, host 880 provides a high voltage (12 V) to device 890. This higher voltage increases the amount of power that host 880 can provide to device 890. This in turn reduces the number of battery charges. Device 890 in turn transmits a low voltage (3.3 V) back to the cable circuits in left plug 820 and right plug 850 in cable 810. That is, the high voltage V1 does not have to be directly powered by these cable circuits. The fact is that the higher voltage on V1 is reduced to a lower voltage by power supply 896, which is provided on line V2. This lower voltage then powers the active circuitry in left plug 820 and right plug 850.
再者,若藉由主機880及器件890兩者將高電壓提供於各別接針20上,則額外分路調節器814及864可分別斷開器件P4及P8。此又保護纜線電路以免連接至高電壓。Moreover, if a high voltage is supplied to the respective pins 20 by both the host 880 and the device 890, the additional shunt regulators 814 and 864 can disconnect the devices P4 and P8, respectively. This in turn protects the cable circuitry from connecting to high voltages.
再者,在本發明之一些實施例中,主機可連接至另一主機或自供電器件。在此狀況下,需要每一主機或自供電器件對其自己之相應插塞供電。以此方式,電力無需經由纜線而發送。下圖中展示一實例。Still further, in some embodiments of the invention, the host can be connected to another host or self-powered device. In this case, each host or self-powered device is required to supply its own corresponding plug. In this way, power is not transmitted via the cable. An example is shown in the figure below.
圖9說明主機980提供電力至左插塞920且主機或自供電器件990提供電力至右插塞950之另一電子系統。在此實例中,主機980中之電力開關982提供線V1上之3.3 V至左插塞920。此電壓接通電晶體P1,藉此提供3.3 V至纜線微控制器922及開關924。類似地,在主機或自供電器件990中之電力開關992提供線V2上之3.3 V至右插塞950。此電壓接通電晶體P6,藉此提供3.3 V至纜線微控制器952及開關954。9 illustrates another electronic system in which host 980 provides power to left plug 920 and host or self-powered device 990 provides power to right plug 950. In this example, power switch 982 in host 980 provides 3.3 V to left plug 920 on line V1. This voltage turns on transistor P1, thereby providing 3.3 V to cable microcontroller 922 and switch 924. Similarly, power switch 992 in host or self-powered device 990 provides a 3.3 V to right plug 950 on line V2. This voltage turns on transistor P6, thereby providing 3.3 V to cable microcontroller 952 and switch 954.
當在右插塞950連接至主機或自供電器件990之前左插塞920連接至主機980時,瞬時情況可發生。在此瞬時情況期間,線V1上之3.3 V可接通電晶體P1。此可經由P4之本體二極體接通P4,藉此將線V2上之電壓帶至2.6 V。當右插塞950連接至主機或自供電器件990時,電力開關992可提供線V2上之3.3 V,藉此斷開電晶體P4並減小其本體二極體電流。An instantaneous condition can occur when the left plug 920 is connected to the host 980 before the right plug 950 is connected to the host or self-powered device 990. During this transient condition, 3.3 V on line V1 can turn on transistor P1. This turns P4 on via the body diode of P4, thereby bringing the voltage on line V2 to 2.6V. When the right plug 950 is connected to the host or self-powered device 990, the power switch 992 can provide 3.3 V on line V2, thereby turning off the transistor P4 and reducing its body diode current.
再者,在本發明之各種實施例中,可使用各種電路組態。在此及其他實施例中,可使用分路調節器。此等分路調節器可接收在以上實例中由電阻器分壓器(resistor divider)所提供的電壓。比較此所接收電壓與內部參考電壓。若所接收電壓高於參考電壓,則輸出電晶體可導電;若所接收電壓低於參考電壓,則輸出電晶體可斷開。舉例而言,在圖7中,線V1上之電壓僅為3.3 V,且所接收電壓小於參考電壓。在此狀況下,分路調節器中之輸出電晶體斷開,且P1斷開,此接通P2。在圖8中,線V1上之電壓為12 V,且所接收電壓高於參考電壓。在此狀況下,分路調節器中之輸出電晶體接通,且P1接通,此斷開P2。Moreover, various circuit configurations can be used in various embodiments of the invention. In this and other embodiments, a shunt regulator can be used. These shunt regulators can receive the voltage provided by the resistor divider in the above example. Compare this received voltage with the internal reference voltage. If the received voltage is higher than the reference voltage, the output transistor can be electrically conductive; if the received voltage is lower than the reference voltage, the output transistor can be turned off. For example, in Figure 7, the voltage on line V1 is only 3.3 V and the received voltage is less than the reference voltage. In this case, the output transistor in the shunt regulator is turned off and P1 is turned off, which turns P2 on. In Figure 8, the voltage on line V1 is 12 V and the received voltage is higher than the reference voltage. In this case, the output transistor in the shunt regulator is turned "on" and P1 is turned "on", which turns off P2.
在使用以上組態之情況下,若所接收電力在臨限值以下,則在匯點器件(sink device)並非自供電之情況下,所接收電力用以對兩個插塞供電。若所接收電力在該臨限值以上,則所接收電力由匯點器件使用以產生電壓來對插塞中之主動電路供電。若匯點器件為自供電的,則每一器件可對其自己之插塞供電。在本發明之各種實施例中,可使用各種數目個此等調節器,且其可置放於各種位置中。In the case of the above configuration, if the received power is below the threshold, the received power is used to power the two plugs if the sink device is not self-powered. If the received power is above the threshold, the received power is used by the sink device to generate a voltage to power the active circuitry in the plug. If the sink device is self-powered, each device can power its own plug. In various embodiments of the invention, various numbers of such adjusters can be used and can be placed in a variety of positions.
在本發明之此等及其他實施例中,可包括滯後以減少顫動及振盪可能性。舉例而言,電阻器Rhy已添加至圖7至圖9中之電路以在進入各種狀態之情況下提供滯後至以上臨限值。In this and other embodiments of the invention, hysteresis may be included to reduce the likelihood of chattering and oscillation. For example, resistor Rhy has been added to the circuits of Figures 7-9 to provide hysteresis to the above thresholds when entering various states.
本發明之實施例可包括用以接收及重新定時資料之電路。舉例而言,一或多個時脈及資料復原電路926及956可包括於插塞920及950中之任一者或兩者中。左插塞920中之時脈及資料復原電路926可接收來自主機980之信號且將其提供至右插塞950中的時脈及資料復原電路956。類似地,右插塞950中之時脈及資料復原電路956可接收來自器件990之信號且將其提供至左插塞920中的時脈及資料復原電路926。在本發明之各種實施例中,可藉由時脈及資料復原電路926及956提供一個或兩個雙向訊務單工通道(lane)。此之實例可在名為用於主動纜線之電路(Circuitry for Active Cable)之同在申請中的美國專利申請案第13/ , 號(代理人檔案號碼20750P-02500US)中找到,該案以引用的方式併入。Embodiments of the invention may include circuitry for receiving and retiming data. For example, one or more clock and data recovery circuits 926 and 956 can be included in either or both of plugs 920 and 950. The clock and data recovery circuit 926 in the left plug 920 can receive signals from the host 980 and provide them to the clock and data recovery circuit 956 in the right plug 950. Similarly, the clock and data recovery circuit 956 in the right plug 950 can receive the signal from the device 990 and provide it to the clock and data recovery circuit 926 in the left plug 920. In various embodiments of the invention, one or two two-way traffic simplex lanes may be provided by clock and data recovery circuits 926 and 956. An example of this can be found in U.S. Patent Application Serial No. 13/, which is incorporated herein by reference. , Found in the number (Agency File Number 20750P-02500US), the case is incorporated by reference.
在此等實例中,開關展示為耦接至每一插塞中之兩個時脈及資料復原電路中的每一者。在本發明之其他實施例中,僅一開關可連接至兩個時脈及資料復原電路。當一時脈及資料復原電路不需要時,其可經由軟體而非實體開關來斷電。在本發明之其他實施例中,可使用其他電力管理技術。In these examples, the switch is shown coupled to each of the two clock and data recovery circuits in each plug. In other embodiments of the invention, only one switch can be connected to two clock and data recovery circuits. When a clock and data recovery circuit is not needed, it can be powered down via a software rather than a physical switch. In other embodiments of the invention, other power management techniques may be used.
在本發明之各種實施例中,使用埠微控制器984及994以及纜線微控制器922及952來控制纜線電路之組態中的大部分。可使用在LSR2P TX及LSP2R RX接針上發源之信號將此等微控制器彼此連接。此等接針可稱為LSx匯流排。In various embodiments of the invention, 埠 microcontrollers 984 and 994 and cable microcontrollers 922 and 952 are used to control most of the configuration of the cable circuits. The microcontrollers can be connected to each other using signals originating on the LSR2P TX and LSP2R RX pins. These pins can be referred to as LSx bus bars.
此匯流排可輸送斷開與未使用之通道或單工通道相關聯之電路、判定連接之存在及可針對較高電壓而協商的信號。舉例而言,連接之存在可藉由LSP2R RX接針上具有弱(1 MΩ)下拉電阻器及LSR2P TX接針上具有較強(10 KΩ)上拉電阻器的每一端點(主機或器件)來促進。因為纜線以端至端方式交叉,所以每一端可感測其P2R信號以判定遠側是否存在被供電之主機或器件,且在纜線未完全連接時繼續允許電力管理。再者,若器件要求較高電壓由主機提供,則器件可請求使用LSx匯流排增加電壓。This bus bar can deliver a circuit that disconnects an unused channel or a simplex channel, determines the presence of a connection, and can negotiate a signal for a higher voltage. For example, the connection can exist through the LSP2R RX pin with a weak (1 MΩ) pull-down resistor and each end of the LSR2P TX pin with a strong (10 KΩ) pull-up resistor (host or device) To promote. Because the cables cross in an end-to-end fashion, each end can sense its P2R signal to determine if there is a powered host or device on the far side and continue to allow power management when the cable is not fully connected. Furthermore, if the device requires a higher voltage to be provided by the host, the device can request an increase in voltage using the LSx bus.
再者,在本發明之各種實施例中,纜線微控制器可與經由纜線通信之主機及器件中之埠微控制器通信。在本發明之特定實施例中,第一器件中之埠微控制器可直接與嵌入於該第一器件中之插塞中的纜線微控制器以及附接至遠端插塞之遠端器件中的埠微控制器通信。可藉由遠端器件中之埠微控制器的「彈回」訊息與遠程或遠端插塞進行進一步通信。Moreover, in various embodiments of the invention, the cable microcontroller can communicate with the host and the microcontroller in the device via cable communication. In a particular embodiment of the invention, the chirp microcontroller in the first device can be directly coupled to the cable microcontroller embedded in the plug in the first device and the remote device attached to the distal plug The 埠 microcontroller communicates. Further communication with the remote or remote plug can be accomplished by a "bounce back" message from the top microcontroller in the remote device.
在埠微控制器與纜線微控制器之間的此等通信可採取各種形式。傳統上,互連在每一端處被固定,很少有機會發現改良之性能或靈活實施。因此,本發明之實施例提供此通信能力,使得(例如)纜線可與主機或器件共用關於其特徵之資訊,且該主機或器件可利用此等特徵。Such communication between the helium microcontroller and the cable microcontroller can take a variety of forms. Traditionally, interconnects have been fixed at each end, with few opportunities to discover improved performance or flexible implementation. Accordingly, embodiments of the present invention provide this communication capability such that, for example, a cable can share information about its characteristics with a host or device, and the host or device can utilize such features.
在其他實例中,在各種埠微控制器與纜線微控制器之間的此等通信在本質上可為診斷。此等診斷通信可輔助藉由終端使用者或其他使用者進行故障隔離,此可允許迅速矯正問題並可將注意力集中在引起故障之器件上。此等通信亦可在測試及製造方面有用。其亦可用以最佳化用於電力節約之組態,例如,未使用之通道可被斷電,低電力遠端器件可藉由主機供電,使得器件不需要至壁式電源插座之連接。再者,可監視由遠端器件所消耗之電力,且可按需要而啟用電力增加(或減少)。其亦可允許器件繼續操作而不管各種損害。其亦可使得能夠使用銅或其他導體,或纜線自身中之光纖。此之另外實例可在名為用於主動纜線之電路(Circuitry for Active Cable)之同在申請中的美國專利申請案第13/ , 號(代理人檔案號碼20750P-02500US)中找到,該案以引用的方式併入。In other examples, such communication between various helium microcontrollers and cable microcontrollers may be diagnostic in nature. Such diagnostic communications may assist in fault isolation by the end user or other users, which may allow for rapid correction of problems and focus on the device that caused the failure. These communications can also be useful in testing and manufacturing. It can also be used to optimize configurations for power savings, for example, unused channels can be powered down, and low power remote devices can be powered by the host so that the device does not require a connection to a wall outlet. Again, the power consumed by the remote device can be monitored and power up (or reduced) can be enabled as needed. It also allows the device to continue to operate regardless of various damage. It may also enable the use of copper or other conductors, or fibers in the cable itself. A further example of this can be found in U.S. Patent Application Serial No. 13/, which is incorporated herein by reference. , Found in the number (Agency File Number 20750P-02500US), the case is incorporated by reference.
在本發明之此等實施例中,纜線微控制器922及952控制開關924及954,開關924及954連接或斷開連接至及來自時脈及資料復原電路926及956之電力。纜線微控制器922及952以及時脈及資料復原電路926及956消耗電力,其可隨時間逝去而將電池放電或以其他方式耗損電力。因此,當不需要此等電路時,其可被斷電。舉例而言,若僅使用纜線910中之一資料鏈路,則一組時脈及資料復原電路926及956可藉由纜線微控制器922及952而停用。再者,若無資料自主機982傳送至器件990,則左插塞920及右插塞950中之電路可斷開以節約電力。下圖中展示一實例。In such embodiments of the invention, cable microcontrollers 922 and 952 control switches 924 and 954 that connect or disconnect power to and from clock and data recovery circuits 926 and 956. Cable microcontrollers 922 and 952 and clock and data recovery circuits 926 and 956 consume power that can discharge or otherwise dissipate power over time. Therefore, when such circuits are not needed, they can be powered down. For example, if only one of the data links in cable 910 is used, then a set of clock and data recovery circuits 926 and 956 can be deactivated by cable microcontrollers 922 and 952. Moreover, if no data is transferred from the host 982 to the device 990, the circuits in the left plug 920 and the right plug 950 can be disconnected to conserve power. An example is shown in the figure below.
圖10說明根據本發明之實施例的節省電力之方法。在通電、重設或其他開始事件1010之後,在動作1020中判定在時間T1內是否無經由纜線之資料活動。若無活動,則可在動作1030中進入低電力睡眠狀態。在動作1040中,判定(例如)在低速或高速輸入上是否存在資料邊緣。若存在資料邊緣,則在動作1050中可退出睡眠狀態且可開始載入纜線之操作所需的程式碼。必要時,此邊緣可為瞬時雜訊。此邊緣可能不繼之以任何其他活動。在此狀況下,在動作1030中可重新進入睡眠狀態。若在時間T2內存在活動(動作1060),則可在動作1070中載入程式碼之剩餘部分,及/或恢復正常操作。Figure 10 illustrates a method of conserving power in accordance with an embodiment of the present invention. After power up, reset, or other start event 1010, it is determined in act 1020 whether there is no data activity via the cable during time T1. If there is no activity, a low power sleep state can be entered in act 1030. In act 1040, it is determined, for example, whether there is a data edge on the low speed or high speed input. If there is a data edge, the code required to exit the sleep state and can begin to load the cable in action 1050. This edge can be transient noise if necessary. This edge may not be followed by any other activity. In this situation, the sleep state can be re-entered in act 1030. If there is activity at time T2 (act 1060), the remainder of the code can be loaded in action 1070 and/or normal operation resumed.
再者,符合本發明之實施例的連接器及纜線可能能夠處置兩個或兩個以上信號協定。在本發明之特定實施例中,兩個協定為DisplayPort及高速協定HSIO,高速協定HSIO在以下實例中稱為T29。因此,當使用符合本發明之實施例的纜線將器件連接在一起時,藉由埠微控制器(諸如,埠微控制器984)進行關於使用哪一協定之判定。下圖中展示進行此判定之方式的一實例。Furthermore, connectors and cables consistent with embodiments of the present invention may be capable of handling two or more signal protocols. In a particular embodiment of the invention, the two agreements are DisplayPort and the high speed protocol HSIO, and the high speed protocol HSIO is referred to as T29 in the following example. Thus, when the devices are connected together using a cable in accordance with an embodiment of the present invention, a determination as to which protocol to use is made by a 埠 microcontroller, such as 埠 microcontroller 984. An example of the way this decision is made is shown in the figure below.
圖11說明根據本發明之實施例的可在組態資料鏈路時使用之狀態機。在本發明之特定實施例中,此等判定可藉由埠微控制器(諸如,埠微控制器984或其他微控制器或狀態機)進行。Figure 11 illustrates a state machine that can be used in configuring a data link in accordance with an embodiment of the present invention. In a particular embodiment of the invention, such determinations may be made by a 埠 microcontroller such as a 埠microcontroller 984 or other microcontroller or state machine.
在通電或重設條件之後,進入重設狀態1100。一般而言,藉由熱插塞偵測線HPD上之高上拉來偵測DisplayPort鏈路之存在。因此,若熱插塞偵測被感測為高,則進入連接狀態1110。此時,判定高狀態是否被維持持續一段時間(例如,100毫秒)。此判定具有去除HPD線上之電壓抖動之效應。若此高狀態被維持,則可進入DisplayPort狀態1112。若熱插塞偵測線上存在低信號,則重新進入重設階段1100。埠微控制器可保持處於DisplayPort狀態1112,直至熱插塞偵測返回為低為止。在此狀況下,進入斷開連接狀態1114。After the power is turned on or the condition is reset, the reset state 1100 is entered. In general, the presence of a DisplayPort link is detected by a high pullup on the hot plug detection line HPD. Therefore, if the hot plug detection is sensed as high, then the connected state 1110 is entered. At this time, it is determined whether the high state is maintained for a certain period of time (for example, 100 milliseconds). This decision has the effect of removing voltage jitter on the HPD line. If this high state is maintained, then the DisplayPort state 1112 can be entered. If there is a low signal on the hot plug detection line, the reset phase 1100 is re-entered. The microcontroller can remain in DisplayPort state 1112 until the hot plug detection returns low. In this case, the disconnected state 1114 is entered.
斷開連接狀態1114提供一滯後量以防止DisplayPort狀態1112過早地退出。舉例而言,DisplayPort經由HPD接針提供第二中斷。此等中斷可為HPD上持續小於1毫秒之高-低-高脈衝。此等中斷不應視為斷開連接,且提供此滯後(10毫秒延遲)防止斷開連接。因此,若熱插塞偵測持續10毫秒保持為低,則重新進入重設階段1100,否則重新進入DisplayPort狀態1112。Disconnected state 1114 provides a hysteresis amount to prevent DisplayPort state 1112 from exiting prematurely. For example, the DisplayPort provides a second interrupt via the HPD pin. These interruptions can be high-low-high pulses that last less than 1 millisecond on the HPD. These interrupts should not be considered disconnected and this hysteresis (10 millisecond delay) is provided to prevent disconnection. Therefore, if the hot plug detection remains low for 10 milliseconds, the reset phase 1100 is re-entered, otherwise the DisplayPort state 1112 is re-entered.
再者,一般而言,T29連接之存在係藉由組態接針CONFIG2(別處識別為CFG2)為高來判定。當此成立時,退出重設狀態1100且進入T29連接狀態1120。可藉由將唯一ID自輸入端傳遞至輸出端而進入迴送狀態1122。若CONFIG2返回為低,則可進入T29斷開連接狀態1124。如同斷開連接狀態1114一樣,T29斷開連接狀態1124提供一滯後量,並防止過早退出T29連接狀態。Furthermore, in general, the presence of the T29 connection is determined by configuring the pin CONFIG2 (identified as CFG2 elsewhere) to be high. When this is established, the reset state 1100 is exited and the T29 connection state 1120 is entered. The loopback state 1122 can be entered by passing a unique ID from the input to the output. If CONFIG2 returns low, then the T29 disconnected state 1124 can be entered. As with disconnected state 1114, T29 disconnected state 1124 provides a hysteresis and prevents premature exit from the T29 connected state.
一旦在T29連接狀態1120中,若接收到資料,則進入纜線狀態1126。一旦進入纜線狀態1126,若再次接收到資料,則進入T29狀態1128。如所示,若CONFIG2返回為低,則可退出纜線狀態1126及T29狀態1128。Once in T29 connection state 1120, if a message is received, cable status 1126 is entered. Once the cable state 1126 is entered, if the data is received again, the T29 state 1128 is entered. As shown, if CONFIG2 returns low, the cable state 1126 and T29 state 1128 can be exited.
如上文所描述,在本發明之各種實施例中,可進入各種睡眠狀態。舉例而言,可接收指示埠微控制器預備睡眠或預備進入靜止狀態之命令,藉此進入狀態1158或1160。As described above, various sleep states are accessible in various embodiments of the invention. For example, a command may be received indicating that the microcontroller is ready to sleep or is ready to enter a quiescent state, thereby entering state 1158 or 1160.
在以上實例中,隨著所供應電力自低電壓向上斜升至高電壓,可因為已越過分路臨限值而存在圖8中之P2斷開之時間,但器件890仍不具有足夠電壓來提供3.3 V至其接針20。結果,纜線「電壓不足(browns-out)」,且CONFIG2可降壓。可能不需要將此偵測為斷開連接。因此,一旦串列通信已成功地進行,則CONFIG2變得無關且僅UART中止可偵測為斷開連接。下圖中展示一實例。In the above example, as the supplied power ramps up from a low voltage to a high voltage, there may be a time when P2 is off in Figure 8 because the shunt threshold has been crossed, but device 890 still does not have sufficient voltage to provide 3.3 V to its pin 20. As a result, the cable "browns-out" and the CONFIG2 can be stepped down. It may not be necessary to detect this as a disconnect. Therefore, once the serial communication has been successfully performed, CONFIG2 becomes irrelevant and only the UART abort can be detected as disconnected. An example is shown in the figure below.
圖12說明根據本發明之實施例的可在組態資料鏈路時使用之狀態機。在本發明之特定實施例中,此等判定可藉由埠微控制器(諸如,主機埠微控制器984或其他微控制器或狀態機)來進行。Figure 12 illustrates a state machine that can be used in configuring a data link in accordance with an embodiment of the present invention. In a particular embodiment of the invention, such determinations may be made by a 埠 microcontroller such as a host 埠 microcontroller 984 or other microcontroller or state machine.
在通電或重設條件之後,進入重設狀態1200。一般而言,藉由熱插塞偵測線HPD上之高上拉來偵測DisplayPort鏈路之存在。因此,若熱插塞偵測被感測為高,則進入連接狀態1210。此時,判定高狀態是否被維持持續一段時間(例如,100毫秒)。此判定具有去除HPD線上之電壓抖動之效應。若此高狀態被維持,則可進入DisplayPort狀態1212。若熱插塞偵測線上存在低信號,則重新進入重試階段1200。埠微控制器可保持處於DisplayPort狀態1212,直至熱插塞偵測返回為低為止。在此狀況下,進入斷開連接狀態1214。After the power is turned on or the condition is reset, the reset state 1200 is entered. In general, the presence of a DisplayPort link is detected by a high pullup on the hot plug detection line HPD. Therefore, if the hot plug detection is sensed as high, then the connected state 1210 is entered. At this time, it is determined whether the high state is maintained for a certain period of time (for example, 100 milliseconds). This decision has the effect of removing voltage jitter on the HPD line. If this high state is maintained, then the DisplayPort state 1212 can be entered. If there is a low signal on the hot plug detection line, the retry phase 1200 is re-entered. The microcontroller can remain in DisplayPort state 1212 until the hot plug detection returns low. In this state, the disconnected state 1214 is entered.
斷開連接狀態1214提供一滯後量以防止DisplayPort狀態1212過早地退出。舉例而言,DisplayPort經由HPD接針提供第二中斷。此等中斷可為HPD上持續小於1毫秒之高-低-高脈衝。此等中斷不應視為斷開連接,且提供此滯後(10毫秒延遲)防止斷開連接。因此,若熱插塞偵測持續10毫秒保持為低,則重新進入重設階段1200,否則重新進入DisplayPort狀態1212。Disconnected state 1214 provides a hysteresis amount to prevent DisplayPort state 1212 from exiting prematurely. For example, the DisplayPort provides a second interrupt via the HPD pin. These interruptions can be high-low-high pulses that last less than 1 millisecond on the HPD. These interrupts should not be considered disconnected and this hysteresis (10 millisecond delay) is provided to prevent disconnection. Therefore, if the hot plug detection remains low for 10 milliseconds, the reset phase 1200 is re-entered, otherwise the DisplayPort state 1212 is re-entered.
再者,一般而言,T29(或TBT)連接之存在係藉由組態接針CONFIG2(別處識別為CFG2)為高來判定。當此成立時,退出重設狀態1200且進入TBT(別處識別為T29)連接狀態1220。可藉由將唯一ID自輸入端傳遞至輸出端而進入迴送狀態1222。若CONFIG2返回為低,則可進入TBT斷開連接狀態1224。如同斷開連接狀態1214一樣,TBT斷開連接狀態1224提供一滯後量,並防止過早退出TBT連接狀態。Furthermore, in general, the presence of a T29 (or TBT) connection is determined by configuring the pin CONFIG2 (identified as CFG2 elsewhere) to be high. When this is established, the reset state 1200 is exited and the TBT (identified as T29 elsewhere) connection state 1220 is entered. The loopback state 1222 can be entered by passing a unique ID from the input to the output. If CONFIG2 returns low, the TBT disconnected state 1224 can be entered. As with the disconnected state 1214, the TBT disconnected state 1224 provides a hysteresis and prevents premature exit from the TBT connected state.
一旦在TBT連接狀態1120中,若接收到資料,則進入纜線狀態1226。一旦進入纜線狀態1226,若再次接收到資料,則進入TBT狀態1228。一旦進入TBT狀態1228,則其藉由UART中止而退出,且進入中止狀態1240。再者,在本發明之此實施例中,TBT狀態1228並非藉由CONFIG2上之上拉電阻器的損失而退出。若在5毫秒中未接收到資料,則進入纜線狀態1226。若接收到資料,則可重新進入TBT狀態1228。再者,在此實施例中,一或多個單工通道可能未經啟用以用於TBT資料傳輸。在此狀況下,當在纜線狀態1226中時,可進入等待電力狀態1242直至啟用單工通道或通道為止。Once in the TBT connection state 1120, if a message is received, the cable state 1226 is entered. Once in the cable state 1226, if the data is received again, the TBT state 1228 is entered. Once in TBT state 1228, it exits by UART abort and enters abort state 1240. Moreover, in this embodiment of the invention, the TBT state 1228 is not exited by the loss of the pull-up resistor on CONFIG2. If no data is received within 5 milliseconds, the cable state 1226 is entered. If the data is received, the TBT state 1228 can be re-entered. Again, in this embodiment, one or more simplex channels may not be enabled for TBT data transmission. In this situation, while in cable state 1226, wait for power state 1242 can be entered until a simplex channel or channel is enabled.
再者,在本發明之各種實施例中,可進入各種睡眠狀態。舉例而言,可接收指示埠微控制器預備睡眠或預備進入靜止狀態之命令,藉此進入狀態1258。Moreover, in various embodiments of the invention, various sleep states are accessible. For example, a command may be received indicating that the microcontroller is ready to sleep or is ready to enter a quiescent state, thereby entering state 1258.
已出於說明及描述之目的而呈現本發明之實施例的以上描述。其並不意欲為詳盡的或將本發明限於所描述之精確形式,且許多修改及變化依據以上教示係可能的。選擇並描述實施例,以便最好地解釋本發明之原理及其實際應用,以藉此使其他熟習此項技術者能夠在各種實施例中並與適合於所涵蓋之特定用途的各種修改一起最好地利用本發明。因此,將瞭解,本發明並不意欲涵蓋在以下申請專利範圍之範疇內之所有修改及等效物。The above description of the embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention. The embodiment was chosen and described in order to best explain the embodiments of the invention and the embodiments of the invention The invention is well utilized. Therefore, it is to be understood that the invention is not intended to
1...接地接針1. . . Grounding pin
2...熱插塞偵測接針2. . . Hot plug detection pin
3...高速傳輸接針3. . . High speed transmission pin
4...高速接收接針4. . . High speed receiving pin
5...高速傳輸接針5. . . High speed transmission pin
6...高速接收接針6. . . High speed receiving pin
7...接地接針7. . . Grounding pin
8...接地接針8. . . Grounding pin
9...接針9. . . Pin
10...接針10. . . Pin
11...接針11. . . Pin
12...接針12. . . Pin
13...接地接針13. . . Grounding pin
14...接地接針14. . . Grounding pin
15...高速傳輸接針15. . . High speed transmission pin
16...高速接收接針16. . . High speed receiving pin
17...高速傳輸接針17. . . High speed transmission pin
18...高速接收接針18. . . High speed receiving pin
19...接地接針19. . . Grounding pin
20...電力接針20. . . Power pin
110...電腦110. . . computer
115...舊版連接115. . . Legacy connection
120...舊版顯示器120. . . Legacy display
220...電腦或顯示器220. . . Computer or display
225...高速連接225. . . High speed connection
230...磁碟機230. . . Disk drive
235...高速連接235. . . High speed connection
410...纜線410. . . Cable
420...左插塞420. . . Left plug
422...纜線微控制器422. . . Cable microcontroller
424...開關424. . . switch
426...時脈及資料復原電路426. . . Clock and data recovery circuit
450...右插塞450. . . Right plug
452...纜線微控制器452. . . Cable microcontroller
454...開關454. . . switch
456...時脈及資料復原電路456. . . Clock and data recovery circuit
480...主機480. . . Host
482...開關482. . . switch
484...主機埠微控制器484. . . Host 埠 microcontroller
486...HV埠電力開關486. . . HV埠 power switch
490...器件490. . . Device
492...低壓降調節器492. . . Low pressure drop regulator
494...器件埠微控制器494. . . Device and microcontroller
496...電源供應器496. . . Power Supplier
510...纜線510. . . Cable
520...左插塞520. . . Left plug
522...纜線微控制器/分路調節器522. . . Cable Microcontroller / Shunt Regulator
524...開關524. . . switch
526...時脈及資料復原電路526. . . Clock and data recovery circuit
550...右插塞550. . . Right plug
552...纜線微控制器552. . . Cable microcontroller
554...開關554. . . switch
556...時脈及資料復原電路556. . . Clock and data recovery circuit
580...主機580. . . Host
582...DP埠電力開關582. . . DP埠 power switch
584...埠微控制器584. . .埠microcontroller
586...HV埠電力開關/高電壓電力開關586. . . HV埠 power switch / high voltage power switch
590...器件590. . . Device
592...低壓降調節器592. . . Low pressure drop regulator
594...器件埠微控制器594. . . Device and microcontroller
596...電源供應器596. . . Power Supplier
610...纜線610. . . Cable
620...左插塞620. . . Left plug
622...纜線微控制器622. . . Cable microcontroller
624...開關624. . . switch
626...時脈及資料復原電路626. . . Clock and data recovery circuit
650...右插塞650. . . Right plug
652...纜線微控制器652. . . Cable microcontroller
654...開關654. . . switch
656...時脈及資料復原電路656. . . Clock and data recovery circuit
680...主機680. . . Host
682...電力開關682. . . Power switch
684...埠微控制器684. . .埠microcontroller
686...HV埠電力開關686. . . HV埠 power switch
690...主機或自供電器件690. . . Host or self-powered device
692...電力開關692. . . Power switch
694...埠微控制器694. . .埠microcontroller
696...HV埠電力開關696. . . HV埠 power switch
710...纜線710. . . Cable
720...左插塞720. . . Left plug
722...纜線微控制器722. . . Cable microcontroller
724...開關724. . . switch
726...時脈及資料復原電路726. . . Clock and data recovery circuit
750...右插塞750. . . Right plug
752...纜線微控制器752. . . Cable microcontroller
754...開關754. . . switch
756...時脈及資料復原電路756. . . Clock and data recovery circuit
780...主機780. . . Host
782...開關782. . . switch
784...主機埠微控制器784. . . Host 埠 microcontroller
786...HV埠電力開關786. . . HV埠 power switch
790...器件790. . . Device
792...低壓降調節器792. . . Low pressure drop regulator
794...器件埠微控制器794. . . Device and microcontroller
796...電源供應器796. . . Power Supplier
810...纜線810. . . Cable
812...分路調節器812. . . Shunt regulator
814...分路調節器814. . . Shunt regulator
820...左插塞820. . . Left plug
822...纜線微控制器822. . . Cable microcontroller
824...開關824. . . switch
826...時脈及資料復原電路826. . . Clock and data recovery circuit
850...右插塞850. . . Right plug
852...纜線微控制器852. . . Cable microcontroller
854...開關854. . . switch
856...時脈及資料復原電路856. . . Clock and data recovery circuit
864...分路調節器864. . . Shunt regulator
880...主機880. . . Host
882...DP埠電力開關882. . . DP埠 power switch
884...埠微控制器884. . .埠microcontroller
886...HV埠電力開關/高電壓電力開關886. . . HV埠 power switch / high voltage power switch
890...器件890. . . Device
892...低壓降調節器892. . . Low pressure drop regulator
894...埠微控制器894. . .埠microcontroller
896...電源供應器896. . . Power Supplier
910...纜線910. . . Cable
920...左插塞920. . . Left plug
922...纜線微控制器922. . . Cable microcontroller
924...開關924. . . switch
926...時脈及資料復原電路926. . . Clock and data recovery circuit
950...右插塞950. . . Right plug
952...纜線微控制器952. . . Cable microcontroller
954...開關954. . . switch
956...時脈及資料復原電路956. . . Clock and data recovery circuit
980...主機980. . . Host
982...電力開關982. . . Power switch
984...埠微控制器984. . .埠microcontroller
986...HV埠電力開關986. . . HV埠 power switch
990...主機或自供電器件990. . . Host or self-powered device
992...電力開關992. . . Power switch
994...埠微控制器994. . .埠microcontroller
996...HV埠電力開關996. . . HV埠 power switch
1100...重設狀態/重設階段1100. . . Reset state/reset phase
1110...連接狀態1110. . . Connection Status
1112...DisplayPort狀態1112. . . DisplayPort status
1114...斷開連接狀態1114. . . Disconnected state
1120...T29連接狀態1120. . . T29 connection status
1122...迴送狀態1122. . . Return status
1124...T29斷開連接狀態1124. . . T29 disconnected state
1126...纜線狀態1126. . . Cable status
1128...T29狀態1128. . . T29 status
1158...PtoS狀態1158. . . PtoS status
1160...PtoQ狀態1160. . . PtoQ status
1162...Q狀態1162. . . Q state
1200...重設狀態/重設階段1200. . . Reset state/reset phase
1210...連接狀態1210. . . Connection Status
1212...DisplayPort狀態1212. . . DisplayPort status
1214...斷開連接狀態1214. . . Disconnected state
1220...TBT連接狀態1220. . . TBT connection status
1222...迴送狀態1222. . . Return status
1224...TBT斷開連接狀態1224. . . TBT disconnected state
1226...纜線狀態1226. . . Cable status
1228...TBT狀態1228. . . TBT status
1240...中止狀態1240. . . Abort state
1242...等待電力狀態1242. . . Waiting for power status
1258...PtoS狀態1258. . . PtoS status
N1...電晶體N1. . . Transistor
N2...電晶體N2. . . Transistor
N3...電晶體N3. . . Transistor
N4...電晶體N4. . . Transistor
P1...電晶體P1. . . Transistor
P2...電晶體P2. . . Transistor
P3...電晶體P3. . . Transistor
P4...電晶體P4. . . Transistor
P5...電晶體P5. . . Transistor
P6...電晶體P6. . . Transistor
P7...電晶體P7. . . Transistor
P8...電晶體P8. . . Transistor
V1...線/電壓V1. . . Line/voltage
V2...線V2. . . line
圖1說明可藉由本發明之實施例的併入而改良之舊版系統;Figure 1 illustrates an older version of the system that can be modified by the incorporation of embodiments of the present invention;
圖2說明根據本發明之實施例的電腦系統;2 illustrates a computer system in accordance with an embodiment of the present invention;
圖3說明根據本發明之實施例的連接器之引出線;Figure 3 illustrates a lead wire of a connector in accordance with an embodiment of the present invention;
圖4說明根據本發明之實施例的電子系統;Figure 4 illustrates an electronic system in accordance with an embodiment of the present invention;
圖5說明主機經由纜線提供高電壓至器件之電子系統;Figure 5 illustrates an electronic system in which a host provides a high voltage to a device via a cable;
圖6說明主機提供電力至左插塞且主機或自供電器件提供電力至右插塞之電子系統;Figure 6 illustrates an electronic system in which the host provides power to the left plug and the host or self-powered device provides power to the right plug;
圖7說明根據本發明之實施例的另一電子系統;Figure 7 illustrates another electronic system in accordance with an embodiment of the present invention;
圖8說明主機經由纜線提供高電壓至器件之另一電子系統;Figure 8 illustrates another electronic system in which the host provides a high voltage to the device via a cable;
圖9說明主機提供電力至左插塞且主機或自供電器件提供電力至右插塞之另一電子系統;Figure 9 illustrates another electronic system in which the host provides power to the left plug and the host or self-powered device provides power to the right plug;
圖10說明根據本發明之實施例的節省電力之方法;Figure 10 illustrates a method of conserving power in accordance with an embodiment of the present invention;
圖11說明根據本發明之實施例的可在組態資料鏈路時使用之狀態機;及Figure 11 illustrates a state machine that can be used in configuring a data link in accordance with an embodiment of the present invention;
圖12說明根據本發明之實施例的可在組態資料鏈路時使用之另一狀態機。Figure 12 illustrates another state machine that can be used in configuring a data link in accordance with an embodiment of the present invention.
710...纜線710. . . Cable
720...左插塞720. . . Left plug
722...纜線微控制器722. . . Cable microcontroller
724...開關724. . . switch
726...時脈及資料復原電路726. . . Clock and data recovery circuit
750...右插塞750. . . Right plug
752...纜線微控制器752. . . Cable microcontroller
754...開關754. . . switch
756...時脈及資料復原電路756. . . Clock and data recovery circuit
780...主機780. . . Host
782...開關782. . . switch
784...主機埠微控制器784. . . Host 埠 microcontroller
786...HV埠電力開關786. . . HV埠 power switch
790...器件790. . . Device
792...低壓降調節器792. . . Low pressure drop regulator
794...器件埠微控制器794. . . Device and microcontroller
796...電源供應器796. . . Power Supplier
N1...電晶體N1. . . Transistor
N2...電晶體N2. . . Transistor
P1...電晶體P1. . . Transistor
P2...電晶體P2. . . Transistor
P3...電晶體P3. . . Transistor
P4...電晶體P4. . . Transistor
P5...電晶體P5. . . Transistor
P6...電晶體P6. . . Transistor
P7...電晶體P7. . . Transistor
P8...電晶體P8. . . Transistor
V1...線/電壓V1. . . Line/voltage
V2...線V2. . . line
Claims (18)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US36043210P | 2010-06-30 | 2010-06-30 | |
| US201161446027P | 2011-02-23 | 2011-02-23 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201230001A TW201230001A (en) | 2012-07-16 |
| TWI449025B true TWI449025B (en) | 2014-08-11 |
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Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW100123233A TWI449025B (en) | 2010-06-30 | 2011-06-30 | Power distribution inside cable |
| TW100123236A TWI450263B (en) | 2010-06-30 | 2011-06-30 | Circuitry for active cable |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW100123236A TWI450263B (en) | 2010-06-30 | 2011-06-30 | Circuitry for active cable |
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| TW (2) | TWI449025B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI684129B (en) * | 2018-01-12 | 2020-02-01 | 大陸商龍迅半導體(合肥)股份有限公司 | A software upgrading method, system and an active dp cable |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200627322A (en) * | 2005-01-28 | 2006-08-01 | Chien-Chuan Chu | Apparatus contains 2-wire power line and server/client circuits with each end, substituting for power transmitting line of traffic lights |
| TW200838085A (en) * | 2006-11-30 | 2008-09-16 | Electro Scient Ind Inc | Passive station power distribution for cable reduction |
| TW200909825A (en) * | 2007-08-20 | 2009-03-01 | Ernst Klees | Cable |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002318647A (en) * | 2001-04-19 | 2002-10-31 | Mitsubishi Electric Corp | Detecting device and detecting method thereof |
| US7162731B2 (en) * | 2002-02-07 | 2007-01-09 | Advent Networks, Inc. | Radio frequency characterization of cable plant and corresponding calibration of communication equipment communicating via the cable plant |
| US6969270B2 (en) * | 2003-06-26 | 2005-11-29 | Intel Corporation | Integrated socket and cable connector |
-
2011
- 2011-06-30 TW TW100123233A patent/TWI449025B/en active
- 2011-06-30 TW TW100123236A patent/TWI450263B/en active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200627322A (en) * | 2005-01-28 | 2006-08-01 | Chien-Chuan Chu | Apparatus contains 2-wire power line and server/client circuits with each end, substituting for power transmitting line of traffic lights |
| TW200838085A (en) * | 2006-11-30 | 2008-09-16 | Electro Scient Ind Inc | Passive station power distribution for cable reduction |
| TW200909825A (en) * | 2007-08-20 | 2009-03-01 | Ernst Klees | Cable |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201230001A (en) | 2012-07-16 |
| TW201230002A (en) | 2012-07-16 |
| TWI450263B (en) | 2014-08-21 |
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