TW201230002A - Circuitry for active cable - Google Patents

Abstract

Circuits, methods, and apparatus that allow signals that are compliant with multiple standards to share a common connector on an electronic device. An exemplary embodiment of the present invention provides a connector that provides signals compatible with a legacy standard in one mode and a newer standard in another mode.

Description

201230002 VI. INSTRUCTIONS: This application claims US Provisional Patent Application No. 61/3 60,432, filed on June 30, 2010, and US Provisional Patent Application No. 61/446,027, filed on February 23, 2011. US Patent Application No. 13/1—No. 1 (with the name of the Power Distribution Inside Cable) (Attorney's File Number 2〇75〇p_ 025〇OOUS) ) 'These cases are incorporated by reference. [Prior Art]

Electronic devices often include connectors that provide power and data signals that can be shared with other devices. This design is compliant-standard, making electronic devices reliable. Various Universal Serial Bus (USB), Peripheral Component Interconnect (PCIe) and DiSplayP〇rt (DP) standards are just a few examples. Whenever necessary, the standard for using these connectors is replaced by newer standards. The result 'multiple connectors that provide similar functions are often included on the electronic device. For example, many current televisions include inputs for hdmi, s video, component video, and RC A jacks. The inclusion of such connectors increases device size, complexity, and cost. Moreover, the inclusion of several options can confuse and frustrate consumers as they attempt to determine the best way to configure a particular system. If a connector can provide more than one standard signal, some of this confusion can be reduced. For example, if the connector can provide signals for both the legacy and newer standards, the number of connected states on the electronic device can be reduced. This makes the device smaller and simpler. Flower 157272.doc 201230002 is less expensive. In addition to this would be helpful, it is very difficult to implement. For example, a circuit associated with a standard can interfere with circuitry associated with another standard. This becomes even more difficult when the data rate is high' because the reflections caused by unused circuitry and terminal mismatch damage the performance of the circuit being used. For example, newer and faster standards can share theft with older, slower standards. Circuitry necessary for older standards can cause reflections and terminal mismatches for newer and faster standard circuits, thereby degrading system performance. Therefore, there is a need for circuits, methods and apparatus that allow various standards to share a common connector. SUMMARY OF THE INVENTION Accordingly, embodiments of the present invention provide circuits, methods, and apparatus that allow for a common connector on a shared electronic benefit device that conforms to multiple standards. Exemplary embodiments of the present invention can provide a connector that provides signals that are compatible with older standards in one mode and newer standards in another mode. Usually, the old standard is slower and the newer standard is faster, but this may not always be true. In an exemplary embodiment of the invention, the pins for the newer standards can be configured to achieve at least two purposes. First, it can be configured to reduce crosstalk and interference in itself. This can be achieved by placing a number of differential differential signal paths between them. Second, the circuit can be added to minimize interference from the circuit used for the sale standard. This can be done by reducing reflection and impedance mismatch. 157272.doc 201230002 The exemplary embodiment of the present invention is capable of providing information such as 1 and having various features and providing more == in the exemplary implementation of the present invention, and the newer standard 1 2: Whether or not it is with-the old standard or the more power-reading pass can be done by sensing the first device of the voltage or impedance raised by the second device. In various embodiments of the invention, when two devices in communication are capable of communicating with a new standard, the standard can be used by the two components. At - Ο

The standard can be used by both devices if the device can only operate with the old standard. Embodiments of the present invention may provide circuitry for isolating an unused circuit for a standard from an operating circuit for another standard. In a particular example, a resistor, a PiN diode, a multiplexer, "other components or circuits can be used to isolate the two transmitter circuits from each other. Light-duplex capacitors and inductors can be used as DC blocking and AC filters to isolate the circuit. Various embodiments of the invention may be combined with one or more of these and other features described herein. A better understanding of the nature and advantages of the present invention can be obtained by reference to the accompanying claims. [Embodiment] Figure 1 illustrates an older system that can be improved by the incorporation of embodiments of the present invention. This figure illustrates the electricity month έ 11 11 that communicates with the old display 12 via the old version Π5. In a particular embodiment of the invention, the legacy connection 115 is a DisplayPort connection, but in other embodiments of the invention, other connections may be used. In this figure, the 'connection 115' is shown as a legacy connection. In other embodiments of the invention 157272.doc 201230002, the connection 115 can also be a novel connection. Moreover, although the computer is shown as being in communication with display 120, other types of connections may be modified by the incorporation of embodiments of the present invention. For example, the connection can be provided between the portable media player and the display, between the computer and the portable media player, or between other types of benefits. In various embodiments of the invention, computer no, display 12(), and other devices shown or discussed may be fabricated by Apple Inc. (Cupertin(R), Calif. Furthermore, computer 110 may be required to be able to drive legacy displays (such as display 120) or any newer computer, display or other type of device. Typically, this requires the addition of another connector on the computer 110. This may be undesirable because of the complexity, cost, and size of adding a computer. The addition of another connector can also increase consumer confusion. Thus, embodiments of the present invention may provide newer connections using the same connectors as the old version. An example is shown in the figure below. 2 illustrates a computer system in accordance with an embodiment of the present invention. This figure is shown for illustrative purposes in conjunction with other figures, and does not limit the scope of the embodiments or claims of the invention. This figure illustrates a computer 110 that communicates with a computer or display 22 via a high speed connection 225. The computer or display 220 communicates with the disk drive 23 via a high speed connection 235. The computer m can (4) the same connector to form the old version connection 1^15 in Fig. i and the two speed connection 225 in Fig. 2. As shown, the idle connection provided by the computer (4) can be daisy-chained to multiple devices. In this configuration, each high speed connection 225 and 235 shares the bandwidth available at the connector of the computer (4). The computer is equipped with a connector that supports the old version in the figure ιΐ5 and the speed connection 225 in Figure 2 I57272.doc 201230002, reducing the computer! The number of connectors on the 10th. This reduces device size, saves money and reduces consumer confusion. In this example, computer 110 is in communication with computer or display 220 and disk drive 230. Other types of devices can be used in other embodiments of the invention. For example, the computer 110 can drive an integrated computer, a second computer, an independent monitor, an expansion device, a raid drive, or other type of device display. ^ Embodiments of the present invention can take into account at least two considerations when configuring an exit line for a high speed connection using an existing legacy connector. First, the signals in the different channels of the high speed connection can be configured such that they do not interfere with each other. That is, crosstalk between high speed signals can be reduced and the signals can be isolated. Second, the circuitry used to drive and receive new high speed signals and the circuitry associated with the legacy standards can be isolated to limit interference therebetween. An example is shown in the figure below. Figure 3 illustrates the lead wires of a connector in accordance with an embodiment of the present invention. In this example, DlsPlayp〇rt is the old standard, which has been overlaid by the pin for the new standard. This new standard can be referred to as T29, but is generally identified as HSIO elsewhere in this document. In other embodiments of the invention, other criteria may be used. Furthermore, one or both of these standards may be the old standard, or both of them may be newer standards. Moreover, although the two criteria are not shown here as a common connector, in other embodiments of the invention, other numbers of standards may share the connector. In various embodiments of the invention, the two criteria may be: In other embodiments of the invention, it may be related. For example: σ ’ HSIO can be a high-speed signaling technology that carries Displayp〇rt information. Also 157272.doc 201230002 ie 'DisplayP〇rt information can be tunneled using the HSI0 signal. HSIO can also carry other types of signal information (such as pcie information). In this way, the connector of Figure 3 can directly carry the Displayp〇rt signal, or it can carry DiSplayport information transmitted as HSIO signal. It should be noted that in various embodiments of the invention described below, HSI is also referred to as T29. In this configuration, the high speed input and output pins can be isolated from each other. In particular, the south speed receiving signal can be placed on the pin 4 and the pin 6 as well as the pin 16 and the pin 18. Each of these signal pairs can be isolated by a signal that is Ac grounded. For example, the high speed receiving pins 4 and 6 can be isolated by the hot plug detecting pin 2 and the grounding pin 8. Similarly, the high speed receiving pins 16 and 18 can be isolated by ground 14 and power pin 20. The high speed transmission pin 3 and the pin $ and the pin 15 and the pin 17 can be isolated by the ground pins 7, 7, 13 and 19. Some or all of the ground pins (such as pins 7 and 7) can be ac grounded (as opposed to a direct DC connection to ground). That is, the pins can be coupled to ground via a capacitor. This provides a ground connection at high frequencies and an open circuit at low frequencies. This configuration allows the power supply to be received at these pins while maintaining ground at high frequencies. In a particular embodiment of the invention 'the pin 2' at the first end of the cable is connected to the pin at the second end of the cable. This allows the power supplied by the host device on the pin 20 to be supplied to the pin header at the device connection. Since the pin 1 is coupled to ground via a capacitor, DC power can be received, but the pin 1 provides AC ground. ^ High-speed signals can be used with the old ones. The pins are also used in this configuration to share the pins in the appropriate signal of the DisPIayport standard in the high-speed HSIO standard. 157272.doc 201230002 4 and the speedy reception on the pin 6 can be shared with the configuration signal in the DjSpiayp〇rt standard. The high speed receive signal on pin 16 and pin 18 can share the pin with the auxiliary signal in the DisplayPon standard. The idle transmission signal on the pin 3 and the pin 5 can share the pin with the DisplayPort output signal, and the high-speed transmission signal on the pin 15 and the pin π can share the pin with the Displayp〇rt output signal. Because these connectors can support the use of 〇13{)1叮? 〇1^ or 1181〇 standard device' so there are at least four possible group states when the two devices are in communication with each other. For example, a DisplayPort host device can communicate with a DisplayP〇rt device or a HSIO device. Furthermore, the HSI〇 host device can communicate with a Dispiayp〇rt device or another HSIO device. Therefore, devices that are compatible with the newer HSI(R) standards may be able to determine which type of device they are communicating with. Once the configuration is known, the device can be configured appropriately. An example is shown in the figure below. Figure 4 illustrates circuitry and methods used in determining the type of device in communication with one another in accordance with an embodiment of the present invention. In line 41, the DisplayP〇rt q source or host is communicating with the DisplayPort sink or endpoint.

The DisplayPort source or host provides pull-down resistors on configuration pins CFG1 and CFG2. In this example, the pull-down resistors are shown as being i-sized, but this may vary in accordance with embodiments of the present invention. The DispiayP〇rt source or host is connected to the DisplayPort sink or endpoint via a passive cable. The DisplayPort sink or endpoint can operate as a dp device. In line 420, the DisplayPort source or host communicates with the HSI0 sink or endpoint. In this particular embodiment of the invention, the HSI0 sink or endpoint will not operate under these conditions 'but in other embodiments of the invention, when the 157272.doc 201230002 HSIO sink or endpoint is a display, the HSIO sink A point or endpoint can act as a DisplayPort sink or endpoint. In line 430, the cable adapter is connected to the DisplayPort source or host. The cable adapter has a pull-up resistor on the configuration pin CFG2 that is much smaller than the source or main pull-down resistor in the main unit. Therefore, the voltage on the configuration pin CFG2 is pulled high. Cable adapters provide signals to sinks or endpoints of the HDMI or DVI type. In line 440, the HSIO source or host communicates with the DisplayPort sink or endpoint via a passive cable. The HSIO source or host has pull-down resistors on the configuration pins CFG1 and CFG2. In this example, the pull-down resistors have a value of 1 Meg, but other sizes of resistors can be used in accordance with embodiments of the present invention. In this case, the HSIO source or host does not detect the pull-up resistor on the configuration pin CFG2, and therefore the HSIO source or host operates as a DisplayPort device. In row 450, the HSIO source or host communicates with the HSIO sink or endpoint. In this configuration, an active cable is required between the HSIO source or host and the HSIO sink or endpoint. The active cable has a 100 K pull-up resistor on the configuration pin CFG2, which provides a high voltage on pin CFG2. Both the HSIO source or host and the HSIO sink or endpoint detect this level and operate as an HSIO device. In line 460, the cable adapter is connected to the HSIO source or host. The cable adapter has a pull-up resistor on the configuration pin CFG2 that is much smaller than the source or host pull-down resistor. Therefore, the voltage on the configuration pin CFG2 is pulled high. The cable adapter provides signals to the HDMI or DVI type of Meeting Point 157272.doc -10- 201230002 or endpoint. In the various implementations of (4), it is necessary to increase the level of power provided by the source or host and the sink or endpoint. In the present invention, ‘this is implemented using an LSx bus, as in the other embodiment of the present invention, this is by way of example. f 本发(10) provides the cable pull resistor to the second cap::: configuration pin only brother this line is provided by the HSIO source or the host and the Η崎点桃朴朴 run to provide a small current junction pin

G to detect. If the dust remains low, the pull-down resistor is small, and if the resistance of the high-power-mode resistor is high, the resulting dust will be 咼' and the high-voltage mode will not be enabled. In various implementations of the invention, it is desirable to exit this high power mode in some cases in order to protect the connected components. Therefore, if the cable is pulled, the power is removed from the device or other conditions occur, and the high power phase can be exited. In a particular embodiment of the invention, the low power state may include providing a supply voltage of 3.3 volts, and the high power state may include providing a supply voltage of volts. In various embodiments of the invention, such voltages may vary and may also vary depending on various conditions, such as the amount of line loss. To further save power, the cable can enter sleep mode once an inactivity cycle has been detected. Furthermore, active cables may be required to support high speed standards. The cable may have the ability to retime the data at each of its ends to provide readily recoverable information by the HSIO source or host and the HSIO Meeting Point or Endpoint. An example of this fiber line is shown in the figure below. Figure 5 illustrates an active cable in accordance with an embodiment of the present invention. For simplicity 157272.doc •11 · 201230002 See, only the circuits associated with high speed operation are shown. This cable includes two main plugs 500 and 505' on each end of the cable 507. Each active plug includes a dual clock and data recovery circuit for retiming data. Specifically, the active plug 500 provides high speed transmission k number ' on the pin 3 and the pin 5 and receives high speed signals on the pin 4 and the pin 6. The line microcontroller 520 can be used to configure the clock and data recovery circuits 5 1 and 530 ° in the active plug 500. Similarly, the active plug 505 provides high speed transmission signals on the pins 3 and 5, and A high speed signal is received on the pin 4 and the pin 6. Cable microcontroller 550 can be used to configure clock and data recovery circuits 54A and 56A. The clock and data recovery circuitry provides and receives signals in a variety of formats. For example, such circuits can include optical receivers and transmitters such that cable 507 becomes a mixture of optical fibers and electrical leads. In various embodiments of the invention, the clock and data recovery circuitry may use equalizer circuitry, buffers, emphasis and de-emphasis circuitry (and, where appropriate, may include a loopback path for diagnostic purposes. For example The output of cDr 5 can be connected as an input to the CDR 53〇, and the output of the *CDR 54〇 can be the input to the CDR 56. This loopback path allows the cerebral palsy device to transmit the transmission when the error & The location of the error. This loopback path can also be used in training or quasi-route 4, as discussed below. In other embodiments, the context is 9 for the purpose of self-communication in end-to-end mode. Other features included include eye size measurement. ° In various embodiments of the invention, the cable can be configured. In the specific caution & /, column of the present invention, the cable microcontroller 52A can be used to configure the cable 157272.doc -12- 201230002 the circuit in the plug 500' and the cable can be used Controller 550 configures the circuitry in cable plug 505. In other embodiments of the invention, other circuits may be used to configure either or both of plugs 500 and 5〇5. In this particular embodiment of the invention, the operational parameters, modes, and other aspects and characteristics of the plug circuit can be configured. Information for this configuration can include parameters for control, diagnostics, testing, configuration, circuit monitoring, and other parameters. The ability to configure the cable in this manner allows the cable to adapt to new hosts and devices when the cable is used in a variety of system applications.资讯 Information about the type of cable, identification of the dealer, and other identifying information can be obtained from the host or device and mirror. This exchange of information can be used to properly configure and drive the circuitry in the host or device and cable. In this particular embodiment of the invention, the configuration and identification information can be read from the cable and written to the cable using the LSx < § on the pin 9 and the pin 11, but in the other aspect of the invention In other embodiments, other signal pins can be used. In various embodiments of the invention, the cable microcontroller 52 and the 〇 〇 can be changed, reconfigured, upgraded or updated. "This code can be encrypted for the Queen's reasons. Furthermore, the information provided during code change, reconfiguration, or update can be encrypted. Also, various embodiments of the present invention can communicate with a 埠 microcontroller in a device (not shown) via a cable. In the present invention, the 埠 microcontroller in the first device can directly interact with the line microcontroller embedded in the plug in the first piece and the remote device attached to the far 2 plug. (4) 璋 Microcontroller communication. The 157272.doc -13· 201230002 one-step communication can be performed by the “bounce back” message of the remote device and the remote or remote plug. This communication between the 埠 microcontroller and the slow-wire microcontroller can be fixed at each end with a variety of open-ended interconnections, with few opportunities to find improved performance or flexible implementation. Thus, embodiments of the present invention provide this communication capability' such that, for example, a stencil can be shared with a host or device with respect to its features' and the host or device can utilize such features. : In his case, such an overnight connection between various 埠 microcontrollers and a wired microcontroller can be diagnostic in nature. Such diagnostic communications can aid in fault isolation by the end user or other users, which can allow rapid green problems and focus attention on the device that caused the fault. These communications can also be useful in testing and manufacturing. It can also be used to optimize power savings. For example, unused channels can be powered down, and low power remote devices can be powered by the host so that the device does not require a connection to a wall outlet. Furthermore, the power consumed by the remote device can be monitored and the power increase (or reduction) can be enabled as needed. It also allows the device to continue to operate regardless of various impairments. It can also enable the use of copper or other conductors, or the cable itself. {') Further, in various embodiments of the invention, the cable may provide pull-up resistors on the configuration pins CFG1 and CFG2, and the device attached to the cable may be provided on its LSR2PTX pin. Pull-up resistor. (The pull-up resistor on the LSR2pTx pin can be attributed to the intersection of these lines in the cable by the remote device on its LSP2R RX pin, as shown). The pull-up resistor on CFG2 allows the device to determine that the strap is attached, even when there is no remote device. In a particular embodiment of the invention, when the thin wire is present and the 157272.doc -14-201230002 has no remote device, the nearby device can communicate with the cable microcontroller in its plug, but may not be able to plug into the remote end The cable microcontroller in the plug communicates because there is no remote device to bounce back the message. These various pull-up resistors can be used to provide other features in various embodiments of the invention. For example, in some embodiments of the invention, it can be used to detect when a host device is disconnected from one or more devices. For example, when the host device is powered down, it may be necessary for the host device to provide a power down signal to one or more devices. However, the host can disconnect the 〇 connection before it can send this signal. In this case, the pull-up resistor on the LSR2PTX-free pin can be detected by the device and used by the device as an indication that it should be powered down.

Specifically, the host device can enable its pull-up resistor on its LSR2PTX while the device pulls its pull-up resistor on its LSR2PTX low. If the device knows the pull-up resistor on its LSP2R RX pin, it knows that it is connected to the host device. It can then enable the pull-up resistor on the LSR2PTX on each of its turns to inform the daisy-chain device that there is a host connected somewhere upstream. In this way, when the host is removed, the LSR2PTX 上 pull-up resistor is removed and the device pulls its LSR2PTX pull-up resistor low again, thereby notifying the daisy-chain device host that it has been disconnected. As shown in this figure, the power received on the pin 20 at a connector is provided at the pin 1 of the remote connector. This prevents the power supplies of the devices connected to each end of the cable from competing with each other. The fact is that the power on the pin 20 of the first connector is supplied to the second connector on the pin 1. In the example cable of Figure 5, a single data path is shown in each direction. In other embodiments of the invention, two or more letters 157272.doc -15-201230002 may be included. An example β is shown in the following figure. Figure 6 illustrates an active cable in accordance with an embodiment of the present invention. Again, only the circuits associated with the high speed path are shown for simplicity. In this example, additional clock and data recovery circuits 615 and 635 have been added to the active plug 6 and the clock and data recovery circuits 645 and 665 have been added to the active plug 6〇5. In this and other embodiments of the invention, the circuitry in the plug can be powered by one or both of the devices connected by the cable. For example, a host device connected to the plug 600 can provide power for the plugs 6A and 6〇5 and the host connected to the plug 605. In other examples, the benefit connected to plug 605 can receive a high voltage from a host connected to plug 6 that provides power to plugs 600 and 605. In still other examples, a host connected to plug 600 can provide power to plug 6A, and a device connected to plug 6〇5 can provide power to plug 605. In the specific example of the 匕 can be in the power distribution inside the cable (Power Distributi〇n Inside in the application of the United States special case file 13/-, - (proxy file number 2〇75〇P Found in 〇25〇〇〇US), the case is incorporated by reference. Furthermore, embodiments of the present invention allow the Us that share the pins between the two standards to not interfere with each other. Thus, the implementation of the present invention The circuit components are used to help isolate the signal path. The example is shown in the following figure. Figures 7A-7C illustrate a circuit that can use alpha to allow common pins from two different standard signal paths to share the connector. The circuits may be located in or associated with the connector receptacle, the connector insert, or both. The HSIO output can be output with the Dlspiayp〇rt in Figure 7Α. Shared pin. In this case 157272.doc -16- 201230002, the two outputs can be AC coupled via a capacitor to provide DC isolation from each other. The device can be connected to the connector via a resistor network as shown Needle. This resistor The network degrades the signal level by 6 dB, but provides ^ dB isolation. In Figure 7B, the high speed input and configuration inputs share the connector pins. In this case, the high speed receive path can be coupled via a gossip The DC voltage on the configuration pin provides isolation. The configuration pins can be isolated via resistors. Additional capacitors can be included to provide further filtering, as shown. In other embodiments of the invention, the configuration pins It can be directly pure to the connector pin. In Figure 7C, the high speed input can share the pin with the auxiliary input. Furthermore, the high speed input can be AC coupled to provide 〇 (:: blocking. The auxiliary pin can be isolated via the inductor The inductor blocks AC signals (such as high-speed signals in 7〇1^1?1^ to 1〇Gbps) while allowing 〇(: or low-frequency signals (such as signals at ) MHz or lower) to pass Furthermore, additional capacitors can be included to provide further filtering as shown. Again, the continuation input can be coupled via slaves as shown.

Q Figure 8A and Figure 8B illustrate an alternative circuit that can be used to allow common pins of the connector from two different standard signal paths. In various embodiments of the invention, the circuits may be located in or associated with the connector receptacle, the connector rear entry, or both. In Figure 8Α, the tendon output can be compared to DispUyp. Read the shared pin. In this example, the two outputs can be coupled from each other via capacitors to provide DC isolation from each other. Capacitors (4) and (2) can be coupled to the connector pins via piN diodes D1 and D2. 157272.doc -17- 201230002 In particular, when the high-speed output is active, the high-speed bias signal HSBIAS is active, driving the buffer phantom output high. This makes

The PiN diode (1) is biased on and connects the capacitor 〇 to the connector pin. The driver takes care of the capacitor. And the diode 〇1 drives the output signal to the connector pin. When the DisplayPort output is active, the Dispiayp〇r^ dust signal DPBIAS is the wire, which drives the output of the buffer to high. This biases diode D2 so that it turns "on" and connects the output of capacitor c2 to the connector pin. Driving HB2 can then drive the signal to the connector pins via capacitor 〇 and diode D2. When the capture output is active, care should be taken to avoid reflections through the DisplayP〇rt path that can interfere with the output signal as a connector pin. For this reason, an embodiment of the present invention may include an additional pad P1 between the capacitor 〇 and the diode 〇 2 as shown. This pad P1 can be formed by a resistor type network or other suitable attenuator. When the high speed output is active, the signal at the connector pin can pass through the diode D2 (which is turned off) and then through the pad P1 and capacitor C2 'by the output of the DisplayPon buffer B2 (which is turned off) Appeared at the place. Although at this time, the splayP〇rt driver B2 is disconnected, a signal can be reflected at its output, and the sub-forward travels forward through the capacitor C2, the pad P1, and the diode 〇2, thereby appearing at the connector pin. And interfere with the desired signal. In a particular embodiment of the invention, the disconnected diode D2 provides approximately 6 dB of attenuation to the return signal. The pad ρι provides an additional 4 fading, while the D1SplayP〇rt snubber B2 provides an additional 1 〇 signal reduction for the 157272.doc -18- 201230002 for its reflected signal and forward it. As the signal travels forward, it again encounters the lining_ and the diode 02' and is again attenuated by it. In this way, the reflected signal passes through the pad P1 twice and is thereby attenuated twice. When the DisPlayPort output is active, the pad 扪 attenuates the signal, but only decays once. Thus, in various embodiments of the invention, the Displayp 〇rt buffer B2 has an increased drive strength to account for the loss due to the liner. In a particular embodiment of the invention, the high speed output is approximately twice as fast as the Displayp〇rt output. In this case, the spacer (such as ρι) need not be in the high speed transmission path, but it may be included. In various examples, such as Figure 8A, the signal path is shown as being single-ended for clarity. In various embodiments of the invention, the signal path can be single ended or differential. In Figure 8B, the high speed input can share the pin with the auxiliary input. As mentioned before, 'high-speed input can be capacitor (:1 and human (: coupled to provide Dc barrier. Auxiliary input pin can be isolated via inductor L1, the inductor can block the Ac k number while allowing the DC signal to pass. Extra capacitor C2 can be included to provide further filtering, as shown. As previously described, the chirp signal path can be AC-coupled via capacitor C3, as shown. In some embodiments of the invention, the auxiliary signal can be an I2C signal. In this case, the loading caused by the input resistance of capacitor C1 and buffer B1 may be sufficient to overload the driver providing the I2C signal and transmit the signal in the I2C signal.

Caused an error. Thus, embodiments of the invention may include a piN diode D1 as shown. This pin diode can be used to isolate capacitor C1 when a capacitor is not needed. 157272.doc -19· 201230002 Specifically, when an I2C signal is received, the bias signal HSBIAS can be inactive (low), which drives the output of buffer B2 low. This in turn disconnects the diode D1, thereby isolating the I2C signal from the capacitor C1. The multiplexer Ml can select the I2c line. Similarly, HSBIAS can be low again when an AUX signal is received, which isolates capacitor C1 from the AUX line. The multiplexer can select the 仏 路径 path, which can be AC coupled via capacitor C3 again. When receiving a high speed signal, HSBIAS can be active (high), thereby outputting buffer B2. The drive is high. The multiplexer 可选择ι selects resistor R3, which provides a return path from the current provided by D1 from the output of buffer B2. This turns on the diode 01 and couples the connector pins to the battery C1 for reception of high speed signals. Various displays may include dedicated mirrors attached as part of the display. These may be referred to as cable cables. Cables can be used with Displayportg or for HSIO monitors, as well as other types of monitors. Again, these cables can be driven by a DisplayPort or HSIO source. Therefore, it is required that such devices be able to determine what they are connected to so that they can properly configure themselves. An example of this is shown in the image below. Figure 9 illustrates the circuitry and method used by the device in determining what type of device it is connected to. In line 910, the DisplayPort source or host communicates with the DisplayPort sink or endpoint. Furthermore, the configuration pins cfgi and CFG2 are pulled down. The cable can be a passive cable and the Displayp〇rt sink or endpoint can operate as a DisplayPort device. 157272.doc -20- 201230002 In line 920, the DisplayPort source or host communicates with the HSIO Meeting Point or Endpoint. Because the sink or endpoint is an HSIO device, the cable is active. However, because the source or host is a DisplayPort device, the in-line winding can operate in bypass mode to conserve power. That is, the included clock and data recovery circuitry can be inactive. Because the HSIO sink or endpoint does not detect a pull-up resistor on the LSx pin (which can be an LSR2P TX pin), it can operate in DisplayPort mode. HSIO Meeting Point can also drive CFG2 low. Ο In line 930, the source or host is a HSIO device, and the sink or endpoint is

DisplayPort device. The HSIO source or host provides pull-down resistors on the CFG1 and CFG2 lines. In this example, the pull-down resistor has a value of 1 Meg, but other resistors may be used in accordance with embodiments of the present invention. The HSIO source or host determines that the voltage on the configuration pin CFG2 is low (ie, there is no pull-up resistor) and CFG1 is also low (hence, the cable is not a connector). Therefore, the HSIO source or host operates in DisplayPort mode. In line 940, the HSIO source or host communicates with the HSIO sink or endpoint. As mentioned earlier, the HSIO source or host provides the pull-up resistors on the LSx pins and the pull-up resistors on the configuration pins CFG 1 and CFG2. The HSIO sink or endpoint detects the pullup resistor on the LSx pin and therefore operates as a HSIO device. In this example, the sink or display can provide a 100 K pull-up resistor on CFG2, but in other embodiments of the invention, other sized resistors can be used. Therefore, the HSIO source or host detects that the voltage on pin CFG2 is high and therefore operates as a HSIO device. In a particular embodiment of the invention, the cable has a 157272.doc -21 - 201230002 plug ' and a gamma cable (which may include additional circuitry) that may include circuitry. In other embodiments of the invention, all of the circuitry may be included in the plug or shackle portion of the cable. An example is shown in the figure below. Figure 10 illustrates a circuit for a cable connection in accordance with an embodiment of the present invention. A plug is provided for embedding into a connector, such as the connector shown in Figure 2. The plug is attached to a plug attached to the gamma cable portion, the gamma cable portion being coupled to the slimline outer casing portion, the gamma cable outer casing portion further including an electrical circuit. Υ The cable is attached to the monitor multilayer from that side. In this example, the high speed signal is received by the monitor via the clock and data recovery circuits 1010 and 1030, and the clock and data recovery circuits 1〇1〇 and 1〇3〇 can be located in the Υ cable housing. The outputs of these clock and data recovery circuits are provided to the clock and data recovery circuits 102 and 1〇4〇. The outputs of the clock and data recovery circuits 1020 and 1040 are provided by the piN diode (1) to provide an HSI or DisplayPort signal. Note that the bias resistors for the diodes 01 to 04 used in this figure have been omitted for clarity. Furthermore, when the #cable acts to provide the DiSplayPort signal, the clock and data recovery circuitry can operate in bypass mode to conserve power. Similarly, the high-speed signal provided by the monitor clock and data recovery circuit is deleted and received and provided to the connector via the clock and data recovery circuit in the plug. The signal can be isolated as shown. ° Λ In the example shown, the PiN diode baskets m to D4 are used to isolate the HSI〇 signal and the D1SplayP〇rt signal. Resistors, multiplexers, or other circuits or components may be used in this embodiment. In various embodiments of the present invention, the reliability of the poem connection is improved by the calibration circuit or training circuit of the host, cable, and other devices 157272.doc -22-201230002^ and the circuit may include compensation for I. Line delay, crosstalk (especially in the device), channel compensation (such as the equalization or cancellation of the reflection, and /' his circuit. Various parameters can be used to adjust these circuits. In the present invention only In the example, the parameters of such circuits may be calibrated or otherwise determined by manufacturing and stored as a preset "for carrying in the fresh period. In the present invention, in his embodiment, such parameters may be determined, and the system Connected. This

(Practice or calibration can occur during power up, restart, or other cycles or event-based times. These or other routes can be used to calibrate the path from the host to the near end of the line, the path through the horizon, and from the line Path to the device or other host. This calibration can be performed in a variety of ways. For example, the host can place the near end of the mirror in loopback mode, transfer data, receive data, and then adjust the transmit and receive parameters accordingly. Similarly, the device can place the near end of the slow line in loopback mode to 'transmit data and receive data, and then adjust the transmission and reception parameters accordingly. Any one or both of the host or device can also The distal end is placed in the loopback mode whereby the cable is also included in the calibration route. An example is shown in the following figure. Figure 11 illustrates a method of calibrating a cable and associated circuitry in accordance with an embodiment of the present invention. In step 1110, a calibration or training procedure begins. This can be triggered by power up, cable connection, reset conditions, or other periodic or event driven criteria. In act 1120, the proximal end of the cable In the loopback mode, the signal is transmitted and received via the loopback control. In action 114, the transmission and reception parameters of the near-end circuit can be optimized. In action 115〇157272.doc In -23 - 201230002, the far end of the wire can be placed in the loopback mode. In addition, in the action ιΐ6, the signal can be transmitted and received via this loopback path. In the action, the far end can be optimized. The transmission and reception parameters of the circuits may be performed by any one or both of the host and the device circuits. The foregoing description of the embodiments of the present invention has been presented for purposes of illustration and description. The present invention is to be limited or limited to the precise forms described, and many modifications and variations are possible in accordance with the above teachings. The embodiments are chosen and described in order to best explain the principles of the invention Others skilled in the art can best utilize the present invention in various embodiments and with various modifications that are suitable for the particular use contemplated. It will be appreciated that the invention is not intended to be All modifications and equivalents within the scope of the patents. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an old system that can be modified by the incorporation of embodiments of the present invention; FIG. 2 illustrates an embodiment in accordance with the present invention. FIG. 3 illustrates a circuit and method for using a connector according to an embodiment of the present invention; FIG. 4 illustrates a circuit and method for determining the type of device in communication with each other according to an embodiment of the present invention; Active cable in accordance with an embodiment of the present invention; Figure 6 illustrates an active cable in accordance with an embodiment of the present invention; Figures 7A through 7C illustrate a common connection that can be used to allow signal paths from two different standards to be hollowed out to a common connector. The circuit of the pin; , Figures 8A and 8B illustrate an alternative circuit that can be used to allow signals from the two different standards, 157272.doc -24 - 201230002, /, and a common pin for the connector; Figure 9 illustrates the n pieces Circuit and method for determining what type of device it is connected to; FIG. 10 illustrates a circuit for winding a mirror line in accordance with an embodiment of the present invention; and FIG. 11 illustrates a calibration line in accordance with an embodiment of the present invention RELATED circuits. [Main component symbol description] Ο

1 Grounding pin 2 Hot plug detecting pin 3 Still speed transmitting pin 4 High-speed receiving pin 5 High-speed transmission pin 6 South speed receiving pin 7 Grounding pin 8 Grounding pin 9 Connector 10 Connector 11 Pin 12 pin 13 ground pin 14 ground pin 15 high speed transmission pin 16 high speed receiving pin 17 high speed transfer pin 157272.doc •25- 201230002 18 high speed receiving pin 19 grounding pin 20 power pin 110 computer 115 Legacy Connection 120 Legacy Display 220 Computer or Display 225 South Speed Connection 230 Drive 235 High Speed Connection 410 Line 420 Line 430 Line 440 Line 450 Line 460 Line 500 Active Plug/Cable Plug 505 Active Plug/ Cable Plug 507 Cable 510 Clock and Data Recovery Circuit / CDR 520 Cable Microcontroller 530 Clock and Data Recovery Circuit / CDR 540 Clock and Data Recovery Circuit / CDR 550 Cable Microcontroller 157272.doc - 26- 201230002 560 Clock and Data Recovery Circuit / CDR 600 Active Plug 605 Active Plug 607 Cable 610 Clock and Data Recovery Circuit / CDR 615 Clock and Data Recovery Circuit / CDR 620 Cable Micro 630 Clock and Data Recovery Circuit / CDR 635 Clock and Data Recovery Circuit / CDR 640 Clock and Data Recovery Circuit / CDR 645 Clock and Data Recovery Circuit / CDR 650 Cable Microcontroller 660 Clock and Data Recovery Circuit / CDR 665 Clock and Data Recovery Circuit / CDR 910 Line 920 Line ο 930 Line 940 Line 1010 Clock and Data Recovery Circuit / CDR 1020 Clock and Data Recovery Circuit / CDR 1030 Clock and Data Recovery Circuit / CDR 1040 Clock and Data Recovery Circuit / CDR 1050 Clock and Data Recovery Circuit / CDR 1060 Clock and Data Recovery Circuit / CDR 157272.doc -27- 201230002 1070 Clock and Data Recovery Circuit / CDR 1080 Clock and Data Recovery Circuit / CDR B1 driver/buffer B2 driver/buffer B3 buffer B4 buffer Cl capacitor C2 capacitor C3 capacitor CFG1 configuration pin CFG2 configuration pin D1 PiN diode D2 PiN diode D3 PiN diode D4 PiN Diode LI Inductor Ml Multiplexer PI Pad R1 Resistor R2 Resistor R3 Resistor 157272.doc -28-

Claims (1)

201230002 VII. Patent application scope: 1 · An active cable comprising: a cable; a first plug connected to one of the first ends of the cable and comprising: a first clock and a data recovery circuit Reclocking the signal received at one of the inputs of the first plug; a second clock and data recovery circuit re-timing the signal received from the view; and Ο a first microcontroller Configuring the first clock and data recovery circuit and the second clock and data recovery circuit; and a second plug connected to the second end of the cable and comprising: a third clock And a data recovery circuit that retimes the signal received at one of the inputs of the second plug; a fourth clock and data recovery circuit that retimes the signal received from the cable; and a second micro The controller configures the third clock and data recovery ♦ Γ) ', the circuit and the fourth clock and data recovery circuit. 2. The active cable of claim 1, wherein the cable connects the output of one of the first clock and data recovery circuits to one of the fourth clock and data recovery circuits and the third time An output of one of the pulse and data recovery circuits is coupled to one of the input terminals of the second clock and data recovery circuit. 3. The active cable of claim 1, wherein the first microcontroller and the second controller are programmable using the first plug and the pin on the second plug. 157272.doc 201230002 4. The active cable of claim 1 wherein the first clock and data recovery circuit comprises an equalizer circuit. 5 The active cable of claim 1, wherein the first clock and data recovery circuit comprises a de-emphasis circuit. 6. The active cable of claim 1 wherein the first microcontroller is configurable to output one of the first clock and data recovery circuits to be coupled to one of the second clock and data recovery circuits end. The active cable of claim 1, wherein the first microcontroller can configure an output of the second clock and data recovery circuit to be coupled to one of the first clock and data recovery circuits. end. 8. A cable assembly comprising: a cable; a first plug [which is consuming one of the loops and includes a circuit to receive and transmit signals; and a second plug' The second circuit is connected to the second line and includes a circuit for receiving and transmitting signals, and wherein the first circuit and the second circuit are powered when the I line transmits the coincident-co-k signal, and In the case of a signal of money,,, 9. agreement, the first circuit and the second circuit, a &lt;RTI ID=0.0&gt;&gt; The pin to the first plug &amp; ^ ^ B contains one of the inputs, one of the inputs, the original circuit, and the conductor that is connected to the line order? Pulse and data loss recovery circuit. The second clock and the remaining 1 _ _ the cable assembly 157272.doc of claim 9 further includes a first 201230002 clock and data recovery circuit and the second clock and data recovery circuit A microcontroller. 11. The cable assembly of claim 1, wherein the microcontroller is programmable using at least one of the first plugs. 12. The cable assembly of claim </ RTI> wherein the microcontroller can be programmed using the code provided at the at least the pin of the first plug. 13. The lanyard assembly of claim 12, wherein the code is encrypted. An electronic device, comprising: a connector comprising a plurality of pins; a first output circuit coupled to the pins of the plurality of pins and comprising: 15. a selection circuit coupled To the first pin; the driver, which is AC coupled to the selecter-second driver, to the select circuit. The electronic device of claim 14. The AC is lightly coupled to an attenuating device 'where the connector is a path; and the attenuator is coupled to a connector embedding the electronic device of claim 14. Where the connector is a connector plug Wherein the attenuator is 'where the electrical p i network is selected. The circuit comprises a plurality of 17. The electronic device of claim 14, 18. The electronic device PiN of the claim 14 is a polar body. 19. The electronic device of claim 14, wherein the selection circuit comprises a multiplex 157272.doc 201230002. 20. The electronic device of claim 14, further comprising a receiving circuit, the receiving circuit comprising: a first a switch having a first terminal coupled to one of the plurality of pins; a receiving circuit AC coupled to the second terminal of the first switch; an inductor having a coupling Connected to one of the first terminals of the second pin; and a capacitor coupled between the second terminal of one of the inductors and the ground. 21. The electronic device of claim 20, further comprising a multiplexer coupled to the second terminal of the inductor. 22. The electronic device of claim 20, wherein the switch comprises a PiN diode. 157272.doc -4-