TWI444954B - Transmission interface and transmission method for display apparatus - Google Patents

Description

Signal transmission interface and signal transmission method of display device

The present invention relates to a signal transmission interface and a signal transmission method thereof, and more particularly to a signal transmission interface of a display device and a signal transmission method thereof.

In recent years, display panel technology has become more and more mature, but with the needs of consumers, the size of display panels is getting bigger and bigger, and the resolution is getting higher. However, when the resolution and size of the display panel increase, it will lead to The operating frequency inside the panel is getting higher and higher.

The traditional intra-panel interface of the display panel requires a large number of transmission lines. In a high-frequency environment, it is difficult to make each transmission line have similar electrical properties; therefore, the receiving end is not easy to be effective for this. The correction mechanism, the bit error rate, cannot be reduced. More importantly, the system requires additional costs to deal specifically with this issue, and the competitiveness of the product cannot be improved.

Traditional transmission interfaces, such as the RSSD (Reduce Swing Differential Signaling) transmission interface, are connected in the form of transmission pairs, which can be reduced to a small amplitude, thereby supporting high frequency applications and generating less electromagnetic interference (EMI). . The transmission mode of the transmission interface of the Point-to-Point Differential Signaling (PPDS) is a single-point-to-single-point transmission mode. The load on the transmission side is lighter and easier to be estimated by the control, and there is less for a single source driver. Transmission line pair. The above transmission interface must be sampled with an additional clock signal transmission line. Therefore, when operating at high frequencies, electromagnetic interference and clock offset may occur due to clock and data transmission through different transmission lines. The situation of skew, which in turn causes a problem of an increase in the bit error rate.

The invention provides a signal transmission method for a display panel, which can reduce electromagnetic interference and reduce the bit error rate.

The invention provides a signal transmission method for a display device, wherein the display device comprises a source driver and a display panel. The signal transmission method comprises: first, embedding a clock information into a data signal sequence in a specific data format, wherein the data signal sequence comprises a plurality of data segments, each data segment comprising a plurality of pixel signals, the pixel signals Separated by clock information into multiple pixel signal segments. Next, the data signal sequence is transmitted to the source driver to drive the display panel.

The invention also provides a signal transmission interface of a display device, wherein the display device comprises a display panel. The signal transmission interface includes a timing controller and a source driver. The timing controller receives a sequence of data signals and embeds a clock information into a sequence of data signals in a specific data format. The data signal sequence includes a plurality of data segments, and each data segment includes a plurality of pixel signals, and the pixel signals are separated into a plurality of pixel signal segments by clock information. In addition, the source driver drives the display panel according to a sequence of data signals embedded with clock information.

In an embodiment of the invention, each of the pixel signal segments includes two pixel signals.

In an embodiment of the invention, each of the pixel signals is a bit signal of X bits, wherein X is a positive integer.

In an embodiment of the invention, the specific data format includes a bit signal of M bits located at a beginning position of each pixel signal section, and a bit of N bits located at a position of the end of each pixel signal section. Signal, where M and N are positive integers.

In an embodiment of the invention, wherein M = N = 2, and the bit signal at the beginning position is 11, and the bit signal at the end position is 00.

In an embodiment of the invention, wherein M=1 and N=2, and the bit signal at the beginning position is 1, and the bit data at the end position is 00.

In an embodiment of the present invention, each of the data sections further includes a start signal, a plurality of control signals, and a dummy signal, and the start signal, the control signal, and the dummy signal are bits of 2X bits. A meta-signal, where X is a positive integer. The start signal, the control signal, and the dummy signal are embedded in a specific data format by the clock information and are respectively divided into a start signal segment, a plurality of control signal segments, and a dummy signal segment, wherein the start signal segment is located in the data The beginning of the segment, and the dummy signal segment is at the end of the data segment.

Based on the above, the present invention utilizes the clock information embedded in the data signal sequence, so that the pixel data transmission line can be sampled without using the clock signal transmission line to reduce the electromagnetic interference problem of the traditional transmission interface during high frequency operation and reduce the bit element. Error rate.

The above described features and advantages of the present invention will be more apparent from the following description.

1 is a schematic diagram of a signal transmission interface of a display device according to an embodiment of the invention. 2 is a flow chart of a signal transmission method of a display panel according to an embodiment of the invention. Hereinafter, the signal transmission method of the display panel will be described with reference to FIG. 1 and FIG. 2, please refer to FIG. 1 and FIG. 2 at the same time. The signal transmission interface of display device 100 includes a timing controller 104 and a source driver 106. The signal transmission method steps of the display panel 102 are as follows. First, the timing controller 104 receives a data signal sequence S1 and embeds a clock information into the data signal sequence S1 in a specific data format (step S202). The source driver 106 drives the display panel 102 in accordance with the data signal sequence S1 embedded with the clock information (step S204). Thus, by embedding the clock information in the data signal sequence S1, the timing controller 104 does not need to additionally transmit the clock signal to the source driver 106. The source driver 106 can restore the clock information embedded in the data signal sequence S1 to a clock signal by using a delay locked loop (DLL) or a phase locked loop (PLL). Therefore, the source driver 106 can correctly read the data from the data signal sequence S1 according to the clock information embedded in the data signal sequence S1, thereby driving the display panel 102 without the conventional transmission interface operating at high frequency. Electromagnetic interference problem. It should be noted that, in this embodiment, the display device 100 includes only one source driver 106, but is not limited thereto. In other embodiments, display device 100 can include more source drivers 106 to effectively drive pixels on display panel 102 when the display panel 102 is larger.

In detail, the data signal sequence S1 can be as shown in FIG. The data signal sequence S1 includes a plurality of data segments DA1, wherein each data segment DA1 includes a start signal, a dummy signal, a plurality of control signals, and a plurality of pixel signals, and the signals are respectively received by the clock information. It is divided into a start signal section DS1, a dummy signal section DU1, a plurality of control signal sections DC1 (two control signal sections DC1 in this embodiment), and a plurality of pixel signal sections DP1. The start signal segment DS1 is located at the beginning of the data segment DA1 to indicate the start time of the data segment DA1, and the dummy signal segment DU1 is located at the end of the data segment DA1 to indicate the end of the data segment DA1. time. The control signal in the control signal section DC1 carries information controlled by the panel, such as dynamic image adjustment or dynamic adjustment of panel characteristics. In addition, the pixel signal in the pixel signal segment DP1 carries the pixel data for driving the display panel 102. It should be noted that, in this embodiment, the position of the control signal segment DC1 is in front of the dummy signal DU1, but not limited thereto, the control signal segment DC1 may be located in the start signal segment DS1 and the dummy signal segment. At any position between DU1, for example, immediately after the start signal segment DS1.

Further, each of the start signal segment DS1, the dummy signal segment DU1, the control signal segment DC1, and the pixel signal segment DP1 may be regarded as one packet, and the format of the packet may be according to the source driver 106. Demand to design. For example, FIG. 4A is a schematic diagram of a packet format of a pixel signal segment DP1 according to an embodiment of the present invention. Referring to FIG. 4A, in the embodiment, each pixel signal segment DP1 includes two pixel signals. However, in other embodiments, the pixel signal segment DP1 may include more pixel signals. (eg three pixel signals). When the format of the source driver 106 is 6 bits, the packet format of the pixel signal segment DP1 is 16 bits for one packet. The packet includes two 6-bit pixel signals P1 and P2, and a bit signal "11" at the beginning of the pixel signal segment DP1 and a bit signal "00" at the end of the pixel signal segment DP1. For the embedded clock information. When the source driver 106 detects the bit signals (ie, "11") of two consecutive high voltage levels in the pixel signal segment DP1, the source driver 106 can thereby know the bit signal. The bit signal after 11" is the pixel data, and the display panel 102 is driven accordingly. When the source driver 106 detects the bit signals of two consecutive low voltage levels (ie, "00") in the pixel signal segment DP1, the source driver 106 can learn that the packet has been transmitted. Finished. Similarly, when the format of the source driver 106 is 8-bit or 10-bit, the pixel signals P1 and P2 in the pixel signal segment DP1 are 8-bit and 10-bit, respectively, and the embedded clock. The information "11" and "00" are 4 bits, so the packet format is 20 bits or 24 bits.

It should be noted that although the pixel transmission signals P1 and P2 of the 6-bit, 8-bit, and 10-bit are taken as an example for the description of the signal transmission method, the present invention is not limited thereto. The number of bits of the pixel signals P1 and P2 can be adjusted according to actual conditions. In addition, the bit signals (that is, the clock information used to separate the signals) placed at the beginning and the end of each segment are not limited to "11" or "00", and those skilled in the art can rely on The actual situation adjusts its number of bits and the value of the bit. For example, the bit signal placed at the beginning of each segment can be set to "1", and the bit signal placed at the end position and the end position of each segment is "00", so that the signals can be separated. Therefore, setting the bit signal of the end position to "00" (that is, two consecutive low voltage levels) can prevent the voltage level of the signal from falling too slowly, so that the source driver 106 can not discriminate the low logic voltage level. And cause a misjudgment of the signal.

Similarly, other signals (start signal, dummy signal, and control signal) in the data section DA1 can also be embedded in the clock information in the same manner. As shown in FIG. 4B, the clock information "11" and "00" are respectively placed at the beginning and the end of the dummy signal to separate the dummy signal section DU1. The dummy signal segment DU1 generated by being separated by the clock information is different from the above-described pixel signal segment DP1 in that the pixel signal segment DP1 includes two pixel signals, and the dummy signal segment DU1 is only Includes a dummy signal, and the dummy signal has twice the number of bits of the pixel signal.

Similarly, in FIG. 4C, the clock information "11" and "00" are respectively placed at the beginning and the end of the start signal to separate the start signal segment DS1. The start signal segment DS1 separated by the clock information after being embedded is different from the above-described pixel signal segment DP1 in that the pixel signal segment DP1 includes two pixel signals, and the start signal segment DS1 includes only one start signal, and the number of bits of the start signal is twice that of the pixel signal.

In addition, in FIG. 4D, the clock information "11" and "00" are also placed at the beginning and the end of the control signal, respectively, to separate the control signal section DC1. The control signal segment DC1 generated by being separated by the clock information is different from the above-described pixel signal segment DP1 in that the pixel signal segment DP1 includes two pixel signals, and the control signal segment DC1 only A control signal is included, and the number of bits of the control signal is twice that of the pixel signal.

FIG. 5 is a schematic diagram of a source driver according to an embodiment of the invention. Referring to FIG. 5, the source driver 500 includes a serial to parallel conversion unit 502 and a plurality of pixel signal distribution units 504. The serial-to-parallel conversion unit 502 is coupled to the pixel signal distribution unit 504 through the data transmission lines L1 and L2. Each pixel signal distribution unit 504 includes a latch LA1, a latch LA2, a switching device SW1, a switching device SW2, a digital analog converter DAC1, a digital analog converter DAC2, a buffer BF1, and a buffer BF2. The latch LA1 and the input end of the latch LA2 are respectively coupled to the data transmission lines L1 and L2. The switching device SW1 is coupled to the output of the latch .LA1 and the latch LA2. The switching device SW1 operates in a first connection state and a second connection state. In the first connected state, the switching device SW1 connects the output of the latch LA1 to the input of the digital analog converter DAC1 and the output of the latch LA2 to the input of the digital analog converter DAC2. In the second connected state, the switching device SW1 connects the output of the latch LA1 to the input of the digital analog converter DAC2 and the output of the latch LA2 to the input of the digital analog converter DAC1.

The digital analog converter DAC1 and the buffer BF1 are connected in series between the switching device SW1 and the switching device SW2, and the digital analog converter DAC2 and the buffer BF2 are also connected in series between the switching device SW1 and the switching device SW2. The switching device SW2 is coupled to a pixel on the display panel 102. The operation of the switching device SW2 is similar to the switching device SW1.

The serial to parallel conversion unit 502 is configured to convert the data format of the received signal from a serial form to a parallel form. The digital analog converter DAC1 and the coupled buffer BF1 are responsible for generating a positive polarity voltage, and the digital analog converter DAC2 and the coupled buffer BF2 are responsible for generating a negative polarity voltage. The switching devices SW1 and SW2 are configured to transmit the pixel voltages of the positive polarity voltage and the negative polarity voltage to the display panel 102 when the display panel 102 performs polarity inversion.

When the serial-to-parallel conversion unit 502 receives the data signal sequence S1 from the timing controller 104, the serial-to-parallel conversion unit 502 converts the pixel signal in the data signal sequence S1 from the serial data form to the parallel data form, and The latch LA1 and the latch LA2 in the pixel signal distribution unit 504 are respectively transmitted to the data transmission lines L1 and L2. The pixel data transmitted to the latch LA1 and the latch LA2 is output to the analog signal via the switching device SW1, the digital analog converter DAC1, the DAC2, the buffer BF1, the buffer BF2, and the switching device SW2. The pixels on the display panel 102 are driven to drive the display panel 102 to display a picture.

As described above, by using the signal transmission method of the embodiment of the present invention, the pixel signal in the data signal sequence S1 is divided into two segments for each two pixel signals, and the serial to parallel conversion unit 502 can be matched with the data transmission line. L1 and L2 sequentially transmit the pixel signals to the pixel signal distribution unit 504 to distribute the pixel data to the display panel 102, for example, the pixel signal P1 in each pixel segment DP1 is transmitted by the data transmission line L1. The pixel signal P2 in each pixel segment DP1 is transmitted by the data transmission line L2. In this way, compared with the conventional one, only one data transmission line is used to transmit the pixel signal, and the pixel signal is transmitted in a parallel manner, which can greatly improve the update speed of the display screen.

In other embodiments, the pixel signal in the data signal sequence S1 may be divided into three segments for each of the three pixel signals, and the serial to parallel conversion unit 502 transmits the pixel signals through the data transmission lines L1 and L2. It is transmitted to the pixel signal distribution unit 504 to distribute the pixel data to the display panel 102. However, this method will cause the serial-to-parallel conversion unit 502 to indiscriminately assign the pixel signals in each pixel signal segment to a specific data transmission line in sequence, and a program for combining the signals must be added to draw the picture. The signal is transmitted to the display panel in the correct order, thereby making the circuit design of the serial to parallel conversion unit 502 more complicated.

In summary, the transmission interface of the embodiment of the present invention uses the clock information to be embedded in the data signal sequence, so that the clock signal transmission line is not required to be used for sampling the pixel data, thereby reducing the traditional transmission interface at high frequency operation. The electromagnetic interference problem and reduce the bit error rate. In addition, in the case where each pixel signal section includes two signals, applying the signal transmission method to the source driver having two data transmission lines can greatly improve the update speed of the display screen.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Display device

102. . . Display panel

104. . . Timing controller

106,500. . . Source driver

502. . . Tandem to parallel conversion unit

504. . . Signal distribution unit

DA1. . . Data section

DU1. . . Dumb signal section

DS1. . . Start signal segment

DP1. . . Pixel signal segment

DC1. . . Control signal section

P1, P2. . . Pixel signal

S1. . . Data signal sequence

LA1, LA2. . . Latch

L1, L2. . . Data transmission line

DAC1, DAC2. . . Digital analog converter

SW1, SW2. . . Switching device

BF1, BF2. . . buffer

S202~S204. . . Display panel signal transmission method steps

1 is a schematic diagram of a signal transmission interface of a display device according to an embodiment of the invention.

2 is a flow chart of a signal transmission method of a display panel according to an embodiment of the invention.

3 is a schematic diagram of a data signal sequence in accordance with an embodiment of the present invention.

FIG. 4A is a schematic diagram of a packet format of a pixel signal segment according to an embodiment of the present invention.

FIG. 4B is a schematic diagram of a packet format of a dummy signal segment according to an embodiment of the present invention.

4C is a schematic diagram of a packet format of a start signal segment according to an embodiment of the present invention.

4D is a schematic diagram of a packet format of a control signal segment according to an embodiment of the invention.

FIG. 5 is a schematic diagram of a source driver according to an embodiment of the invention.

S202~S204. . . Display panel signal transmission method steps

Claims (12)

A signal transmission method for a display device, the display device comprising a source driver and a display panel, the method comprising: embedding a clock information in a specific data format into a data signal sequence, wherein the data signal sequence comprises a plurality of data regions a segment, each of the data segments includes a plurality of pixel signals, the pixel signals are separated into a plurality of pixel signal segments by the clock information, and the specific data format includes a position at a beginning of each pixel signal segment a bit signal of the M bit, and a bit signal of N bits located at the end of each pixel signal segment, wherein M and N are positive integers; and transmitting the data signal sequence to the source driver Drive the display panel. The signal transmission method of the display device according to claim 1, wherein each of the pixel signal segments includes two pixel signals. The signal transmission method of the display device according to claim 1, wherein each of the pixel signals is a bit signal of X bits, wherein X is a positive integer. The signal transmission method of the display device according to claim 1, wherein M=N=2, and the bit signal at the beginning position is 11, and the bit signal at the end position is 00. The signal transmission method of the display device according to claim 1, wherein M=1 and N=2, and the bit signal at the beginning position is 1, and the bit data at the end position is 00. Signal transmission of the display device as described in claim 1 of the patent application The data input method further includes a start signal, a plurality of control signals, and a dummy signal, and the start signal, the control signals, and the dummy signal are bit signals of 2× bits, and X is positive An integer, the start signal, the control signals, and the dummy signal are embedded in the specific data format by the clock information, and are respectively divided into a start signal segment, a plurality of control signal segments, and a dummy signal segment. Wherein the start signal segment is located at the beginning of the data segment and the dummy signal segment is located at the end of the data segment. A signal transmission interface of a display device, the display device includes a display panel, the signal transmission interface includes: a timing controller, receives a data signal sequence, and embeds a clock information into the data signal sequence in a specific data format, wherein The data signal sequence includes a plurality of data segments, each of the data segments including a plurality of pixel signals, the pixel signals being separated into a plurality of pixel signal segments by the clock information, and the specific data format includes a bit signal of M bits at the beginning of each pixel signal segment, and a bit signal of N bits at the end of each pixel signal segment, where M and N are positive integers; and a source The driver drives the display panel according to the data signal sequence embedded in the clock information. The signal transmission interface of the display device of claim 7, wherein each of the pixel signal segments comprises two pixel signals. The signal transmission interface of the display device according to claim 7, wherein each of the pixel signals is a bit signal of X bits, wherein X is a positive integer. The signal transmission interface of the display device according to claim 7, wherein M=N=2, and the bit signal at the beginning position is 11, and the bit signal at the end position is 00. The signal transmission interface of the display device according to claim 7, wherein M=1 and N=2, and the bit signal at the beginning position is 1, and the bit data at the end position is 00. The signal transmission interface of the display device of claim 7, wherein each of the data segments further includes a start signal, a plurality of control signals, and a dummy signal, and the start signal, the control signals, and the The dummy signal is a bit signal of 2X bits, and X is a positive integer. The start signal, the control signals, and the dummy signal are embedded in the specific data format by the clock information and are respectively separated into a start signal segment. And a plurality of control signal segments and a dummy signal segment, wherein the start signal segment is located at a beginning of the data segment, and the dummy signal segment is located at an end of the data segment.