TWI742762B - Display device and auto-calibration method thereof - Google Patents

Abstract

A display device includes a timing controller circuit and a plurality of source driver circuits. The timing controller circuit calculates a calibration setting time for calibrating a source driver circuit according to a data rate and a total number of packets of a calibration data for transmitting, calculates a delay time and a number of packets corresponding to the delay time according to the calibration setting time and a number of transmitters of the timing controller, and transmits the calibration setting data to the plurality of source driver circuits every the delay time according to an order of the transmitters of the timing controller. Each source driver circuit receives the calibration setting data for calibrating during the calibration setting time, and transmits a calibration signal to the timing controller during the delay time behind the calibration setting time to inform whether a calibration is finished.

Description

Display device and automatic correction method thereof

The invention relates to a display device and an automatic correction method thereof.

Since TV products on the market have many different open cell designs, this means that the material and length of the flexible flat cable (FFC) used by the factory and the client will be different, making such LCD panels available to customers. In the application of the end, there will be poor design, such as insufficient design or overdesign. Therefore, automatic correction (auto- calibration) design to solve the problem of poor design. The traditional automatic calibration method is to perform automatic calibration between the clock controller and a source driver integrated circuit, and after the automatic calibration between them is completed, the clock controller and the other source driver integrated circuit will automatically calibrate. , And the automatic calibration between the clock controller and other source driver integrated circuits will be carried out in sequence until the automatic calibration between the clock controller and the last source driver integrated circuit is completed. However, as the resolution of the liquid crystal panel gets higher and higher, the number of source driver ICs will increase, and the time spent on automatic calibration will increase. Therefore, how to shorten the automatic calibration time between the clock controller of the liquid crystal panel and the multiple source driver integrated circuits is an important issue to be solved in the technical field.

The invention provides a display device and an automatic correction method thereof, which can effectively reduce the time for automatic correction of the display device.

The display device provided by the present invention includes a clock control circuit and a plurality of source driving circuits coupled to the clock control circuit. The clock control circuit has a plurality of transmitting terminals and a receiving terminal, each source driving circuit has a receiving terminal and a transmitting terminal, and the plurality of receiving terminals of the plurality of source driving circuits are sequentially and electrically connected to the clock. The multiple transmitting ends of the control circuit and the multiple transmitting ends of the multiple source driving circuits are electrically connected to the receiving end of the clock control circuit after being electrically connected to each other. Among them, the clock control circuit calculates a calibration setting time for each source driver circuit to calibrate according to a data transmission rate and a total number of sent packets of a calibration setting data, and a plurality of transmissions based on the calibration setting time and the clock control circuit. The number of terminals calculates a delay time and the number of packets corresponding to the delay time, and sends the correction setting data to the multiple source driving circuits every delay time according to the order of the multiple sending ends of the clock control circuit. Wherein, after each source driving circuit receives the calibration setting data for calibration and after the calibration setting time has elapsed, each source driving circuit sends a calibration signal to the clock control circuit within a delay time after the calibration setting time has elapsed. Whether the calibration is complete. Among them, the delay time is less than the correction setting time.

The automatic correction method provided by the present invention is applied to a display device including a clock control circuit and a plurality of source driving circuits, wherein the clock control circuit has a plurality of transmitting terminals and a receiving terminal, and the plurality of source driving circuits are coupled Connected to the clock control circuit, each source drive circuit has a receiving end and a sending end, and the multiple receiving ends of the multiple source drive circuits are sequentially and individually electrically connected to the multiple sending ends of the clock control circuit. indivual The multiple transmitting ends of the source driving circuit are electrically connected to the receiving end of the clock control circuit after being electrically connected to each other. The automatic calibration method includes: calculating a calibration setting time for each source driver circuit to calibrate according to a data transmission rate and a total number of sent packets of a calibration setting data; Calculate a delay time and the number of packets corresponding to the delay time; send correction setting data to multiple source drive circuits every delay time according to the sequence of multiple sending ends of the clock control circuit; and after receiving the correction setting data and undergoing correction After the time is set, a calibration signal is sent to the clock control circuit within the delay time after the calibration setting time is continued to notify whether the calibration is completed; wherein the delay time is less than the calibration setting time.

In an embodiment of the present invention, when the timing control circuit receives a high-level correction signal of the source drive circuit, the source drive circuit is calibrated; and the timing control circuit receives a low level of the source drive circuit. When the potential correction signal, the source drive circuit has not been corrected.

In an embodiment of the present invention, when a source driving circuit is not calibrated, the source driving circuit repeatedly performs calibration within the next calibration setting time after the connection delay time and after the next calibration setting time is continued Send the correction signal to the clock control circuit within the next delay time until the clock control circuit receives the high-level correction signal of the source drive circuit.

In an embodiment of the present invention, the clock control circuit includes a plurality of delay circuits, and each delay circuit is electrically connected to each other in sequence and individually electrically connected to a plurality of transmitting ends of the clock control circuit. Each delay circuit includes: an enabling circuit and a counter. Each enabling circuit is configured to be electrically connected to a transmitting end of the clock control circuit, and each counter configured to be electrically connected to the enabling circuit. Wherein, the plurality of counters of the plurality of delay circuits are electrically connected to each other in sequence. Among them, the timing control circuit sends correction settings through the transmitter When data, a counter of the delay circuit counts the number of packets of correction setting data or counts a time, and when the counter counts the number of packets of correction setting data equal to the number of packets corresponding to the delay time or the counted time is equal to the delay time, the counter sends A trigger signal is sent to the enable circuit and the counter of the other delay circuit connected to the counter, so that the enable circuit enables the transmitter to send the correction setting data, and the counter of the other delay circuit starts counting or counting the number of packets of the correction setting data. Count the time.

The display device and the automatic correction method provided by the present invention stagger the time for each sending end in the clock control circuit to send the correction setting data, and at the same time reserve the time for each source drive circuit to respond to the correction signal, which can greatly The time for automatic calibration of the display device is shortened, and at the same time, the clock control circuit can receive the calibration signal returned by each source driving circuit without overlapping problems.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, the following specific examples are given in conjunction with the accompanying drawings, which are described in detail as follows.

1: display device

2: Clock control circuit

21: enabling circuit

22: counter

A: Correction signal

CST1, CST2,..., CSTm-2: Calibration setting time

D1, D2,..., Dn: Delay circuit

DT1, DT2,..., DTm-2: Delay time

S-IC1, S-IC2, S-IC3,..., S-ICn-2, S-ICn-1, S-ICn: source drive circuit

Tx, Tx1, Tx2, Tx3,..., Txn-2, Txn-1, Txn: sender

Rx: receiving end

S1, S3, S5, S7: steps

1 is a schematic diagram of a display device provided by an embodiment of the present invention; FIG. 2 is a schematic diagram of a clock control circuit provided by an embodiment of the present invention; FIG. 3 is a flow chart of an automatic calibration method provided by an embodiment of the present invention Figure; Figure 4 is a timing diagram of automatic correction provided by an embodiment of the present invention.

Hereinafter, the present invention will be described in detail by illustrating various embodiments of the present invention with drawings. However, the concept of the present invention may be embodied in many different forms and should not be The interpretation is limited to the exemplary embodiments set forth herein. In addition, the same reference numerals in the drawings may be used to indicate similar elements.

FIG. 1 is a schematic diagram of a display device provided by an embodiment of the invention. As shown in FIG. 1, the display device 1 provided by the embodiment of the present invention includes a time controller (Tcon) 2 and a plurality of source driver integrated circuits (S-IC) S-IC1 and S-IC. IC2, S-IC3,..., S-ICn. The clock controller circuit 2 has a plurality of transmitting terminals Tx1, Tx2,..., Txn and a receiving terminal Rx. A plurality of source drive circuits S-IC1, S-IC2, S-IC3,..., S-ICn are coupled to the clock control circuit 2, and each source drive circuit S-IC1, S-IC2, S- IC3,...,S-ICn have a receiving terminal Rx and a transmitting terminal Tx, and the receiving terminals Rx of all source driving circuits S-IC1, S-IC2, S-IC3,..., S-ICn are in sequence And individually and electrically connected to the transmitting terminals Tx1, Tx2,..., Txn of the clock control circuit 2, and the transmitting terminals of all source driving circuits S-IC1, S-IC2, S-IC3,..., S-ICn After the Tx are electrically connected to each other, they are electrically connected to the receiving end Rx of the clock control circuit 2.

FIG. 2 is a schematic diagram of a clock control circuit provided by an embodiment of the invention. As shown in FIG. 2, the clock control circuit 2 provided by the embodiment of the present invention includes a plurality of delay circuits D1, D2,..., Dn, and each delay circuit D1, D2,..., Dn is electrically connected to each other in sequence. Connected and individually electrically connected to the transmitting terminals Tx1, Tx2,..., Txn of the clock control circuit 2. Specifically, each of the delay circuits D1, D2,..., Dn includes an enabling circuit 21 and a counter 22. The enabling circuits 21 of the delay circuits D1, D2,..., Dn are configured to be electrically and dependent on The transmitting terminals Tx1, Tx2,..., Txn of the clock control circuit 2 are connected in sequence, the counter 22 is configured to be electrically connected to the enabling circuit 21, and the counters 22 of all the delay circuits D1, D2,..., Dn are connected to each other in sequence Electrical connection. For example, the enabling circuit 21 of the delay circuit D1 is electrically connected to the transmitting terminal Tx1 of the clock control circuit 2, and the counter of the delay circuit D1 is The counter 22 is electrically connected to the enabling circuit 21 of the delay circuit D1 and the counter 22 of the delay circuit D2, the enabling circuit 21 of the delay circuit D2 is electrically connected to the transmitting terminal Tx2 of the clock control circuit 2, and the counter 22 of the delay circuit D2 is electrically connected. The enabling circuit 21 of the delay circuit D2 and the counter 22 of the delay circuits D1 and D3 are electrically connected, and the enabling circuit 21 of the delay circuit Dn is electrically connected to the transmitting terminal Txn of the clock control circuit 2, and the counter 22 of the delay circuit Dn is electrically connected. The enable circuit 21 of the delay circuit Dn and the counter 22 of the delay circuit Dn-1 are connected.

FIG. 3 is a flowchart of an automatic calibration method provided by an embodiment of the present invention, and FIG. 4 is a timing diagram of an automatic calibration provided by an embodiment of the present invention. Referring to FIGS. 1-4 at the same time, the automatic calibration method of the display device 1 provided by the embodiment of the present invention includes the following steps. Step S1: The clock control circuit 2 calculates each source driver circuit S-IC1, S-IC2, S-IC3,... ., a calibration setting time (calibration setting time) for S-ICn to calibrate. The equation for the correction setting time calculated by the clock control circuit 2 is X*Y*(1/Z), where the parameter X is the total number of packets sent for the correction setting data, and the parameter Y is the unit period (unit The number of interval, UI) and the parameter Z are the data transmission rate. In an example, the total number of sent packets of the calibration setting data is 94080 packets, the length of each packet is 9 unit intervals, and the data transmission rate is 3Gbps, the calibration setting time calculated by the clock control circuit 2 It is 282.24μs. It is understandable that those skilled in the art can adjust the parameters X, Y, and Z according to the design requirements of the display device. The above example teaches the method of calculating the correction setting time, and the present invention is not limited to this.

In step S3, the clock control circuit 2 calculates a delay time and the number of packets corresponding to the delay time according to the correction setting time and the number of the sending ends Tx1, Tx2,..., Txn of the clock control circuit 2. , Where the delay time is less than the calibration setting set time. The delay time calculated by the clock control circuit 2 is equal to the correction setting time divided by the number of sending ends Tx1, Tx2,..., Txn of the clock control circuit 2. In an example, the number of sending ends Tx1, Tx2,..., Txn of the clock control circuit 2 is 24, the delay time calculated by the clock control circuit 2 is 282.24/24=11.76 μs, and the corresponding delay time The number of packets is 94080/24=3920 packets. It is understandable that those skilled in the art can increase or decrease the number of source driving circuits and the number of sending ends of the corresponding clock control circuit according to the resolution requirements of the display device. The above example teaches calculating the delay time and its corresponding The number of packets is not limited to this invention.

In step S5, the clock control circuit 2 sends the correction setting data to all the source drive circuits S-IC1, S-IC2 every delay time in the order of the sending ends Tx1, Tx2,..., Txn of the clock control circuit 2 , S-IC3,..., S-ICn. When the clock control circuit 2 transmits correction setting data through the transmitting terminals Tx1, Tx2,..., Txn, a counter 22 of the delay circuit D1, D2,..., Dn counts the number of packets of correction setting data or counts one When the counter 22 counts the number of packets of the correction setting data equal to the number of packets corresponding to the delay time or the counted time is equal to the delay time, the counter 22 sends a trigger signal to the enable circuit 21 and another delay circuit D2 connected to the counter 22 ,..., Dn counter 22, enabling the enabling circuit 21 to enable the transmitting terminals Tx1, Tx2,..., Txn to send correction setting data, and enabling the counter 22 of another delay circuit D2,..., Dn Start counting the number of packets of correction setting data or counting a time.

In an example, when the clock control circuit 2 sends the correction setting data through the transmitting terminal Tx1, the counter 22 of the delay circuit D1 starts to count the number of packets of the correction setting data. When the counter 22 of the delay circuit D1 counts the number of packets of the correction setting data equal to the number of 3920 packets corresponding to the delay time, the counter 22 of the delay circuit D1 sends The trigger signal is sent to the enable circuit 21 of the delay circuit D1 and the counter 22 of the delay circuit D2 connected to the counter 22, so that the enable circuit 21 of the delay circuit D1 enables the transmitting terminal Tx1 to send the correction setting data to the source drive circuit S-IC1 , And make the counter 22 of the delay circuit D2 start counting the number of packets of the correction setting data. When the counter 22 of the delay circuit D2 counts the number of packets of the correction setting data equal to the number of 3920 packets corresponding to the delay time, the counter 22 of the delay circuit D2 sends a trigger signal to the enable circuit 21 of the delay circuit D2 and the delay circuit connected to the counter 22 The counter 22 of D3 enables the enable circuit 21 of the delay circuit D2 to enable the transmitting terminal Tx2 to send the correction setting data to the source driving circuit S-IC2, and the counter 22 of the delay circuit D3 starts counting the number of packets of the correction setting data. The counter 22 of the delay circuit Dn is triggered after receiving the trigger signal. When the counter 22 of the delay circuit Dn counts the number of packets of the correction setting data equal to the number of 3920 packets corresponding to the delay time, the counter 22 of the delay circuit Dn sends the trigger signal to The enabling circuit 21 of the delay circuit Dn enables the enabling circuit 21 of the delay circuit Dn to enable the transmitting terminal Txn to send the correction setting data to the source driving circuit S-ICn.

In another example, when the clock control circuit 2 sends the correction setting data through the transmitting terminal Tx1, the counter 22 of the delay circuit D1 starts counting time. When the time counted by the counter 22 of the delay circuit D1 is equal to the delay time 11.76μs, the counter 22 of the delay circuit D1 sends a trigger signal to the enable circuit 21 of the delay circuit D1 and the counter 22 of the delay circuit D2 connected to the counter 22 to make the delay circuit The enabling circuit 21 of D1 enables the transmitting terminal Tx1 to send the correction setting data to the source driving circuit S-IC1, and the counter 22 of the delay circuit D2 starts counting for a period of time. When the time counted by the counter 22 of the delay circuit D2 is equal to the delay time 11.76μs, the counter 22 of the delay circuit D2 sends a trigger signal to the enable circuit 21 of the delay circuit D2 and the counter 22 of the delay circuit D3 connected to the counter 22 to make the delay circuit The enabling circuit 21 of D2 enables the transmitting terminal Tx2 to send the correction setting The data is sent to the source driving circuit S-IC2, and the counter 22 of the delay circuit D3 starts counting for a period of time. When the counter 22 of the delay circuit Dn receives the trigger signal and is triggered, when the time counted by the counter 22 of the delay circuit Dn is equal to the delay time 11.76 μs, the counter 22 of the delay circuit Dn sends the trigger signal to the enable circuit 21 of the delay circuit Dn. , Enabling the enabling circuit 21 of the delay circuit Dn to enable the transmitting terminal Txn to send the correction setting data to the source driving circuit S-ICn.

In other words, the sending ends Tx1, Tx2,..., Txn of the clock control circuit 2 sequentially send correction setting data to the source drive circuits S-IC1, S at every delay time or the number of packets corresponding to the delay time. -IC2, S-IC3,..., S-ICn. It is understandable that the display device and its automatic correction method provided by the present invention stagger the time when each sending terminal Tx1, Tx2,..., Txn in the clock control circuit 2 sends the correction setting data, and therefore can also stagger S-IC1, S-IC2, S-IC3,..., S-ICn respond to the clock control circuit 2 time, which greatly shortens the automatic calibration time of the display device.

In step S7, each source driving circuit S-IC1, S-IC2, S-IC3,..., S-ICn receives the calibration setting data for calibration and after the calibration setting time has elapsed, each source driving circuit S-IC1, S-IC2, S-IC3,..., S-ICn send a correction signal A to the clock control circuit 2 within the delay time after the set time of continuous correction to inform whether the correction is completed. When the timing control circuit 2 receives a high-potential correction signal A of the source drive circuits S-IC1, S-IC2, S-IC3,..., S-ICn, it represents the source drive circuits S-IC1, S -IC2, S-IC3,..., S-ICn calibration is completed. When the timing control circuit 2 receives a low-potential correction signal A of the source drive circuits S-IC1, S-IC2, S-IC3,..., S-ICn, it represents the source drive circuits S-IC1, S -IC2, S-IC3,..., S-ICn are not corrected. When the source drive circuit S-IC1, S-IC2, When S-IC3,..., S-ICn is not corrected, the source drive circuit S-IC1, S-IC2, S-IC3,..., S-ICn repeats the next correction after the connection delay time Perform calibration within the set time and send the calibration signal A to the clock control circuit 2 within the next delay time after the next calibration set time continues until the clock control circuit 2 receives the source drive circuits S-IC1, S-IC2 High-potential correction signal A of S-IC3,..., S-ICn.

In an example, the source driver circuit S-IC1 receives the calibration setting data for calibration and the calibration setting time (calibration setting time 1, CST1) has elapsed. The delay of the source driver circuit S-IC1 after the calibration setting time CST1 Within the time (delay time, DT1), a correction signal A is sent to the clock control circuit 2 to inform whether the correction is completed. When the timing control circuit 2 receives the high-potential correction signal A of the source drive circuit S-IC1, it represents that the source drive circuit S-IC1 has been calibrated. The clock control circuit 2 stops sending the correction setting data to the source drive circuit S-IC1 within the next correction setting time after the connection delay time DT1.

In another example, after the source drive circuit S-IC2 receives the correction setting data for correction and the correction setting time CST1 has passed, the source drive circuit S-IC2 sends a correction within the delay time DT1 after the correction setting time CST1. The signal A is sent to the clock control circuit 2 to inform whether the correction is completed. When the timing control circuit 2 receives the low-potential correction signal A of the source drive circuit S-IC2, it means that the source drive circuit S-IC2 has not been corrected. The clock control circuit 2 sends the correction setting data to the source drive circuit S-IC2 in the next correction setting time CST2 after the delay time DT1. After the source driving circuit S-IC2 receives the calibration setting data for calibration and the calibration setting time CST2 has elapsed, the source driving circuit S-IC2 sends a calibration signal A to the clock within the delay time DT2 after the calibration setting time CST2 The control circuit 2 informs whether the correction is completed. when When the clock control circuit 2 receives the high-potential correction signal A of the source drive circuit S-IC2, it represents that the source drive circuit S-IC2 has been calibrated.

In another example, after the source drive circuit S-ICn receives the correction setting data for correction and the correction setting time CST1 has elapsed, the source drive circuit S-ICn sends a correction within the delay time DT1 after the continuous correction setting time CST1 The signal A is sent to the clock control circuit 2 to inform whether the correction is completed. When the timing control circuit 2 receives the low-level correction signal A of the source drive circuit S-ICn, it represents that the source drive circuit S-ICn has not been corrected. The clock control circuit 2 sends the correction setting data to the source driving circuit S-ICn in the next correction setting time CST2 after the delay time DT1. After the source driving circuit S-ICn receives the calibration setting data for calibration and the calibration setting time CST2 has elapsed, the source driving circuit S-ICn sends a calibration signal A to the clock within the delay time DT2 after the calibration setting time CST2 The control circuit 2 informs whether the correction is completed. When the timing control circuit 2 receives the low-level correction signal A of the source drive circuit S-ICn, it represents that the source drive circuit S-ICn has not been corrected. The clock control circuit 2 sends the correction setting data to the source driving circuit S-ICn in the next correction setting time CSTm-2 after the delay time DTm-1. After the source driving circuit S-ICn receives the calibration setting data for calibration and the calibration setting time CSTm-2 has elapsed, the source driving circuit S-ICn sends a signal within the delay time DTm-2 after the continuous calibration setting time CSTm-2 The correction signal A is sent to the clock control circuit 2 to inform whether the correction is completed. When the timing control circuit 2 receives the high-potential correction signal A of the source drive circuit S-ICn, it represents that the source drive circuit S-ICn has been corrected. That is, when the source driver circuit S-ICn is not calibrated, the source driver circuit S-ICn repeatedly performs calibration within the next calibration setting time after the connection delay time and after the next calibration setting time is continued. Next extension The correction signal A is sent to the clock control circuit 2 in the delay time until the clock control circuit 2 receives the correction signal A of the high potential of the source drive circuit S-ICn.

It can be understood that each of the source drive circuits S-IC1, S-IC2, S-IC3,..., S-ICn receives the correction setting data for correction and sends the correction signal A to the upper limit of the clock control circuit 2. The number of times is m times, where m is preferably 10. However, those skilled in the art can determine the upper limit of the number of corrections performed by the source driving circuit according to actual needs, and the invention of this case is not limited thereto.

In an example, the upper limit m of corrections performed by the source drive circuit is 10 times, the total number of packets sent for the correction setting data is 94080 packets, the length of each packet is 9 unit cycles, the data transfer rate is 3Gbps, and the correction Under the condition that the setting time is 282.24μs, the delay time is 11.76μs, and the number of source drive circuits S-IC1, S-IC2, S-IC3,..., S-ICn is 24, the traditional automatic calibration method The time required is 282.24*10*24=67737.6μs, and the time required for the automatic calibration method of the display device 1 provided by the present invention is 11.76*(24-1)+(282.24+11.76)*24=3210.48 μs, therefore, the automatic calibration method of the display device 1 provided by the present invention does greatly shorten the time for the automatic calibration of the display device 1.

In summary, the display device and the automatic correction method provided by the present invention stagger the time for each transmitting end in the clock control circuit to send the correction setting data, and at the same time reserve the time for each source drive circuit to respond to the correction signal. The time can greatly shorten the automatic calibration time of the display device, and at the same time, the clock control circuit can receive the calibration signal returned by each source driving circuit without overlapping problems.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field of the present invention will not deviate from the essence of the present invention. Within the scope of Shenhe, some changes and modifications can be made. Therefore, the scope of protection of the present invention shall be subject to those defined by the attached patent scope.

1: display device

2: Clock control circuit

S-IC1, S-IC2, S-IC3,..., S-ICn-2, S-ICn-1, S-ICn: source drive circuit

Tx, Tx1, Tx2, Tx3,..., Txn-2, Txn-1, Txn: sender

Rx: receiving end

Claims (8)

A display device includes: a clock control circuit having a plurality of transmitting terminals and a receiving terminal; and a plurality of source driving circuits coupled to the clock control circuit, wherein each of the source driving circuits has a receiving terminal And a sending end, the receiving ends of the source driving circuits are sequentially and individually connected to the sending ends of the clock control circuit, and the sending ends of the source driving circuits are electrically connected to each other Afterwards, it is electrically connected to the receiving end of the clock control circuit; wherein the clock control circuit calculates each of the source drive circuits to calibrate a number of packets based on a data transfer rate and a total number of sent packets of a calibration setting data Calibration setting time, calculating a delay time and the number of packets corresponding to the delay time according to the calibration setting time and the number of the sending ends of the clock control circuit, and counting every time according to the order of the sending ends of the clock control circuit The number of packets of the calibration setting data is equal to the number of packets corresponding to the delay time, or when a time is equal to the delay time, the calibration setting data is sent to the source driving circuits; wherein, each of the source driving circuits After receiving the calibration setting data for calibration and the calibration setting time has elapsed, each of the source drive circuits sends a calibration signal to the clock control circuit within the delay time after the calibration setting time has elapsed to inform whether The calibration is completed; wherein, the delay time is less than the calibration setting time. The display device according to claim 1, wherein when the clock control circuit receives the correction signal of a high potential of a source drive circuit, the source drive circuit is corrected; and when the clock control circuit receives When the correction signal of the source drive circuit is at a low potential, the source drive circuit is not corrected. The display device according to claim 2, wherein when the source driving circuit is not calibrated, the source driving circuit repeatedly performs calibration within the next calibration setting time after the delay time is continued, and continues to the next calibration setting time. The correction signal is sent to the clock control circuit within the next delay time after the set time is corrected until the clock control circuit receives the correction signal of the high potential of the source drive circuit. The display device according to claim 1, wherein the clock control circuit includes: a plurality of delay circuits, each of the delay circuits is electrically connected to each other in sequence and is individually electrically connected to the sending ends of the clock control circuit , Each of the delay circuits includes: an enabling circuit configured to be electrically connected to a transmitting end of the clock control circuit; and a counter configured to be electrically connected to the enabling circuit; wherein A plurality of counters are electrically connected to each other in sequence; wherein, when the clock control circuit sends the correction setting data through the transmitting end, the counter of a delay circuit counts the number of packets of the correction setting data or counts the time, and When the counter counts the number of packets of the correction setting data equal to the number of packets corresponding to the delay time or the time is equal to the delay time, the counter sends a trigger signal to the enable circuit and another delay circuit connected to the counter The counter of the enabling circuit enables the sending end to send the correction setting data, and the counter of the other delay circuit starts counting the number of packets of the correction setting data or counting a period of time. An automatic correction method is applied to a display device including a clock control circuit and a plurality of source driving circuits, wherein the clock control circuit has a plurality of sending ends and a receiving end, and the source driving circuits are coupled to the time Pulse control circuit, each of the source drive circuits has a receiving end and a sending end, and the multiple receiving ends of the source drive circuits are sequentially and individually connected to the clock control The transmitting ends of the control circuit, the multiple transmitting ends of the source driving circuits are electrically connected to each other after being electrically connected to the receiving end of the clock control circuit, the automatic correction method includes: according to a data transmission rate and A total number of sent packets of the calibration setting data is calculated for each of the source drive circuits to calibrate a calibration setting time; according to the calibration setting time and the number of the sending ends of the clock control circuit, a delay time and the corresponding The number of packets that should be delayed for time; according to the sequence of the sending ends of the clock control circuit, each packet of the correction setting data is counted equal to the number of packets corresponding to the delay time or sent when a time is equal to the delay time The calibration setting data is sent to the source driving circuits; and after the calibration setting data is received and the calibration setting time has elapsed, a calibration signal is sent to the clock control circuit within the delay time after the calibration setting time has elapsed To inform whether the calibration is completed; wherein, the delay time is less than the calibration setting time. The automatic correction method according to claim 5, wherein when the correction signal of a high potential of a source drive circuit is received, the source drive circuit is corrected; and when the low potential of the source drive circuit is received When the signal is corrected, the source drive circuit is not corrected. The automatic calibration method according to claim 6, wherein when the source driver circuit is not calibrated, the source driver circuit repeatedly performs calibration within the next calibration setting time after the delay time is continued, and continues the next calibration. The correction signal is sent to the clock control circuit in the next delay time after a correction setting time until the clock control circuit receives the correction signal of the high potential of the source drive circuit. The automatic correction method according to claim 5, wherein the clock control circuit includes: A plurality of delay circuits, each of the delay circuits is electrically connected to each other in sequence and is individually electrically connected to the transmitting ends of the clock control circuit, wherein each of the delay circuits includes: a uniform energy circuit configured to be electrically Connected to a transmitting end of the clock control circuit; and a counter configured to be electrically connected to the enabling circuit; wherein, a plurality of counters of the delay circuits are electrically connected to each other in sequence; wherein, when the clock is controlled When the sending end of the circuit sends the correction setting data, the counter of a delay circuit counts the number of packets of the correction setting data or counts the time, and when the counter counts the number of packets of the correction setting data is equal to the corresponding delay time When the number of packets or the time is equal to the delay time, the counter sends a trigger signal to the enable circuit and the counter of another delay circuit connected to the counter, so that the enable circuit enables the transmitter to send the correction Setting data, and making the counter of the other delay circuit start counting the number of packets of the correction setting data or counting a period of time.

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