TW201203198A - Transmission interface and transmission method for display apparatus - Google Patents

Abstract

A transmission interface and transmission method for display apparatus is provided. The transmission method includes the following steps. First, a clock signal is embedded into a data signal sequence by a particular data format, wherein the data signal sequence includes a plurality of data sectors, and each data sector includes a plurality of pixel signals. These pixel signals are divided into a plurality of pixel signal sector. Second, transmit the data signal sequence to the source driver to drives a display panel.

Description

201203198

^1.^1〇.〇〇21^ 34327twf.doc/I VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a signal transmission interface and a signal transmission side thereof, and particularly relates to A signal transmission interface of a display device and a signal transmission method thereof. [Prior Art] • Display panel technology has become more and more mature in recent years, but with the demand of consumers, the size of display panels is getting bigger and bigger, and the resolution is getting higher, but the resolution and size of display panels are increasing. This will cause the operating frequency inside the panel to become higher and higher. Traditional display panel internal transmission interface (intra_panel interfaee) Because multiple pairs of transmission lines are required, it is difficult to make each transmission line have similar electrical properties in a high frequency environment; therefore, the receiving end does not easily make an effective correction mechanism for this. Therefore, the bit error rate cannot be lowered. More _, the system requires additional costs to deal with this problem, and the competitiveness of the product cannot be improved. Traditional transmission interfaces, such as the RSDS (Reduced Swing Differential Signaling) transmission interface, are connected in the form of a transmission pair, which can be reduced to a small amplitude, thereby supporting high frequency applications and generating smaller

Electromagnetic interference (EMI). The transmission interface of ppDS (Pomt-to-P〇int Differential Signaling) is a single-point-to-single-point transmission mode. The load on the transmission side is lighter and easier to control, and for a single source driver. There are fewer: J^l-TW 34327twf.d〇(vl 201203198 := take i say::ϊ:: all must be accompanied by an additional clock signal is transmitted through different transfer lines d' due to time gland and data In the case of pulse skew (clockskew), there may be electromagnetic interference and time problems. The invention provides a magnetic interference and reduces the bit error rate. The signal transmission method of the electric type display device can be reduced, wherein the display device and the display panel are firstly displayed. The signal transmission method is designed to be embedded in a data (four) sequence by the Izaki-specific format, wherein (4) (4) The ship segment, each of which includes a plurality of halogen signals 'These halogen signals are driven by the j-driver to drive the display panel. The sequence of the batch number is transmitted to the source to drive the signal transmission interface of the display device. Display _ No panel. The signal transmission interface includes a timing controller and a source _ device. The timing control receives the "data signal sequence" and the - clock information is __ specific data grid nucleus data signal sequence. The sequence of numbers includes a plurality of (four) segments, and each of the S segments includes a plurality of sacred money. The health symbols are separated by a plurality of sinusoidal signal segments. The signal sequence drives the display panel. 扪育枓201203198

Ruvi-ζυ 10-0021 - TW 34327twf.doc/I In one embodiment of the invention, each of the above-described pixel signal segments includes two pixel signals. In the embodiment of the invention - each of the above-described pixel signals is a bit signal of a χ bit, where X is a positive integer. In an embodiment of the invention, the specific data format includes a bit signal of a Μ bit located at a beginning of each pixel signal segment, and a bit

The bit signal of the Ν bit at the end of each 信号 signal segment, where Μ, Ν are positive integers. In one embodiment of the invention, Μ=Ν=2, and the bit at the beginning is 11§11, and the bit signal at the end position is 〇〇. In an embodiment of the invention, wherein M = 1 and Ν = 2, and the bit 7L signal at the beginning position is 1, the bit data at the end position is 〇〇. In an embodiment of the present invention, each of the data segments further includes a start signal, a plurality of control signals, and a dummy signal, and the start signal, the control signal, and the lease signal are bits without bits. Number, ί I integer. The start signal, the control signal correction and the sub-signal are respectively separated by the clock/sleeve: the format is divided into a start signal area, an evening control signal section and a 0 sub-signal section, wherein Start == the beginning position of the section, and the touch section is in the clear area, ^ in the above, this (four) will be the meaning of the signal embedded signal sequence sample 1 page with the clock signal transmission line to take the reduction of the data The electromagnetic interference problem of the meta-transmission interface during high-frequency operation

201203198... 34327 twf.doc/I The above features and advantages of the present invention will become more apparent from the following detailed description. [Embodiment] FIG. 1 is a schematic diagram of a signal transmission interface of a display device according to an embodiment of the present invention. 2 is a flow chart of a signal transmission method of a display panel according to an embodiment of the present invention. The signal transmission method of the display panel will be described below with reference to Figs. 1 and 2, and please refer to Fig. 1 and Fig. 2 at the same time. The signal transmission interface of the display device 1A includes a timing controller 104 and a source driver 1〇6. The signal transmission method steps of the display panel 102 are as follows. First, the timing controller 104 receives a data signal sequence S1 and embeds a clock information in a specific data format into the data signal sequence S1 (step S2〇2) c> source The driver 1〇6 drives the display panel 1〇2 according to the data signal sequence S1 embedded with the clock information (step S204), by embedding the clock information into the data signal sequence S\S1 'the timing controller just does not need another The clock signal is transmitted to the source driver 106. The source driver i〇6 can restore the clock signal of the embedded data signal sequence SI by using a delay locked loop (delay 1〇eked 1〇〇p, DLL) or a phase locked loop (PLL). . Because the source driver 106 can correctly read the data from the data signal sequence S1 according to the information in the embedded data signal sequence S1, = drive the display panel 1G2, and the conventional transmission interface operates at high frequency = Electroacupuncture problem. It should be noted that in the present embodiment, it is shown that 1GG only includes 1% of the crane, but it is not limited thereto. In other embodiments, the display device_ may include more source drivers 201203198

The HM-ZU10-0021-TW 34327twf.doc/I actuator 106' can effectively drive the pixels on the display panel 1〇2 when the singularity of the display panel 1〇2 is large. In detail, the data signal sequence S1 can be as shown in FIG. The data signal sequence S1 includes a plurality of data segments daI, wherein each data segment DA1 includes a start 彳§ number, a dummy signai, a plurality of control signals, and a plurality of tiling <§ numbers, and the signals Separated by the clock information into a start signal segment DS1, a dummy signal segment DU1, a plurality of control signal segments £) (: 1 (in this embodiment, two control signal segments DC1), and a plurality of pictures The signal segment DP1, wherein the start signal segment DS1 is located at the beginning of the data segment DA1 to indicate the start time of the data segment DA1, and the nickname segment Dm is located at the end of the data segment DA1 for indicating The control signal in the control signal section DC1 carries information controlled by the panel, such as dynamic image adjustment or panel characteristic shift adjustment, etc. In addition, the halogen display panel 102 in the pixel signal section Dpi The data of the pixel is notable. In this embodiment, the position of the control signal section DC1 is in front of the 33 signal (10), and the position of the suffix section. The position 'for example, may be followed by the start letter. Said that each of the above starting signals Dm is in the control signal section DC1 and drawn as a packet, and the format slave DP1 of the packet can be designed according to the requirements. For example, Figure 4A shows the packet format of the signal area. Reference

34327twf.doc/I 201203198 Λ ΛΛ · Λ. In the example, each pixel signal segment DPI includes two pixel signals, but not limited thereto. In other embodiments, the pixel signal segment DPI may include more The pixel signal (for example, three pixel signals) When the format of the source driver 1〇6 is 6 bits, the packet format of the pixel signal segment DPI is 16 bits for one packet. The packet includes two packets. a 6-bit pixel signal pi and P2, and a bit signal "11" at the beginning of the pixel signal segment Dpl and a bit signal "〇〇" at the end of the pixel signal segment DPI are embedded. Clock information. When the source driver 1〇6 detects a bit signal (ie, “u”) of two consecutive high voltage levels in the pixel signal section DPI, the pole driver 106 can thereby It is known that the bit k after the bit signal "u" is a halogen data, and accordingly, the display panel 1〇2 is driven. When the source driver 106 detects two consecutive lows in the pixel signal section Dpi. When the voltage level is at the signal (ie, "〇〇"), the source driver 1〇6 can know that the packet has been After the transfer is completed, similarly, when the format of the source driver 1〇6 is 8 bits or 1 bit, 7 and P2 in the pixel signal segment Dpi are 8 bits and 1 () bits, respectively. The embedded (four) pulse ^ U", "00" is 4 bits, so the packet format is 2 〇 ^ yuan 24 bits. 4 It is worth noting that this embodiment uses 6 bits, 8 bits == The numbers Γ and Ρ2 are used as examples to describe the signal transmission method. The person with normal knowledge can adjust the number of bits of 昼2遽Ρ卜Ρ2 according to the actual situation. In addition, the above-mentioned setting of the end position is also a separate signal. Not limited to 11" or "00", the general knowledge in this field can be relied on 201203198

Nmw! 0-0021 ·Τψ 34327twf.doc/I adjust its bit number and bit value. For example, the bit signal placed at the beginning of each segment may be "", and the bit TG signal placed at the end position and the end position of each segment is "〇〇", so that the signals may be separated. To set the bit signal of the end position to "〇〇" (that is, two consecutive low voltage levels) can prevent the ink level of the signal from falling too slowly, so that the source driver 106 can not discriminate the low logic voltage. The level is wrong, and the signal is misjudged. Similarly, other signals (starting signal, dumb and control signal) in the data section DA1 can also be embedded in the same way as the clock information is displayed. The clock information is "u", "〇〇" The dummy signal segments are separated by placing them at the beginning and end of the epidemic signal. The slightly signal segment leg generated by the clock information being embedded and separated is different from the above-mentioned pixel (4) segment DPI in that the pixel signal segment includes two pixel signals ' while the health segment Dm only The number including the number 'and the postal number is the picture money _ times. ^ Similarly, in Fig. 4C, the clock information "11" and "〇〇" are respectively placed at the beginning and the end of the start signal to separate the start__long segment DS1. The starter segment DS1 separated by the clock information is different from the above-described pixel signal segment DP1 in that the pixel signal segment DPI includes two pixel signals, and the wire The signal segment leg includes only one start signal 'and the number of bits of the start signal is twice that of the prime letter *5^. In addition, in FIG. 4D, the clock information ru" and "(8)" are also placed at the beginning and the end of the control signal to separate the control signal section DC, which is separated by the clock information embedded. letter

34327twf.doc/I 201203198 segment DC1 is different from the above-described pixel signal segment DPI in that the pixel signal segment DPI includes two pixel signals, and the control signal segment DC1 includes only one control signal, and The number of bits of the control signal is twice that of the halogen signal. FIG. 5 is a schematic diagram of a source driver according to an embodiment of the invention. Referring to Fig. 5', the source driver 5 (8) includes a serial to parallel conversion unit 5〇2 and a plurality of pixel allocation units. The serial-to-parallel conversion list is transmitted to the pixel signal distribution unit 504 through the data transmission and the UI. Each of the pixel signal distribution units 5〇4 includes a latch 丨, a latch LA2, a switching device sw, a switching device SW2, a digital analog conversion DAC, a digital analog converter DAC2, a buffer muscle, and a buffer BF2. The input terminals of the flash locker LA1 and the (10) device LA2 are respectively connected to the data transmission lines L1 and L2. Turn off the device just _ flash lock LA1 and off the output of If LA2. The open operation_ operates in the first connection state and the second connection state. In the first connection state, the output of the switching device SW1 to the LA1. is connected to the input of the digital converter DAC1, and the output is connected to the input of the digital analog converter DAC2. In the second connection state, the switching device _ connects the output of the flash locker 1^1 to the input terminal of the digital ship conversion II DAC2 and the output terminal of the LA2 to the input terminal of the digital DAC1. The digital analog converter DAC1 and the buffer BF allow the digital analog converter DAC^ BF2 to be connected in series between the switching device sw 1 and the switching device sW2, 201203198

HM-2O10-0021-TW 34327twf.doc/I The switch device SW2 is lightly connected to the halogen on the display panel 102. The operation of the switching device SW2 is similar to the switching device swi. The serial to parallel conversion unit 502 is configured to convert the data format of the received signal from a serial form to a parallel form. The digital analog converter DAC1 is negatively coupled to the coupled buffer BF1 to generate a positive polarity voltage, and the digital analog converter DAC2 is negatively coupled to the coupled buffer bf2 to generate a negative polarity voltage. The switching devices SW1 and SW2 are used to transmit the gold distribution of the positive polarity voltage and the negative polarity voltage to the display panel 102 when the display panel 1〇2 performs polarity inversion. When the serial-to-parallel conversion unit 502 receives the material signal sequence S1 from the timing controller 1〇4, the serial-to-parallel conversion unit 5〇2 outputs the data in the data signal sequence S1 from the serial data. The form is converted into a parallel data form and transmitted to the latch LA1 and the latch LA2 in the pixel signal distribution unit 504 by output to the data transmission lines L1 and L2, respectively, to the latch LA1 and the latch LA2. The halogen data is output to the pixels on the display panel 102 in the form of analog signals via the switching device SW1, the digital analog converter DAC1, the DAC2, the buffer bF1, the buffer BF2, and the switching device SW2. The display panel 1 〇 2 displays the surface of the pixel signal S1 in the data signal sequence S1 by using a signal transmission method according to an embodiment of the present invention. The column-to-parallel conversion unit 502 sequentially transmits the pixel signals to the pixel signal distribution unit 504 in cooperation with the data transmission wheels L1 and L2 to distribute the pixel data to the display panel 1〇2, for example, the respective pixel segments 11

The halogen signal P1 in uil-TW 34327twf.doc/I 201203198 ^ is transmitted by the data transmission line L1, and the pixel signal 卩2 in the DPI of each picture segment is composed of the data transmission line um, which is only one used compared with the conventional one. The data transmission line transmission 昼 = new queue mode to transmit the pixel signal can greatly improve the update speed of the display screen. In other embodiments, the data in the data signal sequence S1 can be separated into three segments for every three pixel signals, and the string is transmitted to the i column and the L2 signal is transmitted to the early element 5 〇4' to assign pixel data to the display panel. However, this method will cause the serial to parallel conversion unit 5〇2 benefit method to sequentially assign the pixel signals in each pixel signal segment to a specific resource. The transmission line 'has to add a program that combines the signals to be transmitted to the display panel in the correct order, so that the circuit design of the serial to parallel conversion early 7G 502 is more complicated. In summary, the transmission interface of the embodiment of the present invention can reduce the electromagnetic drying problem of the traditional transmission interface during high-frequency operation by reducing the sampling of the data of the clock signal transmission. The bit is wrong. In the case where each element = segment includes two signals, the signal transmission method is applied, and the source drivers of the two data transmission lines can greatly improve the update speed of the display surface. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. , therefore this 12 201203198

, 0-002l-TW 34327twf.doc/I The scope of protection of the invention is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a signal transmission interface of a display device according to an embodiment of the present invention. Fig. 2 is a flow chart showing a signal transmission method of a display panel according to an embodiment of the present invention. • Figure 3 is a schematic diagram of a data signal sequence in accordance with an embodiment of the present invention. 4A is a schematic diagram of a packet format of a pixel signal segment according to an embodiment of the present invention. Figure 4B is a block diagram showing the format of a dummy signal segment according to an embodiment of the present invention. 4C is a schematic diagram of a packet format of a start signal segment according to an embodiment of the present invention. 4D is a schematic diagram of a packet format of a control signal segment according to an embodiment of the present invention. Injury Figure 5 is a schematic view of a source body actuator according to an embodiment of the present invention. [Main component symbol description] 1〇〇: display device 102: display panel 104: timing controller 106, 500: source driver 502: serial to parallel conversion unit 13

U21-TW 34327twf.doc/I 201203198 504 : prime signal distribution unit DA1 : data section DU1 : dummy signal section DS1 : start signal section DPI : 昼 signal section DC1 : control signal section PI, P2 : Alizarin signal S1: data signal sequence LAI, LA2: latch U, L2: data transmission line DAC1, DAC2: digital analog converter SW1, SW2: switching device BF BF2: buffer S202 ~ S204: display panel Signal transmission method steps

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Claims (1)

201203198 .0-0021- 34327twf.doc/I VII. Patent application: 1. A signal transmission method for a display device, the display device includes a source driver and a display panel, and the method includes ···-clock information Embedding a data column in a data format, wherein the data signal sequence includes a plurality of data segments, each of the ancestor segments includes a plurality of pixel signals, and the pixel signals are signaled by the clock signal. Segment; and month % knife h is the display surface ^ The data signal sequence is transmitted to the source driver to drive the display 2. For example, please use the letter method of the display device described in the full-time item, wherein each of the pixel signals The segment includes two pixel signals, a square i 1 term (4), and a signal signal in which each of the pixel signals is a bit cell, wherein X 4· is as described in the third paragraph of the patent application. The display device's = method, wherein the specific data format is included in each of the 昼 信 letters. The bit position of the head position is from the bit signal of the N bit located at the end of each of the pixel segments, where M and N are positive integers. . 5. The signal transmission of the display device according to item 4 of the patent application, wherein the method (4) = 2, and the bit signal at the beginning position is u, and the bit signal at the tail position is 〇〇. π 6 broadly applies the display device 2 method described in item 4 of the patent scope, wherein (4) and Ν=2, and the bit data of the position of the bit signal at the beginning position is 〇〇. </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; The start signal, the plurality of control letters, and ... the Asian money, and the starting money, the control numbers, and the bit signal of the health symbol of 2X bits, χ is a positive integer, the starting letter says the Controlling the money and touching the money are embedded in the data format by the clock and are divided into the wire trust segment, the plurality of control signal segments and the -3⁄4 segment, and the towel is simply recorded in the money section. The beginning of the section, and the section is at the end of the data section. The two magnetics include - a timing controller, a receive-data signal sequence, and a clock: its _ segment; No. The signals are separated into letters by the clock information. The column drive, according to the information of the clock information I η. as shown in Figure 8 (4) of the display device signal 16 201203198 34327twf.doc/I ΗΜ-2υι〇-〇〇2ΐ- the interface, where The specific data format includes a bit of the first position of the first position ^ a bit of the position of the end of the pixel signal segment, = the pixel signal area 12. as described in the scope of claim 5; The interface, where, and at the beginning of the position, the bit signal at the end of the number is 〇〇. .旒 is 1 track i3· The transmission interface of the display device described in item 11 of the patent scope is 'wherein VI=1 and N=2, and the bit data of the position where you stop at the end of ° is 00 . The bit signal at the beginning position is ^the signal transmission side of the display device described in item 8 of the patent scope, wherein each of the data segments further includes a start signal, a multi-health and a health sign and the start signal The control signals and the = sign are 2X bit age signals, χ is positive, and the start signal, the d control signal, and the epidemic signal are respectively embedded in the specific data format by the clock information and are respectively separated into - The start letter segment, the multi-signal signal region= and the dim signal segment, wherein the start signal segment is located at a beginning of the data segment, and the dummy signal segment is located at an end of the data segment. 17