TWI444115B - Printed circuit board and chip system - Google Patents

Description

Printed circuit board and wafer system

This invention relates to wafer systems, and in particular to trace architectures for wafer systems.

In today's wafer system technology, multilayer printed circuit boards (PCBs) are widely used due to their high fan-out, high trace density and small footprint. In general, on small packaged wafers, such as processor units used in portable devices, the number of pins should be as small as possible to save floor area. However, wafers with a small number of pins may cause problems in some systems, especially when the wafer is mounted on a smaller number of printed circuit boards. For example, due to tight wiring and fewer ground pins, there is a longer current return path, which results in stronger radiated electromagnetic interference, longer signal paths, and poor signal integrity. In addition, trace layouts are typically routed on printed circuit boards with fewer pin counts, fewer layers, and smaller integrated ball pitch. It will become more complicated.

Figure 1A is a top view of a conventional Ball Grid Array (BGA) wafer system. Fig. 1B is a cross-sectional view of the conventional BGA wafer system shown in Fig. 1A taken along the AA' direction. As shown in FIG. 1A, on a two-layer PCB 200, an array of bond pads (210) and ground pads 30 are formed, on which the wafer 100 is placed. Wafer 100 includes a plurality of pins 10 (shown partially on FIG. 1B) with pins 10 electrically coupled to the bond pads 210 and the ground pads 30. Multiple first layer trace A pattern of (trace) 215 is formed in the first layer in the double layer PCB 200. A pattern of a plurality of second layer traces 225 (indicated by dashed lines) is formed in the second layer of the dual layer PCB 200. A plurality of vias 220 are formed between the first layer and the second layer of the dual layer PCB 200, and are partially shown in FIGS. 1A and 1B. Portions of the bond pads 210 at the edges of the array are connected to the first layer traces 215, respectively. The portion of the bond pads 210 and the ground pads 30 located in the center of the array are electrically connected through one of the holes 220 and one of the second layer traces 225. Referring to FIGS. 1A and 1B, a current return path from one of the bond pads 210 to the ground pads 30 typically passes through a portion of the holes 220 and the second layer traces 225. A long-distance current return path with two layers of windings exacerbates radiated electromagnetic interference. Therefore, there is a need to provide an improved electrical path to the wafer system to mitigate radiated electromagnetic interference and increase the flexibility of the signal, power or ground traces of the wafer system.

In view of this, the present invention provides a printed circuit board and a wafer system to solve the above problems.

The invention discloses a printed circuit board for mounting a wafer, comprising: a plurality of bonding pads mounted on the printed circuit board and the plurality of pins electrically connected to the chip, wherein the pins in the chip comprise a plurality of pins A pin and a functional pin are used; and a trace disposed on the printed circuit board, the trace being connected to the bond pads of the unused pins and forming a conduction path.

The invention further discloses a wafer system comprising a wafer, the wafer A plurality of pins mounted on the wafer are included, and the pins of the chip include unused pins and functional pins. The unused pins are not isolated from the functional circuitry on the wafer, or are at least one un-enabled circuit electrically coupled to the wafer. A printed circuit board carrying the wafer is provided and includes a plurality of bond pads disposed on the printed circuit board and electrically connected to corresponding unused pins. Traces disposed on the printed circuit board pass through portions of the bond pads to form a conductive path.

By using the printed circuit board and the wafer system provided by the invention, the electromagnetic radiation interference of the wafer system can be effectively alleviated and the signal quality can be improved.

The methods of making and using various embodiments of the present invention are discussed in detail below. However, it is to be noted that many of the possible inventive concepts provided by the present invention can be implemented in various specific ranges. These specific examples are merely illustrative of the methods of making and using the invention, but are not intended to limit the scope of the invention.

Figure 2A is a top plan view of an embodiment of the wafer system of the present invention. Fig. 2B is a cross-sectional view of the wafer system in Fig. 2A taken along the BB' direction. The wafer system includes a wafer 100 in which a plurality of pins are mounted on a bottom surface of the wafer 100. The pins include a functional pin 10 and an unused pin 20 (partially shown in FIG. 2B), wherein the functional pins 10 are electrically coupled to the functional circuitry of the wafer 100. Each of the functional pins 10 can function as a ground node, a signal input/output terminal or a power input terminal of the functional circuit. The unused pins 20 are not electrically isolated from any functional circuitry on the wafer 100, or are electrically connected to the wafer 100. One of the unenabled circuits. For clarity of the drawings, the pins are not shown in Figure 2A and in Figure 2B.

The wafer system further includes a PCB 200 in which a plurality of bond pads are disposed on a portion of the PCB 200 to carry the wafer 100. The bond pads include a plurality of ground pads 30 (including a ground pad 30a), a plurality of unused bond pads 40, and a plurality of functional bond pads 50 (including a functional bond pad 50a). Each of the bond pads is electrically connected to a corresponding pin on the wafer 100, wherein the ground pads 30 are electrically connected to the ground node on the wafer 100 through the corresponding plurality of functional pins 10. The unused bond pads 40 are electrically connected to the unused pins 20. The functional bond pads 50 are electrically connected to the functional pins 10. In this embodiment, the functional bond pad 50a acts as a ground node for the wafer 100. A trace 240 is disposed on the PCB 200, wherein the trace 240 passes through a portion of the unused bond pads 40 to form a conductive path between the ground pad 30a and the functional bond pad 50a. In a preferred embodiment, the unused bond pads 40 and corresponding unused pins 20 are used to form a short conduction path between the ground pad 30a and the functional bond pad 50a. . The trace 240 can be straight or have a corner. The width of the trace 240 may be greater than or equal to the diameter of the pads to provide low impedance, but is not limited thereto. In the present embodiment, the trace 240 is a current return path from the functional bond pad 50a to the ground pad 30a, as shown in FIG. 2B. In Figures 2A and 2B, the trace 240 has a shortened length and does not pass through the second layer in the PCB 200, significantly reducing radiated electromagnetic interference to the wafer system.

Figure 3A shows another embodiment of the wafer system of the present invention. view. Figure 3B is a cross-sectional view of the wafer system of Figure 3A taken along the CC' direction. The wafer system includes a wafer 100 in which a plurality of pins are mounted on the bottom surface of the wafer 100. These pins include a functional pin 10 and an unused pin 20 (partially shown in Figure 3B), similar to the embodiments of Figures 2A and 2B.

The wafer system of FIGS. 3A and 3B also includes a PCB 200 in which a plurality of bonding pads are disposed on a portion of the PCB 200 to carry the wafer 100. The bond pads include a plurality of ground pads 30 (including a ground pad 30a), a plurality of unused bond pads 40, and a plurality of functional bond pads 50, similar to the embodiments of FIGS. 2A and 2B. The wafer system of FIGS. 3A and 3B further includes an external circuit 250 disposed on the PCB 200. In some embodiments, the external circuit 250 can be a memory device, a picture processing unit, a power supply circuit, or other electronic components mounted on the PCB 200. A trace 240 is disposed on the PCB 200, wherein the trace 240 forms a ground connection between the ground pad 30a and the external circuit 250 through a portion of the unused bond pads 40, as shown in FIG. 3B. .

In a preferred embodiment, the unused bond pads 40 and the corresponding unused pins 20 are arranged to form a shorter conductive path between the ground pad 30a and the external circuit 250. The trace 240 can be straight or have a corner. The width of the trace 240 may be greater than or equal to the diameter of the pads to provide a lower impedance, but is not limited thereto. In the embodiments of FIGS. 3A and 3B, the trace 240 has a shorter length and does not pass through the second layer in the PCB 200, which is the return current between the wafer 100 and the external circuit 250. A ground path is provided to improve electromagnetic radiation interference.

Figure 4A is a top plan view of another embodiment of the wafer system of the present invention. Figure 4B is a cross-sectional view of the wafer system in Figure 4A taken along the DD' direction. The wafer system includes a wafer 100 in which a plurality of pins are mounted on the bottom surface of the wafer 100. These pins include a functional pin 10 and an unused pin 20 (partially shown in Figure 4B), similar to the embodiments of Figures 2A and 2B.

The wafer system of FIGS. 4A and 4B also includes a PCB 200 in which a plurality of bonding pads are disposed on a portion of the PCB 200 to carry the wafer 100. The bond pads include a plurality of ground pads 30, a plurality of unused bond pads 40, and a plurality of functional bond pads 50 (including functional bond pads 50a and 50b), similar to the embodiments of FIGS. 2A and 2B. A trace 240 is disposed on the PCB 200, wherein the trace 240 forms a conductive path between the functional bond pads 50a and 50b by a portion of the unused bond pads 40, as shown in FIG. 4B. Show. In a preferred embodiment, the unused bond pads 40 and the corresponding unused pins 20 are arranged to form a shorter conductive path between the functional bond pads 50a and 50b. The trace 240 can be straight or have a corner. The width of the trace 240 may be greater than or equal to the diameter of the pads to provide low impedance, but is not limited thereto. In the embodiments of Figures 4A and 4B, trace 240 has a shorter length and does not pass through the second layer in PCB 200, reducing electromagnetic interference and improving the signal quality of the wafer system.

Figure 5A is a top plan view of another embodiment of the wafer system of the present invention. Fig. 5B is a cross-sectional view of the wafer system in Fig. 5A taken along the EE' direction. The wafer system includes a wafer 100 in which a plurality of pins are mounted on the bottom surface of the wafer 100. These pins include functional pins 10 and Pin 20 is not used (partially shown in Figure 5B), similar to the embodiment of Figures 2A and 2B.

The wafer system of FIGS. 5A and 5B also includes a PCB 200 in which a plurality of bonding pads are disposed on a portion of the PCB 200 to carry the wafer 100. The bond pads include a plurality of unused bond pads 40, and a plurality of functional bond pads 50 (including a functional bond pad 50a), similar to the embodiments of Figures 2A and 2B. The wafer system of FIGS. 5A and 5B further includes an external circuit 250 disposed on the PCB 200. In some embodiments, the external circuit 250 can be a memory device, a picture processing unit, a power supply circuit, or other electronic components mounted on the PCB 200. A trace 240 is disposed on the PCB 200, wherein the trace 240 forms a conductive path between the functional bond pad 50a and the external circuit 250 through a portion of the unused bond pads 40, as shown in FIG. 5B. . In a preferred embodiment, the unused bond pads 40 and corresponding unused pins 20 are arranged to form a shorter conductive path between the functional bond pad 50a and the external circuit 250. The trace 240 can be straight or have a corner. The width of the trace 240 can be greater than or equal to the diameter of the pads to provide a low impedance, but is not limited thereto. In the embodiments of FIGS. 5A and 5B, the trace 240 has a shorter length and does not pass through the second layer in the PCB 200, and thus is preferably provided between the wafer 100 and the external circuit 250. Signal quality.

In the design of a wafer system, a wafer can be applied to different wafer systems. To provide flexibility in printed circuit board layout design, the present invention further discloses a wafer in which the pins of the wafer have the ability to be exchanged between an unused state and a functional state. Figure 6 is an embodiment of a wafer system including a wafer 100 having (state) exchangeable pins P1 and P2 electrically coupled to PCB 200 via bond pads R1 and R2. The chip 100 includes a power supply 105, a start-up circuit 110, an enabled circuit 120, an un-enabled circuit 130, and a multi-multiplexer (140-1 and 140-2 in the embodiment). The multiplexer circuit 140, wherein the input terminals I _{1 of} the multiplexers 140-1 and 140-2 are electrically connected to an input/output terminal N1 of the enabled circuit 120; the multiplexers 140-1 and 140 The input terminal I _{2 of} -2 is electrically connected to an input/output terminal N2 of the unenabled circuit 130. An output terminal O1 of the multiplexer 140-1 is electrically connected to a pin P1 of the chip 100. An output terminal O2 of the multiplexer 140-2 is electrically connected to a pin P2 of the chip 100. When the power supply 105 provides power to the wafer 100, the startup circuit 110 first has functionality and activates the enabled circuit 120 while the unenabled circuit 130 is not activated. The multiplexer circuit 140 further includes the input/output terminals N1 and N2 and the pins of the enabled circuit 120 and the unenabled circuit 130 according to corresponding control signals (S1 and S2 in the embodiment). An actual connection is established between P1 and P2. As shown in the embodiment of FIG. 6, the input/output terminal N1 of the enabled circuit 120 is connected to the input terminal I _{1 of} the multiplexer 140-1 and the input terminal I of the multiplexer 140-2. ₁ . The input terminal I ₁ is selected by transmitting the control signal S1 to the multiplexer 140-1, and the multiplexer 140-1 is thus established at the output terminal O1 of the multiplexer 140-1 and the enabled circuit. An electrical connection between the input/output terminals N1 of 120. In that manner, the input/output terminal N1 of the enabled circuit 120 is assigned to the pin P1. This pin P1 can thus be set as a functional pin. In addition, the circuit 130 is not enabled on the input / output terminal N2 is connected to the input of the multiplexer 140-1 I ₂ and the input of the multiplexer 140-2 I _2. The input terminal I ₂ is selected by transmitting the control signal S2 to the multiplexer 140-2, and the multiplexer 140-2 is thus established at the output terminal O2 of the multiplexer 140-2 and the unenabled circuit. An electrical connection between the input/output terminals N2 of 130. That way, the input/output terminal N2 of the unenable circuit 130 is assigned to the pin P2. This pin P2 is thus set to an unused pin. The pins P1 and P2 can determine whether the pins P1 and P2 are unused or functional according to the control signals S1 and S2, thereby permitting a conduction path to be formed through a trace of the corresponding bonding pad R1 or R2. The operation of the wafer 100 is not affected. In some other embodiments, a circuit input/output of the wafer 100 can be assigned to one of the plurality of pins via a separate multiplexer, depending on the individual control signals. In some other embodiments, the multiplexers of the wafer 100 can have N inputs to permit one of the N circuit input/output terminals to be assigned to a respective pin, where N is a positive Integer.

The present invention discloses a wafer system having a novel trace design structure. The trace design structure not only effectively mitigates the electromagnetic radiation interference of the wafer system, but also improves the signal quality. The invention further discloses a wafer capable of defining a pin as an unused or functional pin, wherein the printed circuit board layout and design flexibility of the corresponding wafer system are also provided.

The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention. Any one of ordinary skill in the art can make a few changes without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.

10(10a)‧‧‧ functional pins

20‧‧‧Unused pins

30 (30a, 50a, 50b) ‧‧‧ grounding mat

40‧‧‧Unused mat

50‧‧‧ functional mat

100‧‧‧ wafer

105‧‧‧Power supply

110‧‧‧Starting circuit

120‧‧‧Enabled circuit

130‧‧‧Unenabled circuit

140‧‧‧Multiprocessor circuit

140-1, 140-2‧‧‧ multiplexer

200‧‧‧Printed circuit board

210‧‧‧Material pads

215‧‧‧ Trace

220‧‧‧ hole

225‧‧‧Wiring

240‧‧‧Wiring

250‧‧‧External circuit

N1~N2‧‧‧ input/output

I ₁ , I ₂ ‧‧‧ input

O1, O2‧‧‧ output

S1, S2‧‧‧ control signals

P1, P2‧‧‧ pin

R1, R2‧‧‧ joint pads

Figure 1A shows a top view of a conventional ball grid array wafer system; Figure 1B shows a conventional ball grid array wafer system of Figure 1A, a cross-sectional view along the AA' direction; and Figure 2A shows the present invention. 1A is a cross-sectional view of the wafer system of FIG. 2A along the BB' direction; and FIG. 3A is a top view of another embodiment of the wafer system of the present invention; 3B is a cross-sectional view of the wafer system of FIG. 3A along the CC' direction; FIG. 4A is a top view of another embodiment of the wafer system of the present invention; and FIG. 4B is a view of FIG. 4A. The wafer system is a cross-sectional view along the DD' direction; FIG. 5A is a top view of another embodiment of the wafer system of the present invention; and FIG. 5B is a wafer system of FIG. 5A along the EE' A cross-sectional view of the direction; Figure 6 shows an embodiment of a wafer system having pin assignment capabilities.

100‧‧‧ wafer

200‧‧‧Printed circuit board

30(30a)‧‧‧Grounding mat

40‧‧‧Unused mat

50(50a)‧‧‧ functional mat

240‧‧‧Wiring

Claims (14)

A printed circuit board for mounting a wafer, comprising: a plurality of bonding pads disposed on the printed circuit board, the bonding pads being electrically connected to the plurality of pins of the chip, wherein the pins comprise a plurality of unused leads And a plurality of functional pins; and a trace disposed on the printed circuit board, wherein the trace forms a conductive path through a portion of the bond pads connected to the unused pins. The printed circuit board of claim 1, wherein the unused pins are coupled to at least one unenabled circuit on the wafer. The printed circuit board of claim 1, wherein the unused pins are electrically isolated from the plurality of functional circuits on the wafer. The printed circuit board of claim 1, wherein the chip further comprises a multiplexer circuit, wherein an output end of the multiplexer circuit is electrically connected to a corresponding pin, and the multiplexer The circuit defines the corresponding pin as an unused pin or a functional pin according to a control signal. The printed circuit board of claim 4, wherein the multiplexer circuit electrically isolates the corresponding pin from the wafer or electrically connects the corresponding pin to the wafer according to the control signal. At least one of the un-enabled circuits defines that the corresponding pin is an unused pin. The printed circuit board of claim 1, wherein the width of the traces is greater than or equal to the diameter of the bond pads. The printed circuit board of claim 1, wherein the trace is electrically connected to one of a ground pin, a signal input/output pin, and a power input pin of the chip. The printed circuit board of claim 1, wherein the trace is electrically connected to one of a ground node, an input/output node, and a power node in an external circuit. A wafer system comprising: a wafer comprising a plurality of pins, wherein the pins comprise a plurality of unused pins and a plurality of functional pins, and the unused pins and the plurality of functional circuits on the wafer are electrically Separating or electrically connecting to the at least one un-enable circuit on the wafer; and a printed circuit board for mounting the wafer, comprising: a plurality of bonding pads disposed on the printed circuit board, the bonding pads being electrically connected And corresponding to the unused pins; and a trace disposed on the printed circuit board, through a portion of the bonding pads to form a conductive path. The wafer system of claim 9, wherein the wafer further comprises a multiplexer circuit, wherein an output of the multiplexer circuit is connected to a corresponding pin, and the multiplexer circuit is controlled according to a The signal defines the corresponding pin as an unused pin or a functional pin. The wafer system of claim 10, wherein the multiplexer circuit electrically isolates the corresponding pin from the wafer or electrically connects the corresponding pin to the wafer according to the control signal. A circuit is not enabled to define that the corresponding pin is an unused pin. The wafer system of claim 9 wherein the width of the traces is greater than or equal to the diameter of the bond pads. The wafer system of claim 9, wherein the trace is electrically connected to a ground pin, a signal input/output lead in the wafer. One of the pins and a power input pin. The wafer system of claim 9, wherein the trace is electrically connected to one of a ground node, an input/output node, and a power node in an external circuit.