TWI440005B - Slice circuit for generating a slice voltage of a liquid crystal display and method thereof - Google Patents

Description

Chamfering circuit for generating chamfer voltage of liquid crystal display and method thereof

The present invention relates to a chamfering circuit for producing a chamfering voltage of a liquid crystal display and a method thereof, and more particularly to a chamfering circuit capable of generating a chamfering voltage of a liquid crystal display at any point in time and a method thereof.

Please refer to FIG. 1 , which is a schematic diagram of a chamfering circuit 100 applied to a GIP (gate in panel) panel in the prior art. As shown in FIG. 1, the chamfering circuit 100 includes a one-position adjuster 102 and a chamfering unit 104, wherein the chamfering circuit 100 can be built in a power IC. The level adjuster 102 adjusts the level of an input voltage LS_I to generate a first voltage LS. The chamfering unit 104 is coupled to the level adjuster 102 for receiving the first voltage LS and generating a chamfering voltage LS_O according to the first voltage LS, wherein the chamfering voltage LS_O is a thin film transistor used by the GIP panel The gate voltage. Referring to FIG. 2, FIG. 2 is a schematic diagram illustrating the waveforms of the input voltage LS_I, the first voltage LS, and the chamfer voltage LS_O, wherein the level of the input voltage LS_I is from 0 to the high voltage VDD. As shown in Fig. 2, the discharge time of the chamfering voltage LS_O is determined by an external capacitor C, and in general, the chamfering voltage LS_O is cut to the voltage VDDA. The discharge slope of the chamfering voltage LS_O is determined by an external resistor R, where VEEG is the gate low voltage and VGH is the gate high voltage. Therefore, the prior art cuts the gate voltage of the thin film transistor, reduces the flicker phenomenon of the GIP panel, and improves the panel uniformity to improve the picture quality. However, the disadvantage of the prior art is that the chamfering action is started at the negative edge of the first voltage LS, and the chamfering cannot be performed at any time point of the first voltage LS (for example, the chamfering is performed at the positive edge of the first voltage LS).

An embodiment of the present invention provides a chamfering circuit that produces a chamfer voltage of a liquid crystal display. The chamfering circuit comprises a quasi-regulator, a phase adjuster, a phase comparator and a chamfer. The level adjuster is configured to adjust a level of an input voltage to generate a first voltage; the phase adjuster is coupled to the level adjuster for receiving the first voltage and adjusting according to a phase a signal, the phase of the first voltage is adjusted to generate a second voltage; the phase comparator is coupled to the level adjuster and the phase adjuster for receiving the first voltage and the second voltage, wherein The phase comparator is configured to compare the first voltage with the second voltage to generate a comparison result; the chamfer is coupled to the level adjuster, the phase adjuster and the phase comparator for The chamfer voltage is output according to the first voltage, the second voltage, and the comparison result.

Another embodiment of the present invention provides a method of producing a chamfer voltage of a liquid crystal display. The method includes adjusting a level of an input voltage to generate a first voltage; adjusting a phase of the first voltage according to a phase adjustment signal to generate a second voltage; comparing the first voltage with the second voltage, And generating a comparison result; and outputting the chamfer voltage according to the first voltage, the second voltage, and the comparison result.

The present invention provides a chamfering circuit for producing a chamfer voltage of a liquid crystal display and a method thereof. The chamfering circuit and the method thereof use a quasi-regulator to adjust the level of an input voltage to generate a first voltage, and use a phase adjuster to adjust the phase of the input voltage to generate a second voltage, and then use A phase comparator compares the phase of the first voltage with the phase of the second voltage to produce a comparison result. The first chamfering unit and the second chamfering unit of the chamfering device can output a chamfering voltage according to the first voltage, the second voltage and the comparison result. Therefore, the present invention can generate the chamfering action at any time point, and can reduce the flicker phenomenon of a GIP panel and improve the uniformity of the GIP panel to improve the picture quality.

Please refer to FIG. 3. FIG. 3 is a schematic diagram showing a chamfering circuit 300 for generating a chamfering voltage of a liquid crystal display according to an embodiment of the present invention. The chamfering circuit 300 includes a quasi-regulator 302, a phase adjuster 304, a phase comparator 306, and a chamfer 308. The level adjuster 302 is configured to adjust the level of an input voltage LS_I to generate a first voltage LS. The phase adjuster 304 is coupled to the level adjuster 302 for receiving the first voltage LS, and according to the first The phase adjustment signal PR_I adjusts the phase of the first voltage LS to generate a second voltage PS. The phase comparator 306 is coupled to the level adjuster 302 and the phase adjuster 304 for receiving the first voltage LS and the second a voltage PS, wherein the phase comparator 306 is configured to compare the phase of the first voltage LS with the phase of the second voltage PS to generate a comparison result PC; the chamfer 308 is coupled to the level adjuster 302, the phase adjuster The phase comparator 306 is configured to output a chamfer voltage LS_O according to the first voltage LS, the second voltage PS, and the comparison result PC.

The chamfer 308 includes a first transmission gate 3082, a first chamfering unit 3084, a second chamfering unit 3086, a second transmission gate 3088 and a third transmission gate 3090. The first transmission gate 3082 is coupled to the phase adjuster 304 and the phase comparator 306; the first chamfering unit 3084 is coupled to the level adjuster 302 and the first transmission gate 3082; and the second chamfering unit 3086 is coupled. The leveling regulator 302 is coupled to the first transmission gate 3082; the second transmission gate 3088 is coupled to the first chamfering unit 3084, the second chamfering unit 3086, and the phase comparator 306; the third transmission gate 3090 is coupled to The first chamfering unit 3084, the second chamfering unit 3086, and the phase comparator 306.

Please refer to FIG. 4, which is a schematic diagram illustrating the chamfering device 308. The first chamfering unit 3084 has a first end coupled to the level adjuster 302 for receiving the first voltage LS, and a second end coupled to the first transmission gate 3082 and a third end coupled The level regulator 302 is configured to receive the first voltage LS, a fourth end, coupled to the second transmission gate 3088, a fifth end, for receiving a gate low voltage VEEG, and a sixth end, The third transfer gate 3090 is coupled to the third transfer gate 3090. The first chamfering unit 3084 includes a first N-type MOS transistor 30842, a second N-type MOS transistor 30844, a first P-type MOS transistor 30846, and a third N-type gold oxide. A half transistor 30848 and a second P-type MOS transistor 30850. The first N-type MOS transistor 30842 has a first end coupled to the first end of the first chamfering unit 3084, and a second end coupled to the first N-type MOS transistor 30842. The first N-type MOS transistor 30844 has a first end coupled to the third end of the first N-type MOS transistor 30842, and a second end coupled The second end of the first chamfering unit 3084 and the third end are coupled to the sixth end of the first chamfering unit 3084. The first P-type MOS transistor 30846 has a first end coupled to the first end. The third end of the second N-type MOS transistor 30844 is coupled to the second end of the second N-type MOS transistor 30844, and a third end; the third N-type gold The oxygen semiconductor transistor 30848 has a first end coupled to the third end of the first P-type MOS transistor 30846, a second end coupled to the third end of the first chamfering unit 3084, and a first end The third end is coupled to the fourth end of the first chamfering unit 3084. The second P-type MOS transistor 30850 has a first end coupled to the third of the second N-type MOS transistor 30844. a second end coupled to A third cut end corner unit 3084, and a third terminal coupled to the fifth terminal of the first chamfered section 3084.

As shown in FIG. 4, the second chamfering unit 3086 has a first end coupled to the level adjuster 302 for receiving the first voltage LS, and a second end coupled to the third transmission gate 3090. a third end, coupled to the level regulator 302, for receiving the first voltage LS, a fourth end, coupled to the first transmission gate 3082, a fifth end, coupled to the second transmission gate 3088, And a sixth end for receiving the gate low voltage VEEG. The second chamfering unit 3086 includes a fourth N-type MOS transistor 30862, a third P-type MOS transistor 30864, a fourth P-type MOS transistor 30866, and a fifth N-type gold oxide. A half transistor 30868 and a fifth P-type MOS transistor 30870. The fourth N-type MOS transistor 30862 has a first end coupled to the first end of the second chamfering unit 3086, and a second end coupled to the first end of the second chamfering unit 3086, and a third end is coupled to the second end of the second chamfering unit 3086. The third P-type MOS transistor 30864 has a first end coupled to the fourth N-type MOS transistor 30862. a third end, a second end, coupled to the third end of the second chamfering unit 3086, and a third end; the fourth P-type MOS transistor 30866 has a first end coupled to the fourth N a third end of the MOS transistor 30862, a second end coupled to the third end of the second chamfering unit 3086, and a third end; the fifth N-type MOS transistor 30868 has a first One end is coupled to the third end of the third P-type MOS transistor 30864, a second end is coupled to the fourth end of the second chamfering unit 3086, and a third end is coupled to the The fifth end of the second chamfering unit 3086; the fifth P-type MOS transistor 30870 has a first end coupled to the third end of the fourth P-type MOS transistor 30866, a second end, coupled Connected to the second chamfering unit 3086 A fourth terminal, and a third terminal coupled to the sixth terminal of the second unit 3086 is chamfered.

As shown in FIG. 4, the first transmission gate 3082 has a first end coupled to the phase adjuster 304 for receiving the second voltage PS, and a second end coupled to the phase comparator 306 for receiving The comparison result PC, a third end, coupled to the second end of the first chamfering unit 3084, and a fourth end coupled to the fourth end of the second chamfering unit 3086, wherein the first transmission gate 3082 is The second voltage PS is transmitted to the first chamfering unit 3084 or the second chamfering unit 3086 according to the comparison result PC. The first transfer gate 3082 includes a sixth N-type MOS transistor 30822 and a sixth P-type MOS transistor 30824. The sixth N-type MOS transistor 30822 has a first end coupled to the first end of the first transmission gate 3082, a second end coupled to the second end of the first transmission gate 3082, and a first The third end is coupled to the third end of the first transmission gate 3082. The sixth P-type MOS transistor 30824 has a first end coupled to the first end of the first transmission gate 3082 and a second end. The second end of the first transmission gate 3082 is coupled to the second end of the first transmission gate 3082 and coupled to the fourth end of the first transmission gate 3082.

As shown in FIG. 4, the second transmission gate 3088 has a first end coupled to the fourth end of the first chamfering unit 3084, and a second end coupled to an external resistor R and a third end. The second comparator is coupled to the fifth end of the second chamfering unit, wherein the second transmission gate 3088 is configured to be based on the comparison result PC, and is coupled to the phase comparator 306. The potential of the sixth end of the first chamfering unit 3084 or the potential of the second end of the second chamfering unit 3086 is discharged to a voltage VDDA through the external resistor R. The second transfer gate 3088 includes a seventh N-type MOS transistor 30882 and a seventh P-type MOS transistor 30884. The seventh N-type MOS transistor 30882 has a first end coupled to the first end of the second transfer gate 3088, a second end coupled to the third end of the second transfer gate 3088, and a first The third end is coupled to the second end of the second transfer gate 3088. The seventh P-type MOS transistor 30884 has a first end coupled to the fourth end of the second transfer gate 3088, and a second end. The third end of the second transmission gate 3088 is coupled to the second end of the second transmission gate 3088 and coupled to the second end of the second transmission gate 3088.

As shown in FIG. 4, the third transmission gate 3090 has a first end coupled to the second end of the second chamfering unit 3086, and a second end coupled to the phase comparator 306 for receiving the comparison result. The PC, a third end, is coupled to the sixth end of the first chamfering unit 3084, and a fourth end for outputting the chamfering voltage LS_O, wherein the third transmission gate 3090 is configured to determine according to the comparison result PC. The sixth end of the first chamfering unit 3084 or the second end of the second chamfering unit 3086 outputs a chamfering voltage LS_O. The third transfer gate 3090 includes an eighth P-type MOS transistor 30902 and an eighth N-type MOS transistor 30904. The eighth P-type MOS transistor 30902 has a first end coupled to the first end of the third transfer gate 3090, a second end coupled to the second end of the third transfer gate 3090, and a first The third end is coupled to the fourth end of the third transfer gate 3090. The eighth N-type MOS transistor 30904 has a first end coupled to the third end of the third transfer gate 3090. The second end is coupled to the second end of the third transmission gate of the 3090, and the third end is coupled to the fourth end of the third transmission gate 3090.

Please refer to FIG. 5A, FIG. 5B and Table 1. FIG. 5A is a schematic diagram illustrating the chamfering voltage LS_O generated by the chamfering circuit 300 when the phase of the first voltage LS is behind the second voltage PS, FIG. 5B and FIG. Table 1 is a schematic diagram illustrating the action of the first chamfering unit 3084 when the phase of the first voltage LS is behind the second voltage PS.

As shown in FIG. 5A, when the first voltage LS lags the second voltage PS time T1, the comparison result PC is a logic high potential, and the chamfer voltage LS_O starts to discharge according to the negative edge of the second voltage PS, and is in the first When the negative edge of a voltage LS ends the discharge, the discharge time (the time of the chamfer) of the chamfer voltage LS_O can be controlled by the time T1. Since the comparison result PC is a logic high potential, the sixth N-type MOS transistor 30822, the seventh N-type MOS transistor 30882, and the eighth N-type MOS transistor 30904 are turned on, so the first chamfer The second end of the unit 3084 receives the second voltage PS through the first transmission gate 3082, and the fourth end of the first chamfering unit 3084 is coupled to the external resistor R and the sixth of the first chamfering unit 3084 through the second transmission gate 3088. The end outputs the chamfer voltage LS_O through the third transfer gate 3090. In addition, the discharge slope of the chamfering voltage LS_O is determined by the first chamfering The parasitic capacitance of the element 3084 is determined by the external resistor R. However, since the parasitic capacitance of the first chamfering unit 3084 is small, the discharge slope of the chamfering voltage LS_O can be controlled by the external resistor R. In addition, in Table 1, the gate high voltage VGH is represented by "1" and the gate low voltage VEEG is represented by "0". As shown in FIG. 4, FIG. 5B and Table 1, in the I region of FIG. 5B, the first voltage LS is "0" and the second voltage PS is "1", so the first N-type oxy-half is half. The transistor 30842 is turned off, the second N-type MOS transistor 30844 is turned on, the first P-type MOS transistor 30846 is turned off, the third N-type MOS transistor 30848 is turned off, and the second P-type MOS transistor is turned off. The 30850 is turned on. Because the second P-type MOS transistor 30850 is turned on, the chamfer voltage LS_O is pulled down to "0" via the fifth end of the first chamfering unit 3084. In the II region of FIG. 5B, the first voltage LS is "1" and the second voltage PS is "1", so the first N-type MOS transistor 30842 is turned on, and the second N-type MOS transistor is turned on. 30844 is turned on, the first P-type MOS transistor 30846 is turned off, the third N-type MOS transistor 30848 is turned on, and the second P-type MOS transistor 30850 is turned off. Because the first N-type MOS transistor 30842 is turned on and the second N-type MOS transistor 30844 is turned on, the chamfering voltage LS_O is pulled up to "1" via the first end of the first chamfering unit 3084. In the III region of FIG. 5B, the first voltage LS is "1" and the second voltage PS is "0", so the first N-type MOS transistor 30842 is turned on, and the second N-type MOS transistor is turned on. 30844 is closed, the first P-type MOS transistor 30846 is turned on, the third N-type MOS transistor 30848 is turned on, and the second P-type MOS transistor 30850 is turned off. Because the first P-type MOS transistor 30846 is turned on and the third N-type MOS transistor 30848 is turned on, the chamfering voltage LS_O is externally connected through the second transfer gate 3088 via the fourth end of the first chamfering unit 3084. Resistor R is discharged to voltage VDDA. In the IV area of Figure 5B, the first The voltage LS is "0" and the second voltage PS is "0", so the first N-type MOS transistor 30842 is turned off, the second N-type MOS transistor 30844 is turned off, and the first P-type MOS is half-closed. The transistor 30846 is turned on, the third N-type MOS transistor 30848 is turned off, and the second P-type MOS transistor 30850 is turned on. Because the second P-type MOS transistor 30850 is turned on, the chamfer voltage LS_O is pulled down to "0" via the fifth end of the first chamfering unit 3084.

Please refer to FIG. 6A, FIG. 6B and Table 2. FIG. 6A is a schematic diagram illustrating the chamfering voltage LS_O generated by the chamfering circuit 300 when the phase of the first voltage LS leads the second voltage PS, FIG. 6B and FIG. Table 2 is a schematic diagram illustrating the action of the second chamfering unit 3086 when the phase of the first voltage LS leads the second voltage PS.

As shown in FIG. 6A, when the first voltage LS leads the second voltage PS time T2, the comparison result PC is a logic low potential, and the chamfer voltage LS_O starts to discharge according to the negative edge of the first voltage LS, and When the negative edge of the two voltages PS ends the discharge, the discharge time (the time of the chamfering) of the chamfering voltage LS_O can be controlled by the time T2. Because the comparison result is that the PC is logic low, the sixth P-type MOS transistor 30824, the seventh P-type MOS transistor 30884, and the eighth P-type MOS transistor 30902 are turned on, because The fourth end of the second chamfering unit 3086 receives the second voltage PS through the first transmission gate 3082, and the fifth end of the second chamfering unit 3086 is coupled to the external resistor R and the second chamfer through the second transmission gate 3088. The second end of the unit 3086 outputs the chamfer voltage LS_O through the third transfer gate 3090. In addition, the discharge slope of the chamfering voltage LS_O is determined by the parasitic capacitance of the second chamfering unit 3086 and the external resistor R. However, since the parasitic capacitance of the second chamfering unit 3086 is small, the discharge slope of the chamfering voltage LS_O can be controlled by the external resistor R. In addition, in Table 2, the gate high voltage VGH is represented by "1" and the gate low voltage VEEG is represented by "0". As shown in FIG. 4, FIG. 6B and Table 2, in the I' region of FIG. 6B, the first voltage LS is "1" and the second voltage PS is "0", so the fourth N-type gold oxide The semi-transistor 30862 is turned on, the third P-type MOS transistor 30864 is turned off, the fourth P-type MOS transistor 30866 is turned off, the fifth N-type MOS transistor 30868 is turned off, and the fifth P-type MOS is turned off. Crystal 30870 is turned on. Because the fourth N-type MOS transistor 30862 is turned on, the chamfering voltage LS_O is pulled up to "1" via the first end of the second chamfering unit 3086. In the II' region of FIG. 6B, the first voltage LS is "1" and the second voltage PS is "1", so the fourth N-type MOS transistor 30862 is turned on, and the third P-type MOS is half-electric. The crystal 30864 is turned off, the fourth P-type MOS transistor 30866 is turned off, the fifth N-type MOS transistor 30868 is turned on, and the fifth P-type MOS transistor 30870 is turned off. Because the fourth N-type MOS transistor 30862 is turned on, the chamfering voltage LS_O is pulled up to "1" via the first end of the second chamfering unit 3086. In the III' region of FIG. 6B, the first voltage LS is "0" and the second voltage PS is "1", so the fourth N-type MOS transistor 30862 is turned off, and the third P-type MOS is half-electric. The crystal 30864 is turned on, the fourth P-type MOS transistor 30866 is turned on, the fifth N-type MOS transistor 30868 is turned on, and the fifth P-type MOS transistor is turned on. 30870 is closed. Because the third P-type MOS transistor 30864 is turned on and the fifth N-type MOS transistor 30868 is turned on, the chamfering voltage LS_O is externally connected through the second transmission gate 3088 via the fifth end of the second chamfering unit 3086. Resistor R is discharged to voltage VDDA. In the IV' region of FIG. 6B, the first voltage LS is "0" and the second voltage PS is "0", so the fourth N-type MOS transistor 30862 is turned off, and the third P-type MOS is half-electric. The crystal 30864 is turned on, the fourth P-type MOS transistor 30866 is turned on, the fifth N-type MOS transistor 30868 is turned off, and the fifth P-type MOS transistor 30870 is turned on. Because the fourth P-type MOS transistor 30866 is turned on and the fifth P-type MOS transistor 30870 is turned on, the chamfering voltage LS_O is pulled down to "0" via the sixth end of the second chamfering unit 3086.

Please refer to FIG. 7. FIG. 7 is a flow chart showing a method for generating a chamfer voltage of a liquid crystal display according to another embodiment of the present invention. The method of FIG. 7 is illustrated by the chamfering circuit 300 of FIG. 3. The detailed steps are as follows: Step 700: Start; Step 702: Adjust the level of the input voltage LS_I to generate the first voltage LS; Step 704: Adjust according to the phase The signal PR_I, adjust the phase of the first voltage LS to generate the second voltage PS; Step 706: Compare whether the phase of the first voltage LS is ahead of the phase of the second voltage PS, and generate a comparison result PC; if yes, proceed to step 708; If no, go to step 710; Step 708: The second chamfering unit 3086 is based on the first voltage LS, the second voltage PS and The comparison result PC outputs the chamfer voltage LS_O; Step 710: The first chamfering unit 3084 outputs the chamfer voltage LS_O according to the first voltage LS, the second voltage PS and the comparison result PC.

In step 702, the level adjuster 302 adjusts the level of the input voltage LS_I to generate a first voltage LS. In step 704, the phase adjuster 304 adjusts the phase of the first voltage LS according to the phase adjustment signal PR_I to generate the second voltage PS. In step 706, the phase comparator 306 compares the phase of the first voltage LS with the phase of the second voltage PS to produce a comparison result PC. In step 708, when the phase of the first voltage LS leads the phase of the second voltage PS, the second chamfering unit 3086 receives the second voltage PS through the first transmission gate 3082 according to the comparison result PC. Then, the second chamfering unit 3086 outputs the chamfering voltage LS_O according to the second voltage PS, the first voltage LS, and the comparison result PC. In step 710, when the phase of the first voltage LS is behind the phase of the second voltage PS, the first chamfering unit 3084 receives the second voltage PS through the first transmission gate 3082 according to the comparison result PC. Then, the first chamfering unit 3084 outputs the chamfering voltage LS_O according to the second voltage PS, the first voltage LS, and the comparison result PC.

In summary, the present invention provides a chamfering circuit for generating a chamfering voltage of a liquid crystal display and a method thereof, which use a level adjuster to adjust the level of the input voltage to generate a first voltage, and adjust the input by using a phase adjuster. The phase of the voltage is used to generate a second voltage, and the phase comparator is used to compare the phase of the first voltage with the phase of the second voltage to produce a comparison result. The first chamfering unit and the second chamfering unit of the chamfering device can output the chamfering voltage according to the first voltage, the second voltage and the comparison result. Therefore, the present invention can be arbitrarily The chamfering action occurs at the time point, and the flickering phenomenon of the GIP panel and the uniformity of the GIP panel can be reduced to improve the picture quality.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100, 300‧‧‧ chamfering circuit

102, 302‧‧ ‧ level adjuster

104‧‧‧Chamfering unit

304‧‧‧ phase adjuster

306‧‧‧ phase comparator

308‧‧‧Chamfer

3082‧‧‧First transmission gate

3084‧‧‧First chamfering unit

3086‧‧‧second chamfering unit

3088‧‧‧Second transmission gate

3090‧‧‧3rd transmission gate

30822‧‧‧6th N-type gold oxide semi-transistor

30824‧‧‧6th P-type oxy-oxygen semiconductor

30842‧‧‧First N-type gold oxide semi-transistor

30844‧‧‧Second N-type gold oxide semi-transistor

30846‧‧‧First P-type MOS semi-transistor

30848‧‧‧Third N-type gold oxide semi-transistor

30850‧‧‧Second P-type oxy-oxygen semiconductor

30862‧‧‧Fourth N-type gold oxide semi-transistor

30864‧‧‧ Third P-type oxy-oxygen semiconductor

30866‧‧‧Fourth P-type oxy-oxygen semiconductor

30868‧‧‧ Fifth N-type oxy-oxygen semiconductor

30870‧‧‧ Fifth P-type oxy-oxygen semiconductor

30882‧‧‧The seventh N-type gold oxide semi-transistor

30884‧‧‧The seventh P-type gold oxide semi-transistor

30902‧‧‧The eighth P-type MOS semi-transistor

30904‧‧‧8th N-type gold oxide semi-transistor

C‧‧‧External capacitor

LS‧‧‧First voltage

LS_I‧‧‧ input voltage

LS_O‧‧‧Chamfering voltage

PC‧‧‧ comparison results

PR_I‧‧‧ phase adjustment signal

PS‧‧‧second voltage

R‧‧‧ external resistor

T1, T2‧‧‧ time

VDD‧‧‧high voltage

VEEG‧‧‧ gate low voltage

VGH‧‧‧ gate high voltage

VDDA‧‧‧ voltage

700 to 710‧‧ steps

Figure 1 is a schematic illustration of a chamfering circuit system applied to a GIP panel in the prior art.

Fig. 2 is a schematic view showing waveforms of an input voltage, a first voltage, and a chamfer voltage.

Fig. 3 is a schematic view showing a chamfering circuit for generating a chamfering voltage of a liquid crystal display according to an embodiment of the present invention.

Figure 4 is a schematic view showing the chamfering device.

Figure 5A is a schematic diagram illustrating the chamfering voltage generated by the chamfering circuit when the phase of the first voltage is behind the second voltage.

FIG. 5B and Table 1 are diagrams illustrating the operation of the first chamfering unit when the phase of the first voltage is behind the second voltage.

Fig. 6A is a diagram illustrating the chamfering voltage generated by the chamfering circuit when the phase of the first voltage leads the second voltage.

6B and 2 are schematic diagrams illustrating the operation of the second chamfering unit when the phase of the first voltage leads the second voltage.

Figure 7 is a flow chart showing a method of producing a chamfer voltage of a liquid crystal display according to another embodiment of the present invention.

300. . . Chamfering circuit

302. . . Level adjuster

304. . . Phase adjuster

306. . . Phase comparator

308. . . Chamfer

3082. . . First transmission gate

3084. . . First chamfering unit

3086. . . Second chamfering unit

3088. . . Second transmission gate

3090. . . Third transmission gate

LS. . . First voltage

LS_I. . . Input voltage

LS_O. . . Angle cutting voltage

PC. . . Comparing results

PR_I. . . Phase adjustment signal

PS. . . Second voltage

R. . . External resistor

VDDA. . . Voltage

Claims (8)

A chamfering circuit for generating a chamfering voltage of a liquid crystal display, comprising: a quasi-regulator for adjusting an input voltage level to generate a first voltage; and a phase adjuster coupled to the level adjustment And receiving the first voltage, and adjusting a phase of the first voltage according to a phase adjustment signal to generate a second voltage; a phase comparator coupled to the level adjuster and the phase adjuster Receiving the first voltage and the second voltage, wherein the phase comparator is configured to compare the first voltage with the second voltage to generate a comparison result; and a chamfer is coupled to the bit a phase adjuster, the phase adjuster and the phase comparator for outputting the chamfer voltage according to the first voltage, the second voltage and the comparison result, wherein the chamfer comprises: a first transmission gate, The phase adjuster is coupled to the phase adjuster; a first chamfering unit is coupled to the level adjuster and the first transfer gate; and a second chamfering unit is coupled to the level adjuster And the first transmission gate; a second transmission gate The first chamfering unit, the second chamfering unit, and the phase comparator are coupled to the first chamfering unit, the second chamfering unit, and the phase comparator . The chamfering circuit of claim 1, wherein the first chamfering unit has a first end coupled to the level adjuster for receiving the first voltage, a second end, The first transmission gate is coupled to the first transmission gate, and the third terminal is coupled to the level regulator for receiving the first voltage, and the fourth terminal is coupled to the second transmission gate and the fifth terminal. The first chamfering unit includes: a first N-type MOS transistor having a first end, configured to receive a gate low voltage, and a sixth end coupled to the third transfer gate, wherein the first chamfering unit comprises: a first N-type MOS transistor And coupled to the first end of the first chamfering unit, a second end coupled to the first end, and a third end; a second N-type MOS transistor having a first end, The first end of the first N-type MOS transistor is coupled to the second end of the first N-type MOS transistor, and the second end is coupled to the second end of the first chamfering unit, and a third end coupled to the first a sixth end of the corner unit; a first P-type MOS transistor having a first end coupled to the third end of the second N-type MOS transistor, and a second end coupled to a second end of the second N-type MOS transistor, and a third end; a third N-type MOS transistor having a first end coupled to the first P-type MOS The third end of the crystal, a second end, coupled a third end of the first chamfering unit, and a third end coupled to the fourth end of the first chamfering unit; and a second P-type MOS transistor having a first end, The third end of the second N-type MOS transistor is coupled to the third end of the first chamfering unit, and the third end is coupled to the first end The fifth end of the corner unit. The chamfering circuit of claim 1, wherein the second chamfering unit has a first The first end is coupled to the level regulator, and the second end is coupled to the third transmission gate, and the third terminal is coupled to the level adjuster for receiving The first voltage, a fourth end, coupled to the first transmission gate, a fifth end, coupled to the second transmission gate, and a sixth terminal for receiving the gate low voltage, wherein the The second chamfering unit includes: a fourth N-type MOS transistor having a first end coupled to the first end of the second chamfering unit, and a second end coupled to the first end And a third end coupled to the second end of the second chamfering unit; a third P-type MOS transistor having a first end coupled to the fourth N-type oxy-halide a third end of the crystal, a second end coupled to the third end of the second chamfering unit, and a third end; a fourth P-type MOS transistor having a first end coupled a third end of the fourth N-type MOS transistor, a second end coupled to the third end of the second chamfering unit, and a third end; a fifth N-type oxy-oxygen semi-electric a crystal having a first end coupled a third end of the third P-type MOS transistor, a second end coupled to the fourth end of the second chamfering unit, and a third end coupled to the second chamfering unit And a fifth P-type MOS transistor having a first end coupled to the third end of the fourth P-type MOS transistor, and a second end coupled to the The fourth end of the second chamfering unit and the third end are coupled to the sixth end of the second chamfering unit. The chamfering circuit of claim 1, wherein the first transmission gate has a first end coupled to the phase adjuster for receiving the second voltage, and a second end coupled to the phase comparison The third end is coupled to the second end of the first chamfering unit, and the fourth end is coupled to the fourth end of the second chamfering unit, wherein the third end is coupled to the fourth end of the second chamfering unit The first transmission gate is configured to transmit the second voltage to the first chamfering unit or the second chamfering unit according to the comparison result, where the first transmission gate comprises: a sixth N-type MOS transistor; The first end is coupled to the first end of the first transmission gate, the second end is coupled to the second end of the first transmission gate, and a third end is coupled to the first transmission a third end of the gate; and a sixth P-type MOS transistor having a first end coupled to the first end of the first transmission gate and a second end coupled to the first transmission gate The second end and a third end are coupled to the fourth end of the first transmission gate. The chamfering circuit of claim 1, wherein the second transmission gate has a first end coupled to the fourth end of the first chamfering unit, and a second end coupled to an external resistor, The third end is coupled to the phase comparator for receiving the comparison result, and a fourth end is coupled to the fifth end of the second chamfering unit, wherein the second transmission gate is used according to the As a result of the comparison, the potential of the sixth end of the first chamfering unit or the potential of the second end of the second chamfering unit is discharged to a voltage through the external resistor, and the second transmission gate comprises: a seventh N-type gold oxide a semi-transistor having a first end coupled to the first end of the second transmission gate and a second end coupled to the third end of the second transmission gate And a third end coupled to the second end of the second transmission gate; and a seventh P-type MOS transistor having a first end coupled to the fourth end of the second transmission gate The second end is coupled to the third end of the second transmission gate, and the third end is coupled to the second end of the second transmission gate. The chamfering circuit of claim 1, wherein the third transmission gate has a first end coupled to the second end of the second chamfering unit, and a second end coupled to the phase comparator, For receiving the comparison result, a third end is coupled to the sixth end of the first chamfering unit, and a fourth end for outputting the chamfer voltage, wherein the third transmission gate is used according to The comparison result determines that the sixth end of the first chamfering unit or the second end of the second chamfering unit outputs the chamfer voltage, and the third transmission gate comprises: an eighth P-type MOS transistor; The first end is coupled to the first end of the third transmission gate, the second end is coupled to the second end of the third transmission gate, and a third end is coupled to the third transmission a fourth end of the gate; and an eighth N-type MOS transistor having a first end coupled to the third end of the third transfer gate, and a second end coupled to the third transfer gate The second end and the third end are coupled to the fourth end of the third transmission gate. A method for generating a chamfer voltage of a liquid crystal display, comprising: adjusting a level of an input voltage to generate a first voltage; adjusting a phase of the first voltage according to a phase adjustment signal to generate a second voltage; Comparing a phase of the first voltage with a phase of the second voltage to generate a comparison result; and outputting the chamfer voltage according to the first voltage, the second voltage, and the comparison result; wherein when the comparison result indicates When the phase of the first voltage is behind the phase of the second voltage, the first chamfering unit of the chamfer outputs the chamfer voltage according to the first voltage, the second voltage, and the comparison result. The method of claim 7, wherein when the comparison result indicates that the phase of the first voltage is ahead of the phase of the second voltage, the second chamfering unit of the chamfer is based on the first voltage and the second voltage In comparison with the result, the chamfer voltage is output.