[go: up one dir, main page]

CN116169874A - Pump circuit - Google Patents

Pump circuit Download PDF

Info

Publication number
CN116169874A
CN116169874A CN202310174204.6A CN202310174204A CN116169874A CN 116169874 A CN116169874 A CN 116169874A CN 202310174204 A CN202310174204 A CN 202310174204A CN 116169874 A CN116169874 A CN 116169874A
Authority
CN
China
Prior art keywords
voltage
circuit
power supply
pump
clock control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310174204.6A
Other languages
Chinese (zh)
Inventor
刘芳芳
姚翔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority to CN202310174204.6A priority Critical patent/CN116169874A/en
Publication of CN116169874A publication Critical patent/CN116169874A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0041—Control circuits in which a clock signal is selectively enabled or disabled
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from DC input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention provides a pump circuit, which comprises a voltage dividing circuit, a comparator, a clock control circuit, a charge pump and a power supply circuit, wherein the voltage dividing circuit is connected with the comparator; the output end of the charge pump outputs a first positive voltage VPOS, and a second positive voltage VPOSW is output from a middle tap of the charge pump; the voltage dividing circuit is connected between the first positive voltage VPOS and ground and outputs a divided voltage DIV; the comparator compares the divided voltage DIV with a reference voltage VREF and outputs a clock control signal; the clock control signal is input to the control end of the clock control circuit, and the clock signal PCLK is input to the input end of the charge pump through the clock control circuit; the supply voltage of the clock control circuit and the charge pump is VDDI, which is generated by the supply circuit. According to the invention, the NMOS tube N2 is added in the power supply module, the second positive voltage VPOSM is added in the pump module, and the VPOSM is connected to the drain end of the NMOS tube N2, so that the purpose that the NMOS tube N1 is fully conducted when the low-voltage pump is started and the VDDI is infinitely close to the external total power supply of the power supply circuit is realized, and the voltage value of the positive voltage VPOS output by the pump circuit is improved.

Description

Pump circuit
Technical Field
The invention relates to the technical field of electronics, in particular to a pump circuit.
Background
When Flash products execute erase and program operations, high voltage is required to be generated, and in order to meet the requirements that Flash products can normally work at a very wide power supply voltage, have low power consumption and have strong driving capability, a pump circuit is required to be used.
Fig. 1 shows a circuit schematic for generating a positive voltage VPOS for a PUMP BLOCK in the prior art. As shown in fig. 1, the circuit includes a voltage dividing circuit, a Comparator (COMP), a clock control circuit (PCLK BLOCK), a charge pump, i.e., a Boost module (Boost Stage), and a power supply module (vdd gen). The voltage dividing circuit is connected between the positive voltage VPOS and the ground vgnd and outputs a voltage division DIV formed by the positive voltage VPOS and the ground vgnd, and the voltage dividing circuit is formed by connecting a plurality of resistors in series; the comparator compares the divided voltage DIV with the reference voltage VREF and outputs a clock control signal, the non-inverting input end of the comparator is connected with the divided voltage DIV, and the inverting input end of the comparator is connected with the reference voltage VREF; the clock signal PCLK is input to the input terminal of the charge pump through the clock control circuit. The clock control signal adjusts the magnitude of the positive voltage VPOS by adjusting the magnitude of the clock signal PCLK; the filter capacitor is connected between the output of the positive voltage VPOS and ground vgnd. The power supply of the PCLK & Boost Stage module is VDDI, which is generated by the vdd gen module, which is the external total power supply of VDDA50.
The circuit shown in fig. 1, when activated at low voltage pump, consumes an instantaneous increase in power, VDDI is reduced by a portion of the tube N1 compared to VDDA50, and is subject to the ability of the N1 tube to recover slower, and the pump circuit is activated at VDDI to a predetermined target for a longer period of time at that time.
Disclosure of Invention
In view of the above, the present invention provides a pump circuit for solving the problem of poor driving capability of the positive voltage VPOS when the existing pump circuit is started at low voltage.
The invention provides a pump circuit, comprising: the circuit comprises a voltage dividing circuit, a comparator, a clock control circuit, a charge pump and a power supply circuit;
the output end of the charge pump outputs a first positive voltage VPOS, and a second positive voltage VPOSW is output from a middle tap of the charge pump; the voltage dividing circuit is connected between the first positive voltage VPOS and ground and outputs a divided voltage DIV; the comparator compares the divided voltage DIV with a reference voltage VREF and outputs a clock control signal;
the clock control signal is input to a control end of the clock control circuit, a clock signal PCLK is input to an input end of the charge pump through the clock control circuit, the clock control signal adjusts the amplitude of the clock signal PCLK input to the charge pump, and the magnitudes of the first positive voltage VPOS and the second positive voltage VPOSW are adjusted through the adjustment of the amplitude of the clock signal PCLK;
the power supply circuit comprises a first current path, a second current path and an NMOS tube N2, wherein the first current path and the second current path are connected between an external main power supply and the ground, the first current path comprises a first current source, an MOS tube and a triode which are connected in series, and the second current path comprises an NMOS tube N1 and a second current source; one end of the first current source is connected with the external total power supply, the other end of the first current source is connected with the grid electrode of the NMOS tube N1 and the source electrode of the NMOS tube N2, the grid electrode of the NMOS tube N2 is connected with the external total power supply, the second positive voltage VPOSM is output to the drain end of the NMOS tube N2, the source electrode of the NMOS tube N1 is connected with the external total power supply, and the drain electrode of the NMOS tube N1 is used for outputting the power supply voltage VDDI of the clock control circuit and the charge pump.
Preferably, the voltage dividing circuit is formed by connecting a plurality of resistors in series.
Preferably, a non-inverting input terminal of the comparator is connected to the divided voltage DIV, and an inverting input terminal is connected to the reference voltage VREF.
The voltage value of the second positive voltage VPOSW is about half of the first positive voltage VPOS.
Preferably, the supply voltage VDDI of the clock control circuit and the charge pump is infinitely close to the external mains supply.
Preferably, the external total power supply is VDDA50.
Preferably, the MOS tube is a PNMOS tube.
Preferably, the circuit further comprises a filter capacitor.
Preferably, the filter capacitor is connected between the output of the first positive voltage VPOS and ground.
According to the pump circuit, the NMOS tube N2 is added in the power supply module, the second positive voltage VPOSM is added in the pump module, and the VPOSM is connected to the drain end of the NMOS tube N2, so that when the low-voltage pump is started, the NMOS tube N2 is conducted, the potential of the gate end of the NMOS tube N1 is lifted to VPOSM, the NMOS tube N1 is fully conducted, VDDI is infinitely close to an external total power supply VDDA50 of the power supply circuit, the driving capability of the positive voltage VPOS is improved, and compared with the existing circuit, the positive voltage VPOS output by the pump circuit is lifted.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 is a schematic diagram of a conventional pump circuit;
FIG. 2 is a schematic diagram showing a circuit structure of a pump circuit according to an embodiment of the invention;
fig. 3 shows a potential diagram of the circuit shown in fig. 1 and the circuit shown in fig. 2 outputting a positive voltage VPOS.
Detailed Description
The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, flows, components and circuits have not been described in detail so as not to obscure the nature of the invention.
Moreover, those of ordinary skill in the art will appreciate that the drawings are provided herein for illustrative purposes and that the drawings are not necessarily drawn to scale.
Unless the context clearly requires otherwise, the words "comprise," "comprising," and the like throughout the application are to be construed as including but not being exclusive or exhaustive; that is, it is the meaning of "including but not limited to".
In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
Fig. 2 is a schematic circuit diagram of a pump circuit according to an embodiment of the invention. As shown in fig. 2, the pump circuit according to the embodiment of the invention includes a pump module and a power module. The pump module comprises a voltage dividing circuit, a Comparator (COMP), a clock control circuit (PCLK BLOCK), a charge pump, namely a Boost module (Boost Stage), and a power supply module (vdd gen).
The output end of the charge pump outputs a first positive voltage VPOS, and the second positive voltage VPOSW is output from the middle tap of the charge pump. The voltage dividing circuit is connected between the first positive voltage VPOS and ground and outputs a divided voltage DIV. The non-inverting input end of the comparator is connected with the divided voltage DIV, the inverting input end of the comparator is connected with the reference voltage VREF, and the comparator compares the divided voltage DIV with the reference voltage VREF and outputs a clock control signal. The clock control signal is input to a control end of the clock control circuit (PCLK BLOCK), the clock signal PCLK is input to an input end of the charge pump (Boost Stage) through the clock control circuit (PCLK BLOCK), the clock control signal adjusts the amplitude of the clock signal PCLK input to the charge pump (Boost Stage), and the magnitudes of the first positive voltage VPOS and the second positive voltage VPOSW are adjusted through adjustment of the amplitude of the clock signal PCLK.
In the embodiment of the present invention, the voltage sources of the clock control circuit and the charge pump are VDDI, which is generated by the power supply module. The power supply circuit of the power supply module (vdd gen) includes a first current path, a second current path, and an NMOS transistor N2. The first current path and the second current path are both connected between an external total power supply and the ground, the first current path comprises a first current source, an MOS tube and a triode which are connected in series, the MOS tube is a PNMOS tube, and the second current path comprises an NMOS tube N1 and a second current source. One end of the first current source is connected with an external total power supply, the other end of the first current source is connected with the grid electrode of the NMOS tube N1 and the source electrode of the NMOS tube N2, the grid electrode of the NMOS tube N2 is connected with the external total power supply, the second positive voltage VPOSM is output to the drain end of the NMOS tube N2, the source electrode of the NMOS tube N1 is connected with the external total power supply, and the drain electrode outputs the power voltage VDDI of the clock control circuit and the charge pump.
In the embodiment of the invention, the voltage dividing circuit is formed by connecting a plurality of resistors in series. In other embodiments can also be: the voltage dividing circuit is formed by connecting a plurality of MOS transistors in series, and the drain and the gate of each MOS transistor are connected together.
In the embodiment of the invention, the external total power supply is VDDA50.
In the embodiment of the invention, the supply voltage VDDI of the clock control circuit and the charge pump is infinitely close to the external total power supply VDDA50. In the embodiment of the invention, when the pump is started at the low potential of VDDA50, the NMOS transistor N2 is turned on, the gate terminal potential of the NMOS transistor N1 is raised to VPOSM, the VPOSM value is about 0.5 x VPOS, so that the NMOS transistor N1 is fully turned on, VDDI is infinitely close to VDDA50, but ib_vddi in the conventional pump circuit in fig. 1 is clamped by current, the voltage is far lower than VPOSM, the VDDI potential is VDDA50-Vt, and VDDI is used as the base potential of the clock control circuit (PCLK BLOCK) and the charge pump (Boost Stage), so that the voltage value of the final VPOS is directly determined.
The pump circuit of the embodiment of the invention further comprises a filter capacitor, and the filter capacitor is connected between the output end of the first positive voltage VPOS and the ground.
Fig. 3 shows a voltage VPOS potential diagram of the circuit shown in fig. 1 and the circuit shown in the embodiment of the present invention. As shown in fig. 3, curve 12 is the output positive voltage VPOS potential diagram of the prior art pump circuit shown in fig. 1; curve 11 is the output positive voltage VPOS potential diagram of the pump circuit according to the embodiment of the present invention. As can be seen from the figure, the NMOS transistor N2 is added in the power module, the second positive voltage VPOSM is added in the pump module, and the VPOSM is connected to the drain terminal of the NMOS transistor N2, so that the positive voltage VPOS output by the pump circuit can be effectively improved, and in the embodiment of the invention, the VPOS potential is improved from 8.65V to 8.85V.
In summary, in the pump circuit according to the embodiment of the invention, the NMOS transistor N2 is added in the power module, the second positive voltage VPOSM is added in the pump module, and VPOSM is connected to the drain terminal of the NMOS transistor N2, so that when the low-voltage pump is started, the NMOS transistor N2 is turned on, the gate terminal potential of the NMOS transistor N1 is raised to VPOSM, the NMOS transistor N1 is fully turned on, VDDI is infinitely close to the external total power supply VDDA50 of the power circuit, the driving capability of the positive voltage VPOS is improved, and compared with the existing circuit, the positive voltage VPOS output by the pump circuit of the invention is raised.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (9)

1.一种pump电路，其特征在于，包括分压电路、比较器、时钟控制电路、电荷泵和电源电路；1. A pump circuit, characterized in that, comprises a voltage divider circuit, a comparator, a clock control circuit, a charge pump and a power supply circuit; 所述电荷泵的输出端输出第一正电压VPOS，第二正电压VPOSW从所述电荷泵的中间抽头输出；所述分压电路连接在所述第一正电压VPOS和地之间并输出分压DIV；所述比较器比较所述分压DIV和参考电压VREF并输出时钟控制信号；The output terminal of the charge pump outputs the first positive voltage VPOS, and the second positive voltage VPOSW is output from the center tap of the charge pump; the voltage divider circuit is connected between the first positive voltage VPOS and ground and outputs a divided Voltage DIV; the comparator compares the divided voltage DIV with the reference voltage VREF and outputs a clock control signal; 所述时钟控制信号输入到所述时钟控制电路的控制端，时钟信号PCLK通过所述时钟控制电路输入到所述电荷泵的输入端，所述时钟控制信号调节所述时钟信号PCLK输入到所述电荷泵的幅度，通过对所述时钟信号PCLK的幅度的调节来调节所述第一正电压VPOS和所述第二正电压VPOSW的大小；The clock control signal is input to the control terminal of the clock control circuit, the clock signal PCLK is input to the input terminal of the charge pump through the clock control circuit, and the clock control signal adjusts the clock signal PCLK input to the The magnitude of the charge pump is to adjust the magnitude of the first positive voltage VPOS and the second positive voltage VPOSW by adjusting the magnitude of the clock signal PCLK; 所述电源电路包括第一电流路径、第二电流路径和NMOS管N2，所述第一电流路径和第二电流路径都连接在外部总电源和地之间，所述第一电流路径包括串联的第一电流源、MOS管和三极管，所述第二电流路径包括NMOS管N1和第二电流源；所述第一电流源的一端接所述外部总电源，另一端与所述NMOS管N1的栅极和所述NMOS管N2的源极相连，所述NMOS管N2的栅极接所述外部总电源，所述第二正电压VPOSM输出到所述NMOS管N2的漏端，所述NMOS管N1的源极接所述外部总电源，漏极输出所述时钟控制电路和所述电荷泵的电源电压电压VDDI。The power supply circuit includes a first current path, a second current path and an NMOS transistor N2, the first current path and the second current path are both connected between the external general power supply and ground, and the first current path includes a series A first current source, a MOS transistor and a triode, the second current path includes an NMOS transistor N1 and a second current source; one end of the first current source is connected to the external general power supply, and the other end is connected to the NMOS transistor N1 The gate is connected to the source of the NMOS transistor N2, the gate of the NMOS transistor N2 is connected to the external main power supply, the second positive voltage VPOSM is output to the drain of the NMOS transistor N2, and the NMOS transistor N2 The source of N1 is connected to the external general power supply, and the drain outputs the power supply voltage VDDI of the clock control circuit and the charge pump. 2.根据权利要求1所述的pump电路，其特征在于，所述分压电路由多个电阻串联而成。2. The pump circuit according to claim 1, wherein the voltage divider circuit is formed by a plurality of resistors connected in series. 3.根据权利要求1所述的pump电路，其特征在于，所述比较器的正相输入端连接所述分压DIV，反相输入端连接参考电压VREF。3 . The pump circuit according to claim 1 , wherein the non-inverting input terminal of the comparator is connected to the divided voltage DIV, and the inverting input terminal is connected to the reference voltage VREF. 4 . 4.根据权利要求1所述的pump电路，其特征在于，所述第二正电压VPOSW的电压值为所述第一正电压VPOS的一半左右。4. The pump circuit according to claim 1, wherein the voltage value of the second positive voltage VPOSW is about half of the first positive voltage VPOS. 5.根据权利要求1所述的pump电路，其特征在于，所述时钟控制电路和所述电荷泵的电源电压电压VDDI无限接近于所述外部总电源。5. The pump circuit according to claim 1, characterized in that, the power supply voltage VDDI of the clock control circuit and the charge pump is infinitely close to the external main power supply. 6.根据权利要求1所述的pump电路，其特征在于，所述外部总电源为VDDA50。6. The pump circuit according to claim 1, characterized in that, the external total power supply is VDDA50. 7.根据权利要求1所述的pump电路，其特征在于，所述MOS管为PNMOS管。7. The pump circuit according to claim 1, wherein the MOS transistor is a PNMOS transistor. 8.根据权利要求1所述的pump电路，其特征在于，所述电路还包括滤波电容。8. The pump circuit according to claim 1, further comprising a filter capacitor. 9.根据权利要求8所述的pump电路，其特征在于，所述滤波电容连接在所述第一正电压VPOS的输出端和地之间。9. The pump circuit according to claim 8, wherein the filter capacitor is connected between the output terminal of the first positive voltage VPOS and ground.
CN202310174204.6A 2023-02-28 2023-02-28 Pump circuit Pending CN116169874A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310174204.6A CN116169874A (en) 2023-02-28 2023-02-28 Pump circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310174204.6A CN116169874A (en) 2023-02-28 2023-02-28 Pump circuit

Publications (1)

Publication Number Publication Date
CN116169874A true CN116169874A (en) 2023-05-26

Family

ID=86421696

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310174204.6A Pending CN116169874A (en) 2023-02-28 2023-02-28 Pump circuit

Country Status (1)

Country Link
CN (1) CN116169874A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101304212A (en) * 2007-05-11 2008-11-12 联咏科技股份有限公司 Voltage conversion device capable of improving voltage conversion efficiency
US20130222050A1 (en) * 2012-02-29 2013-08-29 Taiwan Semiconductor Manufacturing Co., Ltd. Low Voltage and High Driving Charge Pump
CN107453599A (en) * 2017-07-17 2017-12-08 上海华虹宏力半导体制造有限公司 The malleation charge pump of multivoltage output
CN112332657A (en) * 2020-10-20 2021-02-05 深迪半导体(上海)有限公司 Charge pump circuit and MEMS sensor
CN113991999A (en) * 2021-10-18 2022-01-28 上海华虹宏力半导体制造有限公司 Charge pump boosting system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101304212A (en) * 2007-05-11 2008-11-12 联咏科技股份有限公司 Voltage conversion device capable of improving voltage conversion efficiency
US20130222050A1 (en) * 2012-02-29 2013-08-29 Taiwan Semiconductor Manufacturing Co., Ltd. Low Voltage and High Driving Charge Pump
CN107453599A (en) * 2017-07-17 2017-12-08 上海华虹宏力半导体制造有限公司 The malleation charge pump of multivoltage output
CN112332657A (en) * 2020-10-20 2021-02-05 深迪半导体(上海)有限公司 Charge pump circuit and MEMS sensor
CN113991999A (en) * 2021-10-18 2022-01-28 上海华虹宏力半导体制造有限公司 Charge pump boosting system

Similar Documents

Publication Publication Date Title
US10481625B2 (en) Voltage regulator
US7948284B2 (en) Power-on reset circuit
CN108536211B (en) voltage regulator
CN107526385B (en) Linear Voltage Regulator
WO2020048420A1 (en) Digital voltage regulator and voltage regulating method thereof
JP2017062688A (en) Regulator circuit with protection circuit
TWI519026B (en) Circuit and method for short circuit and power limit protection
TW202147761A (en) Power clamp circuit
TW201910958A (en) Regulator circuit and method for providing regulated voltage to target circuit thereof
JP5535447B2 (en) Power supply voltage step-down circuit, semiconductor device, and power supply voltage circuit
CN116954297A (en) Power supply selection circuit and power supply
TW201643588A (en) Voltage regulator
CN116185113A (en) Soft start circuit, low dropout linear regulator, chip and electronic equipment
CN108233701B (en) Buck-boost voltage conversion circuit
CN112730958B (en) A voltage overshoot detection circuit
CN100508370C (en) Source follower and stable current feedback circuit thereof
CN116169874A (en) Pump circuit
JP2008171177A (en) Power supply circuit
TWI854330B (en) Low dropout regulator
TWI479803B (en) Output stage circuit
TW202040303A (en) Voltage regulation circuit
CN116088622A (en) Slow start circuit, low dropout linear voltage regulator, chip and electronic equipment
US20060164155A1 (en) Low-ripple boosted voltage generator
JPWO2007114379A1 (en) Variable delay circuit, test apparatus and electronic device
CN101365997B (en) Negative output regulator circuit and electric device using same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination