TWI332261B - A fabrication method of stacked multibit sonos type flash memory - Google Patents

Description

1332261 IX. Description of the Invention: [Technical Field] The present invention relates to a stacked SONOS-type flash memory structure and a method of fabricating the same, and more particularly to a flash memory with a lower SONOS type and an upper SONOS type flash The second component of the memory, and the upper s〇N〇s type flash flash memory element and the lower SONOS type flash memory component are stacked back to back, so that the data storage capacity of the floating gate flash memory is doubled to achieve a large A stacked SONOS-type flash memory structure and a manufacturing method thereof for reducing manufacturing cost. [Prior Art] The traditional floating gate flash memory uses the basic digital data storage concept to reduce the low level, while the "high order" is used to write and erase data. A floating gate (called a write) is injected by channel hot electrons (Channe| Hot & ectr〇n CHE). The lower level "〇" is that the electrons are erased by the floating gate by F_N penetration (Fowler-Nordheim Tunneling). Another kind of Nitride Storage flash memory that has emerged in recent years, using yttrium nitride (SiN) to sandwich it into two oxide layers, which becomes "oxide layer _ tantalum nitride-oxide layer" (Oxide-Nitride-Oxide, 0N0) structure. This 〇N〇 is used to replace the gate oxide layer in the MOSFET to form a charge storage layer. The structure of the flash memory is "Silicon-Oxide-Nitride-Oxide-Silicon (SONOS)", so it is also called SONOS memory. It uses channel hot electrons to inject electrons into the nitride layer (called write). HotHole (HH) neutralizes electrons at the same location and erases them. For SONOS f memory, the charge storage location can be on the left or right of the storage layer.

P070020-TW 5 side, its position depends on whether the write voltage is applied to the source or the pole. Therefore, it is possible to obtain a storage of two 疋 and to double the memory storage capacity of the conventional unit floating gate memory. However, this method has a significant disadvantage in actual operation, that is, there is a mismatch between the written electrons and the holes required for erasing. If the number of write erases increases, the mismatch phenomenon is severe and the threshold voltage of the erase is saturated, and the electrons cannot be effectively erased. Another problem is that the charge is subject to drift and diffusion causing minute movements, and the charge storage layer has a charge redistribution condition, which in turn reduces charge retention. However, even if there are more than one problem to be solved, this SONOS flash has been verified by American Supermicro (AMD) and has been mass-produced. SUMMARY OF THE INVENTION The object of the present invention is to increase the capacity of the flash memory, and the estimation can be increased from the traditional two-bit/quad order to the four-bit/six-digit order. If the multi-level chip f (Multi Level Chip) , MLC) technology, that is, each bit has four steps, then the new structural layer β is large, and the storage capacity is four bits/two hundred and fifty-six. The novel structure has a P SONOS type flash memory and an upper sonos type flash memory, and the (4) structure is composed of: a silk thread, a j body, a control gate layer, and a second Layer and an epitaxial layer. The method of making money according to the present invention is divided into Α_Α, direction process and β·β, direction process, wherein the A_A, direction making method comprises the following steps: *: ; .11 cutting to the definition of the button, _, photoresist removal, so that Its shape

P070020-TW 6 A_A' direction process, into the active area / shallow trench isolation area;: use the nitride dream as a hard mask, the polycrystalline phase ion residue is defined > meaning out; :: the base substrate is ion-etched' And forming a shallow trench isolation area; /Wv direction system. ^冓 isolation area filled with high-density plasma deposition oxide; (4) degree plasma deposition oxide is planarized by chemical mechanical polishing' and high-density plasma The deposited oxide is etched back by nitriding. The height of the (4) interface is removed by hot phosphoric acid. The /, ~ direction manufacturing method includes the following steps: Β Β direction process 1: as in the α_α' direction process Forming a first layer of charge storage layer, multi-turn Β, direction #钟' followed by comprehensive deposition of nitriding into a hard mask; system "1 cut by level definition, _, photoresist removal, to form a gate region; Β-Β, Direction Process 3: Using a nitrogen cut as a hard mask, define the polycrystal dream as the ion side; =Β方=程四·The trench isolation area is filled with high-density plasma deposited oxide; Β- Β, Direction Process 5: High Density Lai Deposition Oxidation It is planarized by chemical mechanical polishing, and the tantalum-density plasma-deposited oxide is etched back to the height of the nitrite interface by the rice etch, and the nitrogen cut is removed by hot phosphoric acid; ΒΒ direction $•程/, deposition first— Layer charge storage layer, worm layer and nitrite ;; Β-Β, direction process seven: nitriding annihilation 并 and forming a closed region with ion _; Β-Β' Fang Shang process person · · high oblique The horn ions are implanted to form the bungee and the source.

P070020-TW 7 1332261 Detailed description, such as the 7-volume and implementation of the thief-integrated image in the implementation of the details of the implementation of the details of the practice of the relevant art knows the technical familiarity of the invention related to the reduction of the roots of the county And the drawings, any of them, i can easily understand the related objects and advantages of the present invention. [Embodiment] Month > Drawing - Shown is a schematic cross-sectional view of the structure of the present invention. The XOR-type SONOS-type flash memory structure has a lower s〇N〇s type fast• _memory element 1 and an upper S〇N〇S type_memory element 3, and its structure is bottom-up order The method includes: a channel of the base layer 11 for use as a channel of the lower S0N0S type flash memory device, wherein the channel is provided with a drain 111 and a source 112; a first layer (oxide layer - tantalum nitride) - Oxide layer 12, used as the charge storage layer of the lower SONOS-type flash memory device 1 121 charge storage layer u can be a nano-crystal, can be a dream oxide (sj_rjch Oxide, Si2-X0), may also be a hydroxide (H+ Containing Oxide). a control gate layer 21 for isolating the lower SONOS-type flash memory component 1 and the upper SONOS-type flash memory component 3, and the control gate is replaced by a lower SONOS-type flash memory device 1 and an upper SONOS type The flash element is shared by the t body element 3; the control gate layer 21 is formed by a polycrystalline stone, and the two ends of the control gate layer 21 are filled with a high-density plasma-deposited oxide (High). Density - Plasma Chemical Vapor Deposition, HDP-CVD) 211. The high-density electric, slurry-deposited oxide 211 can also be used with Tetraethylorthosilicate (TEOS) or other dielectrics with good hole filling ability.

8 P070020-TW 1332261 Replacement of layers. 'a first germanium (oxide layer - nitride nitride oxide layer) 32 for use as the charge storage layer 321 of the upper "SONOS type flash memory element 3; the charge storage layer - 321 may be one nanometer The crystal (Nan〇-crystal) may be replaced by a Si-rich Oxide (Si2-xO) or a hydroxide-containing compound (H+^〇ntajnjng Oxide). A remote layer 31 is used as a channel for the upper S0N0S type flash memory device 3. The channel has a drain 311 and a source 312 on both sides. • The present invention has a plurality of voltage nodes for allowing the upper SONOS-type flash memory device 1 and the lower SONOS-type flash memory device 3 to operate separately. The upper and lower flashes of the upper and lower flashes of the 'It's body elements can also be controlled separately without interfering with each other. * month is shown in Figure 1. It is a schematic diagram of the top view of the present invention. The manufacturing method of the stacked SONOS-type flash memory structure can be seen by the A_A, the direction process and the B_B' direction process. First active area (Active

Area, AA)41 The Shallow Trench Isolation (STI) region 42 will form in the AA, and the square will form a 'Hardmask' in the direction of the 间·Β, forming the interpolar region 43 ° Figure 2 is a schematic diagram of the direction of the production process of the present invention. The steps of the Α-Α' direction manufacturing method include the following processes: Α-Α direction process 1: deposition of charge storage layer, polysilicon and tantalum nitride 1000; * as shown in Figure 2, 'first 〇Ν〇 (oxidation layer _ gas The fossil layer_oxide layer 12 is deposited on the base layer 11 of the white stone as the lower element. Redeposition of polycrystalline stone eve 2. * = then deposit nitriding 4, and the thickness of the nitriding 4 is 2GG~3QGnm, and

9 P070020-TW 161 This is defined as the side hard mask of the wire area 4彳/wire trench isolation area a. The charge storage layer 12 may be a nano-crystal, or may be a hydrogenated compound (SRidi 0xide, Sj2x〇) or a hydrogenated material (H Containing Oxide). , AA direction process nitride nitride is defined by photoresist, like 彳, photoresist removal, so that it forms active area / shallow trench isolation area 1〇〇1; as shown in Figure 2B, with photoresist at nitride eve 4 The active area 41 / shallow trench isolation area 42 is defined above. The vacant dream of Nitrogen is removed from the side and stopped on the polycrystalline stone eve 2 to expose the shallow trenches from each other so that the subsequent filaments are squatted. The photoresist is removed to expose the remaining nitride. ,, Direction Process 2: Using a hard-shielding film of nitriding stone, the polycrystalline stone is etched out by ion etching. As shown in Fig. 3C, the ion layer is defined by 5, layer 12). Polycrystalline germanium 2 will be treated with tantalum nitride 4 as a hard light-shielding film, and the side will be stopped at the first -0N0 (oxide-nitriding oxide _ Α Α Α 方向 direction) process 4003. * The ruthenium substrate is ion-etched and formed The shallow trench isolating area isolation area is not 'Qi base body 11 with ion _ 5, so that it forms a shallow trench 1004 to repair the early · ' ” storm 1 ion after the moment 5, must use oxidation (CornerRgu ^ financial base 11 Damage to the surface, _ can be shaped into a rounded coffee curry shallow county can be filled with high mosquito electric pulp Shen Wei 211

P070020-TW 1332261 Forms an isolation region which is then densified by high temperature annealing. The high density plasma deposited oxide 211 may be replaced by a tetraethyl orthosilicate. A-A' direction process 6: high-density plasma-deposited oxides are planarized by chemical mechanical polishing, and tantalum-density plasma-deposited oxides are etched back to the height of the tantalum nitride interface. Phosphoric acid removal 1〇〇5; Figure 2F, using chemical mechanical polishing (Chemical Mechanical)

Polishing) Flattening the areal density plasma deposited oxide 211, and then high-density plasma

The oxide 211 is deposited at the height of the side-to-nitrogen cut 4 interface, which is subsequently removed by hot phosphoric acid. Please refer to FIG. 4, which is a schematic diagram of the direction production process of the present invention. The steps of the Β-Β direction manufacturing method include the following processes: Β _ Β 'direction process one · comprehensive deposition of nitride nitrite in the form of Figure III F formed as a hard mask 2 〇〇〇; as shown in Figure 4A The depositional nitriding dream 4 is on the polycrystalline stone eve 2, and the thickness of the nitriding stone eve 4 is 2 〇 Q~3 (X) nm, and the shape is derived from the gate region milk. Directional system ^. Nimium is defined by photoresist, #刻, photoresist removal, so that it forms the gate region 2001; Four no, the gate region 43 is defined by a photoresist on the nitride nitride eve 4. The nitrogen in the empty mining area is cut by 4 _ wire, and the light resistance of the wire is left in the exposed area. Zhou to process three: _ nitride material hard cover, the polycrystalline dream to ion etched out of 2002; away from the hand, more secret 2 will cut nitrogen 4 # hard shading film, and then use the layer) 12 definition, The _ kiosk in the first ONO (oxidation layer - nitride eve - oxidation

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II 1332261 B-B' direction Yusi··County ditch_region (4) Density Wei deposit oxide filled 2003; As shown in 'D', use oxidation to repair the damage of the ion wall to the sidewall surface and fill in the density of electricity The oxide 211 is deposited to form an isolation layer. Wherein the high density plasma deposited oxide 211 can be replaced by tetraethyl spleen. BB-direction process 5: high-density plasma oxide is planarized by chemical mechanical polishing' and high-density plasma-deposited oxide is used to laterally return to the height of the niobium nitride surface, which is subsequently removed by hot phosphoric acid; S 4E shows 'using chemical mechanical polishing (chemjca| Mechanjca| P〇_ng) to fertilize the previously deposited oxide 211 + and then returning the high-density plasma-deposited oxide 211 to the side of the nitride At the height of the interface, the nitride nitride 4 is subsequently removed by hot phosphoric acid. Upon reaching the process, the lower S0N0S type flash memory device has a substantially completed structure except for the doping of the m-pole 111 and the source 112. This addition is formed after the structure of the upper S0N0S type flash memory component 3 is completed. B-B direction weighting 6. Depositing charge storage layer, stupid layer and nitride nitride 2 (10) 5. As shown in Fig. 4F, 'deposited the second 0N0 (oxide layer-nitride oxide layer) 32 on the control layer 2 and the high density plasma oxide 211 isolation layer as the upper s〇N〇s type flashing brother recall The charge storage layer 321 of the bulk element 3. The deposition method is the same as that of the first layer 0N0 (oxide layer-nitride oxide layer) 12, and therefore will not be described again. Subsequently, an epitaxial layer 31 and a tantalum nitride 4 are deposited on the upper crucible 32. The upper SONOS-type flash memory component 3 is stacked back-to-back with the lower s〇N〇s type flash memory component 1. 'B-B' direction process seven: nitride material is defined and formed by the ion side

P070020-TW 1332261 Polar Region 2006. As shown in FIG. 4G, the tantalum nitride 4 defines the gate region 43 by photoresist, and then the epitaxial layer 3彳 and the second tantalum N〇 (oxide layer_tantalum nitride_oxide) are gradually formed by ion etching 5 32. The high-density electro-deposited oxide 211, the first 〇N〇 (oxide layer-nickel oxide layer oxidized layer) 12, etc. are removed and a shallow trench isolation region 42 is formed on the stone substrate μ. The depth of the shallow channel region 42 is calculated by calculating the base of the scorpion so as to facilitate the formation of the channel when the element is operated by ion implantation of the electrode 111 and the source 112 and subsequent lateral diffusion. B_B, Directional Process 8: Ion implantation with high oblique angle to form the immersion and source 2007. As shown in Figure 4, the oblique angle ions are used to implant to form a immersed (1) source = 2. Up to this process, the structure of the stacked type s〇N〇s type flash memory of the present invention has been completed. The above is not limited to the spirit and scope of the present invention, and the sighs are too much for the Wei Weiwei of the present invention, and therefore the professional town of Wei_ County of the present invention · The book _ the application _ shape is subject to. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing the structure of the present invention. Figure = is a schematic diagram of the top view of the present invention. The three series are the Α·Α of the invention, and the schematic diagram of the direction production process. Figure 2A is a schematic diagram of the invention, the direction process-structure diagram II is the structure of the invention - Α, direction process, ... m - η long one structure. Fig. 2C is the α-Α of the present invention, and the figure 3D is the Α·Α of the present invention. Schematic diagram of the four-way structure of the universal process. 13

P070020-TW Figure E is the Α·Α of the present invention, and the five-way structure of the direction process is shown in Fig. 2, which is the Β·Α of the present invention, and Fig. 4 is the Β·Β of the invention, and the direction drawing diagram is The present invention is a B Β Β 方向 方向 方向 方向 方向 方向 方向 为本 为本 为本 为本 为本 为本 为本 为本 为本 为本 为本 为本 为本 为本 为本 为本 为本 为本 为本 为本 为本 为本 为本 为本 为本 为本 。 。 。 The structure is not intended to be the B_B of the invention, and the direction of the remainder = Fig. 4F is the B_B of the invention, and the direction is: Figure 4 G is the forest (four) of the Β·Β, direction _ is the invention Β·Β , Directional process Eight-way process five structure display: [Main component symbol description] 1- Lower SONOS type flash memory component 11 - 矽 base 111 - drain 112 - source 12 - first ΟΝΟ 121 - charge storage position 2 Polycrystalline Xi 21 - Control Gate Layer 211 - High Density Plasma Deposition Gasification - 3 - Upper SONOS Type Flash Memory Element 31 - Stupid Layer 311 - Bungee 312 - Source 1332261 32 - Second 0N 〇 321 _ Charge storage location: 4-nitridium nitride - 41 - active region 42 - shallow channel isolation region 43 - gate region 5 - ion etching 6 - still oblique ion implantation • 1000-A-A' direction process - 1001 - A-A' direction process two 1002-A-A' direction process three 1003-A-A1 direction process four 1004A-A' direction process five 1005-A-A' direction process six 2000- B-B' direction process one 2001- B-B' direction process two _ 2002-B-B' direction process three 2003- B-B' direction process four 2004- B-B' direction process five 2005- B_B' direction process six 2006- B-B, direction process seven 2007- B-B' direction process eight

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Claims (1)

1332261 X. Patent application Fan Park·· 1. - Stacking and changing SONOS-type flash memory structure, with the structure components of the lower s〇N〇s type flash memory and the upper SONOS type flash memory, and The structure of the SONOS-type flash memory includes a bottom-up sequence, which is used as a channel for the lower SON〇s type flash memory component, and has a drain and a source on both sides of the channel. The first layer (oxide layer - nitride nitride oxide layer), used as the charge storage layer of the lower sonos type flash § memory element; - control gate layer for isolating the lower s〇N〇s Flash memory and upper SONOS flash memory, and the control gate is shared by the lower and upper s〇N〇s type flash memory; the first 〇NQ (oxidized layer-rat fossil-oxidation) Layer) 'used as the charge storage layer of the upper sonos type flash memory component; - the worm layer is used as the channel of the upper S0N0S type flash memory component, and there is a immersion and a Source. 2. The stacked type s〇N〇s type flash memory structure as described in the first paragraph of the patent application, wherein the upper SONOS-type flash memory component, and the lower s〇N〇s plastic flash memory The components are stacked back to back. 3. The stacked SONOS-type flash memory structure as described in claim 1, wherein the charge storage layer of the first electrode may be a nanocrystal. 4. The stacked SONOS-type flash memory structure according to claim 1, wherein the first 〇N0 charge storage layer may be a ruthenium oxide. 5. The stacked SONOS-type flash memory structure according to item 1 of the patent application scope, wherein the first 0N0 charge storage layer may be an oxygen-containing oxide. 6. The stacked SONOS-type flash memory junction 16 P070020-TW 1332261 according to claim 1, wherein the control gate layer is formed by a polycrystalline chip. 7_ The stacked SONOS-type flash memory structure as described in claim 1 wherein both ends of the control gate layer are filled with a high-density plasma-deposited oxide. • 8· * Patent Application Scope 7 The stacked S SONOS-type flash memory structure described in 'where the bulk plasma deposited oxide can also be replaced with a tetraethyl etchant. The stacked SONOS-type flash memory structure according to claim 1, wherein the second 〇N〇 charge storage layer may be a nanocrystal. . • 1 〇 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 11. The stacked SONOS-type flash memory node according to claim 1, wherein the charge storage layer of the second layer may be - hydroxide-containing. , ° • A stacking type of SONOS flash memory structure, divided into α_α, direction process and Β-Β 'direction process' to produce lower s〇N〇s type flash memory element and upper SONOS type The structure of the flash memory component; ° μ ^ wherein the Α-Α' direction fabrication method comprises the following steps: 八八方向process - deposition of charge storage layer, polycrystalline material and nitride nitride; Α-Α direction process 2: Nitriding (4) photoresist definition, side, fine removal, so that the active area / shallow trench isolation area; Α Α direction process three: paste nitriding broken hard shadow film, more (four) defined by ion money; A direction axis four: silk ship ion side, 郷 渠 沟 隔离 isolation area; ' 'direction t 五 five' shallow channel trench isolation area filled with high density plasma deposition oxide; P070020-TW 17 direction process six: high density The plasma-deposited oxide is planarized by chemical mechanical polishing, and the high-density plasma-deposited oxide is etched back to the height of the tantalum nitride interface, which is subsequently removed by hot t-acid; the β-direction fabrication method contain The following steps: Directional process -: such as AA, direction process six, comprehensive deposition of nitrite on its Β β; to gas path two: nitride nitride by photoresist definition, button engraving, photoresist removal, make β β Forming the gate region; Directional process 3: Using the nitrite as a hard mask, the polycrystalline stone is defined by the ion money; the seven-direction process is four: the shallow trench isolation region is electrically destroyed by the high-density deposition oxide Filling; 'direction process five: the deposition of oxides to the density is planarized by chemical mechanical polishing, and the density of the plasma is deposited by the plasma to etch back the height of the side nitride interface, which is then filled with hot Removal; = Direction Process 6: Deposition of charge storage layer, worm layer, and nitrite eve; Direction Process 7: Nitride is defined by photoresist and ion residue is used to form gate region 13:::2,: High oblique ion implantation forms the drain and source. Structure: = the stacked S0N0S type flash memory structure described above. Where the upper S〇N〇S type flash memory element is connected, the lower SONOS type flash memory tree structure is stacked back to back. P070020-TW Nanocrystals. - The charge storage layer of the medium-μA direction process may be - the stacked type S0N〇S type flash memory type St' described in Item No. 12, wherein the charge storage layer of the 'direction' process may be a structure The stacked type S〇N〇S type flash memory described in item ^ contains hydroxide. The 储存-direction storage layer may be a stacked type s_ type flash memory as described in item 12 for the high-density plasma deposition oxidation of the tetraethyl gangue eve of the 'A_A' direction process. Acidate substitution. Touch 12 object 4 (four) type flash memory production method 'where the Β-Β, the direction of the charge storage layer can be - not ^} ^, 'mouth crystal 〇 range of the 12th type of stacked s〇 The N 〇 s flash memory i Wei (10) method, wherein the charge storage layer of the regenerative direction process can be a stacking type S0N0S flash memory method described in item 12 of the range of '12 The BB, the charge storage layer of the direction process may be a 3-gas oxide. The stacked type S〇N〇S type flash memory method described in the above item is the method, wherein the B_B, the high-density electropolymerized deposition oxide T of the direction process uses a tetraethyl etchant Replace. P070020-TW