TW200847406A - A fabrication method of stacked multibit SONOS type flash memory - Google Patents

Abstract

A stacked SONOS type flash memory fabrication and method, where the structure includes a silicon substrate and an epitaxy layer acting as channels of bottom and top of SONOS type flash device, respectively; a first ONO and second ONO layers acting as charge storage dielectrics; a control gate (CG) acting as common gate control on top and bottom of SONOS type device; a high density plasma chemical vapor deposition (HDP-CVD) filling in both sides of CG to define CG width and providing isolation of top and bottom of SONOS type devices. The ONO layers could be nano-crystals with resulting high performance in charge retention characteristics.

Description

200847406 IX. Invention: [Technical field of invention] Feng Ben ^ Ming involves a kind of stacked type S0N0S type flash memory structure and its fabrication has a lower S0N0S type flash memory and two upper type flash memory The second component 'and the upper SONOS-type fast body component and the lower s〇N〇s-type flash flash (four) component back-to-back stack #, so that 2: the dynamic gate flashes the flash (4) the storage capacity is multiplied, and the saturation is greatly reduced. - Stacked S0N0S type flash memory structure and its manufacturing method. [Prior Art], the traditional floating gate flash memory uses the basic digital data storage concept '〇 is low level, *Ί' is high level' to do the action of writing and erasing data. High level"1 "The electrons are injected into the floating gate (called write) by channel hot electrons (Channel H〇t ectrcn, CHE). The lower order, 〇, is the floating of electrons by F_N penetration (Fowler_Nordheim Tunneling) The gate is erased. Another kind of Nitride Storage flash memory that has emerged in recent years, and the use of nitriding cerium (SiN) is sandwiched between two oxide layers to become "oxidized ruthenium-nitrogen." Oxide-Nitride-Oxide (0N0) structure. This 〇 曰〇 is used to replace the gate oxide layer in the MOS device to form a charge storage layer. The structure of the flash memory is "Silicon_Oxide-Nitride-Oxide_Silicon" (S0N0S), so it is also called S0N0S memory. It uses the channel's hot electrons to inject electrons into the tantalum nitride layer (called a write), and the hot hole (HH) neutralizes the electrons at the same location for erasing. For S0N0S memory, the charge storage location can be on the left or right of the storage layer.

P070020-TW 4 200847406 Side, its position is determined by the write voltage applied to the source or drain. This results in a two-dimensional storage that doubles the memory storage compared to traditional single-element floating gate memory. However, this method has a significant disadvantage in actual operation, that is, there is a mismatch between the electrons to be written and the holes required for erasing. If the number of people is increased, the mismatch phenomenon will cause serious damage and the threshold voltage of the erase will be saturated, and the f-subsequence cannot be effectively eliminated. In addition, the ugly charge is caused by drift and diffusion, resulting in a small axis. The age of the reservoir will be distributed by money: However, even with the above problems to be solved, the s〇n〇s flash memory has been verified by American Supermicro (AMD) and has been mass-produced. SUMMARY OF THE INVENTION The object of the present invention is to increase the data storage capability of the flash memory, and the estimation can be increased from =^ yuan/fourth order to shouting yuan/sixteen gifts, and if combined with multi-level crystal Ievel Chip, MLC) technology 'That is, each bit has four steps, then this new structure: large, increase the storage capacity to four bits / two hundred and fifty-six. The novel structure has the following 4 SONOS type flash memory and an upper s〇N〇s single flash memory: the components, and the bottom-up order of the structure includes: a silk layer, a first layer, a control a gate layer, a second layer of germanium, and an epitaxial layer. For the production method, the method is divided into two directions: the direction of the Β Β Β, the direction process, the front t, the M-STI structure. The latter is to make the lower s 〇 body and the SQNQSm, _ milli-element structure; The WV direction fabrication method comprises the following steps: A-/V square product - layer charge storage layer, polycrystalline stone eve and nitrite eve; ° process 2: nitrogen cut by photoresist definition, side, photoresist wire, so that shape

P070020-TW 5 200847406 Into active area/shallow trench isolation area; A-A' direction process III: Using tantalum nitride as a hard mask, the polycrystalline germanium is defined by ion characterization, and the direction of the process is four. Etching and forming a shallow trench isolation region; A Α direction process 5. The shallow trench isolation region is filled with high-density plasma deposition oxide; A-direction process 6: high-density plasma deposition oxide is chemical mechanical polishing The flattening 'and the south density plasma deposited oxide is returned to the height of the tantalum nitride interface by the surname, and the tantalum nitride is subsequently removed by hot phosphoric acid; B, wherein the B-B' direction manufacturing method comprises the following steps:矽 矽 Ϊ Ϊ : : : : : : : : : : : : : : : : : : : : : : : AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA It is defined by photoresist, etched, and photoresist removed to form BB, which is the gate region. Direction 4: 3: When the nitrogen is cut, it is hard-masked, and the polycrystalline cation class b_b is defined; Β·Β, ί Ϊ=4: The shallow isolation area is highly dense The oxide is filled; "13⁄4·· The density plasma deposited oxide is planarized by chemical mechanical polishing, and the high-density plasma deposited oxide is etched back to the height of the tantalum nitride interface, the tantalum nitride Subsequently, the RD is removed by hot phosphoric acid; the seven directions | g ^ 丄 ·, the direction of the formation, the second layer of the charge storage layer, the remote layer and the nitrite; ^7·Nitric oxide is defined by the photoresist And the ion side is used to form the gate region B and the direction is cut. · Domain; 皲\· implants the drain and source with oblique angle ion implantation. P〇70〇2〇-tw 6 200847406 The detailed implementation of the present invention, the thief map = two; 峨 to make any skilled person related to the technology = and according to the description #的露露的内容和图, anyone who is familiar with the relevant art can (4) transfer the purpose and advantages of the hair. [Embodiment] Please refer to the figure-shown as a schematic cross-sectional view of the structure of the present invention. And the 31 SONOS type flash memory structure has a lower s〇N〇s type flash memory element - and an upper SON 〇s stroboscopic surface element 3, and the bottom-up order of the structure includes: a stone base layer 11 for use as a channel of the lower s〇N〇Sfi flash memory device], the channel is provided with a drain 1 and a source 112 on both sides; a first germanium (oxide layer-nitriding)矽_Oxide layer 12, used as the lower S0N0S ^ [flashing memory layer 1 charge storage layer cl, · the charge storage layer ip T in nano-crystal, (Nano_crystal), may be a rich stone The oxidized oxide (sr. rjch Oxide, Si2_x〇) may also be replaced by a hydroxide (H+ c〇ntaNng 〇χ _. A control gate layer 21 ' is used to isolate the lower S0N0S type flash memory device. 1 and the upper S0N0S type flash memory device 3, and the control gate is shared by the lower S0N0S type flash memory device 1 and the upper s〇N0S type flash memory device 3, and the control gate layer 21 is used. Formed by a polycrystalline stone, and the two ends of the control gate layer 21 are filled with a high-density plasma-deposited oxide (High Densit) y

Plasma Chemical Vapor Deposition, HDP-CVD) 211, the high density plasma deposited oxide 211 can also be used with tetraethyl ortho-decanoate

7 P070020-TW 200847406 (Tetraethylorthosilicate, TEOS) or other dielectric layer with good hole filling ability. a second germanium (oxide layer-nickel oxide layer) 32 for use as the charge storage layer 321 of the upper SONOS-type flash memory device 3; the charge storage layer 321 may be a nanocrystal (Nano-crysta)丨), may be a Si-rich Oxide (SLO), or may be replaced by a hydroxide (H+^〇nta丨Oxide). An epitaxial layer 31 is used as a channel for the upper S0N0S type flash memory device 3, and has a drain 311 and a source 312 on both sides of the channel. The present invention has a plurality of voltage nodes for allowing the upper S〇N〇S type flash memory element 1 and the lower SONOS type flash memory element 3 to operate separately. The right half bit and the left half bit of the upper and lower flash memory components can also be controlled separately without interfering with each other. Referring to FIG. 2, it is a schematic diagram of the top view of the present invention. The manufacturing method of the stacked SONOS-type flash memory structure can be seen by the A-A, the direction process and the day-day process. The first age ^_(AGt|ve A"ea, the Shallow Trench Isolation (STI) region 42 will form in the direction of AA, and then form a gate region 43 in the direction of BB with a hard mask (Hardmask). 〇Please refer to Figure 3, which is a schematic diagram of the direction of A_A, and the manufacturing process of A-A' direction includes the following processes: A-A' direction process 1: deposition of charge storage layer, polysilicon and tantalum nitride As shown in FIG. 2A, a first 0N0 (oxide layer_tantalum nitride-oxide layer) 12 is deposited on the blank base substrate 11 as a charge storage layer 121 of the lower element. The polycrystalline germanium 2 is redeposited.

P070020-TW 200847406 Finally, the tantalum nitride 4 is deposited, and the thickness of the tantalum nitride 4 is 2〇〇~3〇〇nm, and it is derogated as the active region 41/shallow trench isolation region 42 Light-shielding film.八中"Hai charge storage layer 12 can be a nano-crystal, can be a Si-rlch Oxide (Sb-X〇), or can be a hydroxide (H) Containing 〇xjde) replaces each other. / AA direction process 2: Nitride is defined by photoresist, engraved, and photoresist removed to form active area/shallow trench isolation area 1001; ... as shown in Figure 3, with photoresist at nitrite eve 4 The active area 41 / shallow trench isolation area 42 is defined above. The nitriding of the open area; (iv) by the butterfly, and stopped on the polycrystalline stone to expose the shallow trench isolation area 42 for the subsequent side of the hybrid body. The photoresist is removed to expose the remaining nitride. j to I & 2 uses nitriding 11 as a hard mask, and (iv) crystal % is defined as ion residue 1002. The 7F 'polycrystalline ♦ 2-phase nitrogen cut 4 is used as a hard light-shielding film, and the layer is further layered 12 . Definition, the etching stops at the first 〇N〇 (oxide layer-nitrite eve-oxidation 1003. to ^4, the substrate is ionic paste, and forms a shallow trench isolation region isolation region=never' the impurity 11 is ionized Side 5, so that it forms a shallow channel ditch from the 'direction process five · · 嶋 以 with high-density plasma deposition oxide filled with New ί Ε Ε ' 当 当 当 当 当 当 当 当 当 当 当 当 当 当 当 当 当 当 当 当 当 当 当The ion-doping etching can damage the 矽 base U and the clothing, and at the same time, the rounding of the angle can be formed.

P070020-TW 9 200847406 (Corner Rounding). The shallow trench can be filled with a high density plasma deposited oxide 211 to form an isolation region, which is then densified by high temperature annealing. The high density plasma deposited oxide 211 may be replaced by a tetraethyl orthosilicate. A-A' direction process ··········· Then, 1〇〇5 is removed by hot phosphoric acid; as shown in FIG. 2F, 'high-density plasma-deposited oxide 211 is planarized by chemical mechanical polishing, and then high-density plasma is deposited as oxide 211. Etching is etched back to the height of the tantalum nitride 4 interface, which is subsequently removed by hot phosphoric acid. Please refer to FIG. 4 , which is a schematic diagram of the direction production process of the invention B-B. The steps of the B_B' direction manufacturing method include the following processes: B-B' direction process 1. Comprehensive deposition of tantalum nitride in the structure formed in Fig. 3F as a hard mask film 2000; as shown in Fig. 4A, comprehensive deposition The tantalum nitride 4 is in the polysilicon 2, and the tantalum nitride 4 has a thickness of 200 to 300 nm and is defined as the gate region 43. BB-direction process II··Nitric oxide is defined by photoresist definition, surname engraved, and photoresist removed to form gate region 2001; as shown in Fig. 4B, the photoresist region is defined by the photoresist on the nitride nitride eve 4. 43. The nitrogen cut 4 in the empty ore zone is removed from the side and the wire is removed to leave the nitrided stone on the exposed field. BB direction system private 2: using the nitriding stone as a hard shading film, the polycrystalline stone is defined by the ion residue in 2002; 0 C C shows that the eve of the crystal will be a hard mask. Redefined by ion residue 5, the contact stops at the first 〇N〇 (oxide layer-nitridation oxidation

P070020-TW 10 200847406 Layer) 12. The B-B' direction process is filled with 2003; · The shallow channel trench isolation area is deposited with high-density plasma deposition oxide. As shown in Figure 4, the oxidation is used to repair the ion-to-wall surface tid! The plasma oxide 211 is formed to form an isolation layer. The high-density electro-hydraulic material Wei 211 can be replaced by a tetraethyl ortho-salt salt. Directional manufacturing five. Flattening to the plasma oxide oxide by chemical mechanical polishing, f high-density deposition of oxide (10) engraved back to the side of the nitrogen-cut interface, the nitride was subsequently removed by hot phosphoric acid 2004, • As shown in Fig. 4E, using chemical mechanical polishing (Chemical Mechanical flattened the surface deposited oxide 21彳, and then the high-density plasma deposited milk 11 is returned to the height of the interface of the nitride bed at the end of the nitrite. The nitride zebra 4 is subsequently removed by hot phosphoric acid. You arrive at the process, and the lower s〇N〇s type flash memory device] structure is substantially completed, except for the doping of the drain 111 and the source 112. This doping is formed after the structure of the upper SONOS-type flash memory device 3 is completed. B-direction manufacturing, deposition of a charge storage layer, an epitaxial layer, and tantalum nitride. As shown in FIG. The second 〇N〇 (oxide layer_nitriding second_oxide layer) 32 is on the control gate 2 and the high-density lanthanum oxide 21 isolation layer, so that the charge of the upper s〇n〇s type gate element 3 is lost. Layer 321 is deposited in the same manner as the first layer ΟΝΟ (oxide layer _ nitrogen final oxide layer) 12 described above, Therefore, the stupid layer 31 and the nitride nitride 4 are deposited on the second crucible 32. The upper SONOS-type flash memory component 3, and the lower s〇N〇s type flash memory component 1 Stacked back to back.

P070020-TW 11 200847406 Polar region m-direction system seven: Nitrogen cut is defined by photoresist and the gate is formed by ion _ such as _ G 7 ^ 'Nit cut 4 to define the impurity region 43, after the p =1 Day layer &, second (10) ("Xi oxidized H,) r2 deposited oxide 211, first 0N0 (oxide layer - nitride shi _ shi shi base body 11 forms a shallow trench isolation region 42. The depth of the impurity-shielded domain 42 must accurately calculate the exposed base of the stone body so that the ion implantation of the source m and subsequent lateral diffusion ([phase usion) can achieve the formation of the channel when the component operates. BB, direction process eight: The high oblique scales are implanted to form the bungee and the source. The Z-Η is shown as 'using high-angled ions to implant, so as to form the immersed 悧 and = already completed, Benfair (four) (four) paste structure The present invention is not limited to the spirit and scope of the present invention, and the advantages and disadvantages of the present invention are within the scope of the present invention. Therefore, the patent application scope of the present invention is as follows. The definition is based on the details. [Figure 1 is a schematic diagram of the structure of the present invention. Figure 2 is the top view layout of the present invention Figure 3 is a schematic diagram of the process of making the direction of the invention. The schematic diagram of the direction of the process is shown in the figure _ Α Α 方向 方向 方向 方向 方向 方向 方向 方向 方向 方向 方向 方向 方向 方向 方向 方向 。 。 。 。 。 明 明 明 明 明 明 明 明 明 明 Α Α Α Α Α Α Α Α Α Α .

P070020-TW 12 200847406 Fig. 2D is the A_A of the present invention, and the second diagram of the direction E is the fourth embodiment of the present invention, and the structure of the structure is shown in Fig. 3, "the system is evasive, the surface = five structures, and the circular diagram is four ( Β 方 方 方 方 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 Β Β Β Β Β Β Β Β Β Β ° ° ° ° ° ° ° ° Figure 4A is a schematic diagram of the Guardian Guardian αα i η~ χ孝王一,和,吉吉. Figure 4 is the Β Β of the invention, the direction of the second figure is the Β Β 二 二 二 二 二 二 二The Β Β 构 构 。 . . . . . . . . 八 八 八 八 八 八 八 八 八 八 八 八 八 八 八 八 料 料 料 料 料 料 料 料 料 料 料 料 料 料 料 【 【 【 【 【 【 【 【 【 【 【 【 • drain 112 • source 12 - first ΟΝΟ 121_ charge storage location 2 - polycrystalline eve 21 - control gate layer 211 - high density plasma deposited oxide 3 - upper SONOS type flash memory component 13 200847406 31 - stupid layer 311 - drain 312 - source 32 - second 〇 N 〇 321 - charge storage location 4 - tantalum nitride 41 - main Area 42 - Shallow Channel Separation Area 43 - Gate Area 5 - Ion Etching 6 - High Angle Ion Implantation 1000- A-A' Direction Process One 1001-AA Direction Process Two 1002_A-A' Direction Process Three 1003_A-A 'Direction process four 1004 A-A' direction process five 1005-A-A' direction process six 2000- B-B' direction process one 2001- BB, direction process two 2002- B-B' direction process three 2003- B- B' direction process four 2004- B-B' direction process five 2005- B-B' direction process six 2007-B-B' direction process seven

14 P070020-TW

Claims (1)

200847406 X. Patent application scope: 1· - Stacked S〇N〇S type flash memory structure with lower s〇n〇s type flash memory and upper S0N0S type flash memory structure The structure of the SONOS-type flash memory from bottom to top includes · 'a county body layer' is used as a channel for the lower S0N0S type flash memory component, and a drain and a source are provided on both sides of the channel Pole - - - - ΟΝΟ (oxide layer _ nitrogen cut_oxide layer), used as the charge storage layer of the lower s〇n〇s type flash memory device; - control gate layer, used to isolate the lower S0N0S record Flash memory and upper S0N0S flash memory, and the control gate is shared by the lower and upper s〇n〇s type flash memory; - second 0N0 (oxide layer - nitride dream - oxide layer), Used as a charge storage layer for upper s〇n〇s type flash memory components; • _ worm layer for use as a channel for upper s〇N〇s type flash memory components, both sides of the channel With "^ > and pole and '-source. 2_ The stacked type s〇N〇s type flash memory structure according to the first aspect of the patent application, wherein the upper SONOS type flash memory component is stacked back-to-back with the type of flash memory. Pso 3. The stacked type s〇N〇s type I structure according to claim 1, wherein the first 〇N〇 charge storage layer may be a nano crystal; 4) as claimed in the patent scope The stacked type s〇N〇s type flash memory structure according to the above, wherein the first charge storage layer of the first layer may be a fluorene oxide. 5. The stacked type according to claim 1 a sonos-type flash memory structure, wherein the charge storage layer of the first 〇N〇 may be a hydroxide-containing material. [P070020-TW 15 200847406 6. The stacked type s〇N as described in the scope of the patent application. The 〇s style structure, wherein the control gate layer is formed by a polysilicon. . Heart ^ 7. For example, the stacked s〇N〇s type flash memory structure of the patent application ’ 彳 愧 愧 愧 愧 愧 愧 愧 愧 愧 愧 愧 愧 愧 两端 两端 两端 两端 两端 两端 两端 两端 两端 两端 两端 两端 两端 两端 两端 两端 两端 两端 两端 两端• ^Stacked type s〇N〇s type described in item 7 of the patent application scope: wherein the high-density electrodeposited deposited oxide may also be a stacked type as described in item 1 of tetraethyl = 9·^^ S〇N〇S type flash memory junction 1 gentleman, the charge storage layer of the second 〇N〇 can be - nanocrystal. ^ Z fiber circumference of the first item of the stacked type S〇N〇S type _ memory body knots Shi Shen 1 ^ rhyme - 〇Ν〇 charge storage layer can be - sec-oxide. The charge layer of sputum can be - money oxide. The production method of the square A-type S〇N〇S type flash memory structure is divided into AA, body and B_B' direction process, so that the lower S〇N〇S type flash memory ^ cow, upper SONOS The structure of the flash memory component; A,: the second, the direction manufacturing method comprises the following steps: · depositing a charge storage layer, polycrystalline dream, and nitrite eve; to process 2: nitriding stone is defined by photoresist, and the remainder , remove the photoresist, make it, the moving area / shallow trench isolation area; use the nitrite as a hard shading 臈, the polycrystalline 矽 is defined by ion etching; A_A, the direction of the king 矽 substrate is ion etched and formed shallow Ditch isolation area; "5. Shallow trench isolation area filled with high-density plasma deposited oxide 16 P070020-TW 200847406 , Full; AA direction process 6: High-density plasma-deposited oxide is planarized by chemical mechanical polishing And the high-density plasma-deposited oxide is etched back to the height of the tantalum nitride interface, which is subsequently removed by hot phosphoric acid; the middle 4 B_B' direction fabrication method comprises the following steps: B_B' direction process 2 B_B, direction process three: to process four: direction process five: B'B> to process six: B~B'W process seven: B direction process one: as A_A' direction process six, comprehensive deposition of tantalum nitride On the nitrite, the definition of the photoresist, the engraving, and the photoresist are removed to form the gate region; using the gasification fossil as the hard shading film, the polycrystalline stone is defined by the ion I insect; The isolation region is filled with high-density plasma-deposited oxide; the high-density plasma-deposited oxide is planarized by chemical mechanical polishing, and the plasma-deposited oxide is deposited to etch back to the height of the tantalum nitride interface. The ruthenium is subsequently removed by the thermal acid; the charge storage layer, the epitaxial layer and the tantalum nitride are deposited; the tantalum nitride is defined by the photoresist and formed by ion etching to form the gate region; to the process 8: ion implantation at a high oblique angle Into the formation of the bungee and source. Structure ^ item ^ stacked type S0N0S type flash memory ' /, ', the upper s〇N〇s type flash memory element junction P070020-TW 200847406 structure, and the lower SONOS type flash flash 愔 _ _ 14 = The application of the special _12th item of the stacked Fengshi Xi oxygen ^ process charge storage layer can be - 16 = the patent described in the scope of the 12th pile:: r method "where the charge of the butterfly = The material can be replaced by tetraethyl oxalate. 12 SQNQS flash memory method, wherein the charge storage layer of the Μ direction process can be a 1^Itfrr'® *12 s〇n^ Feng Shi Xi oxygen = method, which is to find Β·Β, the charge storage layer of the direction process may be a stacked type s〇n〇s type fast _ body 所述 according to item 12 of the 20iijt patent range, which is to find β·β, and the charged storage layer may be one Sonos I is used as a method in which the B_B, a high-density deposition oxide of the direction process P070020-TW 18 200847406 can be replaced by a tetraethyl ortho-decanoate. 19 P070020-TW