TWI323405B - Voltage regulation unit with zener diode and voltage regulation device thereof - Google Patents
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- 230000000087 stabilizing effect Effects 0.000 claims description 43
- 238000013507 mapping Methods 0.000 claims description 16
- 238000001514 detection method Methods 0.000 claims description 6
- 230000001105 regulatory effect Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 2
- 230000004913 activation Effects 0.000 claims 1
- 230000001276 controlling effect Effects 0.000 claims 1
- 238000007599 discharging Methods 0.000 claims 1
- 230000011664 signaling Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
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- 239000000428 dust Substances 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
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三達編號:TW3173PA 九、發明說明: 【發明所屬之技術領域】 ·· 本發明是有關於一種利用齊納二極體(Zener Diode) 之穩壓裝置,且特別是有關於一種可節省功率損耗之利用 齊納二極體之穩壓裝置。 【先前技術】 • 請參照第1A圖,其繪示傳統之利用齊納二極體之穩 壓裝置的電路圖。致能訊號EN用以致能穩壓裝置100。時 序訊號產生單元102受到致能訊號EN之驅動產生時序訊 號CLK,而電荷泵104根據時序訊號CLK來提高輸出電壓 Vout之電壓位準驅動負載裝置110。 請參照第1B圖,其圖繪示乃第1A圖中齊納二極體106 的電流對電壓曲線圖。當齊納二極體106操作於崩潰區 時,具有特殊之電壓對電流特性曲線;此時無論流經齊納 • 二極體106之電流Iz為何,齊納二極體106兩端之跨壓 仍實質上等於齊納二極體106之崩潰電壓Vzl,使得輸出 電壓Vout實質上等於崩潰電壓Vzl,而達到穩壓之效果。 然,傳統之穩壓裝置100具有若干缺點。 穩壓裝置100無法於輸出電壓Vout達到預定之電壓 位準時終止電荷泵104之運作。而電荷泵104係不停地運 作以提升輸出電壓Vout之電壓位準,並產生輸出電流經 由齊納二極體106導入接地位準。如此,將使得穩壓裝置 100具有耗電量較高及功率使用率(Power Efficiency)較 6 1323405Sanda number: TW3173PA IX. Description of the invention: [Technical field to which the invention pertains] · The present invention relates to a voltage regulator device using a Zener diode, and in particular to a power loss The Zener diode is used as a voltage regulator. [Prior Art] • Please refer to Fig. 1A, which shows a circuit diagram of a conventional voltage stabilizing device using a Zener diode. The enable signal EN is used to enable the voltage stabilizing device 100. The timing signal generating unit 102 is driven by the enable signal EN to generate the timing signal CLK, and the charge pump 104 drives the load device 110 according to the voltage level of the output voltage Vout according to the timing signal CLK. Please refer to FIG. 1B, which is a graph showing the current versus voltage of the Zener diode 106 in FIG. 1A. When the Zener diode 106 operates in the collapse region, it has a special voltage-to-current characteristic curve; at this time, regardless of the current Iz flowing through the Zener diode 106, the voltage across the Zener diode 106 is across. It is still substantially equal to the breakdown voltage Vzl of the Zener diode 106, so that the output voltage Vout is substantially equal to the breakdown voltage Vzl, and the voltage stabilization effect is achieved. However, the conventional voltage stabilizing device 100 has several disadvantages. The voltage stabilizing device 100 cannot terminate the operation of the charge pump 104 when the output voltage Vout reaches a predetermined voltage level. The charge pump 104 is continuously operated to raise the voltage level of the output voltage Vout, and the output current is led to the ground level via the Zener diode 106. In this way, the voltage stabilizing device 100 will have higher power consumption and power efficiency (Power Efficiency) than 6 1323405.
三達編號:TW3173PA 低之缺點。另外,由於齊納二極體106之溫度係數不為零, 使得齊納二極體106兩端之電壓會隨著溫度之變化而改 變。齊納二極體之溫度係數例如為正數。如此,穩壓裝置 100係更具有輸出電壓Vout會隨著溫度改變而變動之缺 請參照第1C圖,其繪示乃傳統之非利用齊納二極體 之穩壓裝置的電路圖。穩壓裝置1〇係經由運算玫大器〇P1 • 之輸出電壓Vol來致能電晶體Τχ,以提升輸出電壓v〇2之 電壓位準。而穩壓裝置10更將輸出電壓V〇2迴授至運算 放大器0P1之負端,以於輸出電壓Vo2之電壓位準高於輸 出電壓VI之電壓位準時,經由運算放大器ορι非致能電 晶體Tx,並經由電流源112將輸出電壓V〇2拉低。如此, 以負迴授之方式來對輸出電壓Vo2進行穩壓。然,由於穩 壓裝置10係需設置運算放大器0P1來對輸出電壓Vo2進 行穩壓’如此,穩壓裝置10係具有電路複雜及成本較高 ®之缺點。 【發明内容】 有鑑於此,本發明係提供一種利用齊納二極體(Zener Diode)之穩壓單元及穩壓裝置,其係具有耗電量較低、使 用功率較高、電路較為簡單及成本較低之優點。 根據本發明提出一種穩壓單元,用以接收電荷泵 (Charge Pump)輸出之驅動電壓,並對驅動電壓進行穩壓。 穩壓單元包括:電流映射單元、齊納二極體及偏鮮元。 7 1323405Sanda number: TW3173PA low disadvantage. In addition, since the temperature coefficient of the Zener diode 106 is not zero, the voltage across the Zener diode 106 changes with temperature. The temperature coefficient of the Zener diode is, for example, a positive number. Thus, the voltage stabilizing device 100 further has an output voltage Vout that varies with temperature. Refer to FIG. 1C, which shows a circuit diagram of a conventional voltage stabilizing device that does not utilize a Zener diode. The voltage regulator device 1 activates the transistor 经由 via the output voltage Vol of the operation 〇P1 • to increase the voltage level of the output voltage v 〇 2 . The voltage regulator device 10 further supplies the output voltage V〇2 to the negative terminal of the operational amplifier OP1, so that when the voltage level of the output voltage Vo2 is higher than the voltage level of the output voltage VI, the operational amplifier ορι non-enabling transistor Tx, and pulls the output voltage V〇2 low via current source 112. In this way, the output voltage Vo2 is regulated by a negative feedback method. However, since the voltage stabilizing device 10 is required to set the operational amplifier OP1 to regulate the output voltage Vo2, the voltage stabilizing device 10 has the disadvantages of complicated circuit and high cost. SUMMARY OF THE INVENTION In view of the above, the present invention provides a Zener Diode (Zener Diode) voltage stabilizing unit and a voltage stabilizing device, which have low power consumption, high power consumption, and relatively simple circuit. The advantage of lower cost. According to the present invention, a voltage stabilizing unit is provided for receiving a driving voltage of a charge pump output and regulating a driving voltage. The voltage stabilizing unit includes: a current mapping unit, a Zener diode, and a fresh element. 7 1323405
三達編號:TW3H3PA 電流映射單元包括電流主控端及電流從屬端。電流映射單 元用以接收驅動電壓,並根據驅動電壓於電流主控端及電 ·· 流從屬端分別產生第一電流訊號及第二電流訊號。齊納二 極體之負端耦接至電流主控端,正端接收固定電壓。齊納 二極體接收第一電流訊號’並控制驅動電壓之電壓位準實 質上等於預定電壓位準,以對驅動電壓進行穩壓。偏壓單 元用以接收第二電流訊號’並根據第二電流訊號來判斷驅 • 動電壓之電壓位準是否達到預定電壓位準,並根據第二電 流訊號產生控制訊號。其中,控制訊號係迴授至電荷泵, 以控制電荷泵產生驅動電壓。 根據本發明提出一種穩壓裝置,其中包括:電荷泵、 穩壓單元、偵測單元及時序訊號產生單元。電荷泵用以輪 出驅動電壓。穩壓單元包括:電流映射單元、齊納二極體 及偏壓單元。電流映射單元包括電流主控端及電流從屬 端。電流映射單元用以接收驅動電壓,並根據驅動電壓於 • 電流主控端及電流從屬端分別產生第一電流訊號及第二 電流訊號。齊納二極體之負端耦接至電流主控端’正端接 收固定電壓。齊納二極體接收第一電流訊號,並控制驅動 電壓之電壓位準實質上等於預定電壓位準,以對驅動電壓 進行穩壓。偏壓單元用以接收第二電流訊號’並根據第二 電流訊號來判斷驅動電壓之電壓位準是否達到預定電壓 位準,並根據第二電流訊號產生控制訊號。偵測單元用以 接收控制訊號’並根據控制訊號產生第一致能訊號。時序 訊號產生單元接收第一致能訊號,並根據第一致能訊號產 1323405Sanda number: TW3H3PA current mapping unit includes current master and current slave. The current mapping unit is configured to receive the driving voltage, and generate the first current signal and the second current signal respectively according to the driving voltage on the current main control end and the electric current flow. The negative terminal of the Zener diode is coupled to the current control terminal, and the positive terminal receives a fixed voltage. The Zener diode receives the first current signal 'and controls the voltage level of the driving voltage to be substantially equal to the predetermined voltage level to regulate the driving voltage. The biasing unit is configured to receive the second current signal ′ and determine whether the voltage level of the driving voltage reaches a predetermined voltage level according to the second current signal, and generate a control signal according to the second current signal. The control signal is fed back to the charge pump to control the charge pump to generate the driving voltage. According to the present invention, a voltage stabilizing device is provided, which comprises: a charge pump, a voltage stabilizing unit, a detecting unit and a timing signal generating unit. A charge pump is used to drive the drive voltage. The voltage stabilizing unit comprises: a current mapping unit, a Zener diode and a biasing unit. The current mapping unit includes a current master and a current slave. The current mapping unit is configured to receive the driving voltage, and generate the first current signal and the second current signal respectively according to the driving voltage on the current main terminal and the current slave end. The negative terminal of the Zener diode is coupled to the positive terminal of the current terminal to receive a fixed voltage. The Zener diode receives the first current signal and controls the voltage level of the driving voltage to be substantially equal to the predetermined voltage level to regulate the driving voltage. The biasing unit is configured to receive the second current signal ′ and determine whether the voltage level of the driving voltage reaches a predetermined voltage level according to the second current signal, and generate a control signal according to the second current signal. The detecting unit is configured to receive the control signal ’ and generate a first enable signal according to the control signal. The timing signal generating unit receives the first enabling signal and generates 1323405 according to the first enabling signal.
三號:TW3173PA 生時序訊號及反向時序訊號。其中,時序訊號及反向時序 訊號係輸出至電荷泵,而電荷泵根據時序訊號及反向時序 訊號產生驅動電壓。 為讓本發明之上述内容能更明顯易懂,下文特舉一較 佳實施例’並配合所附圖式,作詳細說明如下: 【實施方式】 請參照第2A圖’其繪示依照本發明較佳實施例之利 用齊納二極體之穩壓裝置的一電路圖。穩壓裝置2〇〇包括 時序訊號產生單元202、電荷泵204、穩壓單元206及偵 測單元208。時序訊號產生單元202用以接收致能訊號 EN ’並據以產生時序訊號CLK’及反向時序訊號CLKB。 電荷泵204係接收時序訊號CLK’及反向時序訊號CLKB並 據以產生輸出電壓Vout’來驅動負載裝置210。 穩壓單元206包括電流映射單元206a、齊納二極體 206b及偏壓單元206c。電流映射單元206a具有電流主控 端212a及一電流從屬端212b,電流映射單元206a接收輸 出電壓Vout’ ,並將輸出電壓Vout’作為驅動電壓,以 根據驅動電壓於電流主控端212a及電流從屬端212b分別 產生電流訊號II及電流訊號12。電流訊號π及12之電 流值係為相關。 齊納二極體206b之負端耦接至電流主控端212a,正 端接收固定電壓VB。齊納二極體206b係接收電流訊號 II,並控制輸出電壓Vout’之電壓位準實質上等於一預定 9 1323405No. 3: TW3173PA raw timing signal and reverse timing signal. The timing signal and the reverse timing signal are output to the charge pump, and the charge pump generates the driving voltage according to the timing signal and the reverse timing signal. In order to make the above-mentioned contents of the present invention more comprehensible, a preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 2A, FIG. A circuit diagram of a voltage stabilizing device using a Zener diode of the preferred embodiment. The voltage stabilizing device 2A includes a timing signal generating unit 202, a charge pump 204, a voltage stabilizing unit 206, and a detecting unit 208. The timing signal generating unit 202 is configured to receive the enable signal EN ' and generate the timing signal CLK' and the reverse timing signal CLKB accordingly. The charge pump 204 receives the timing signal CLK' and the reverse timing signal CLKB and generates an output voltage Vout' to drive the load device 210. The voltage stabilizing unit 206 includes a current mapping unit 206a, a Zener diode 206b, and a biasing unit 206c. The current mapping unit 206a has a current master terminal 212a and a current slave terminal 212b. The current mapping unit 206a receives the output voltage Vout' and uses the output voltage Vout' as a driving voltage to be dependent on the current voltage at the current master terminal 212a and the current slave. The terminal 212b generates a current signal II and a current signal 12, respectively. The current values of current signals π and 12 are related. The negative terminal of the Zener diode 206b is coupled to the current master terminal 212a, and the positive terminal receives the fixed voltage VB. The Zener diode 206b receives the current signal II and controls the voltage level of the output voltage Vout' to be substantially equal to a predetermined 9 1323405
號:TW3173PA :壓位準’以對輸出電壓v〇ut,$行穩壓。偏壓單元· 收電流訊號12 ’並根據電流訊號12來判斷輸出電屋 ^>ut之電壓位準是否達到預定電壓位準,並根據電流訊 〜12產生控制訊號sc。在本實施例中,固定電壓w例如 為接地電=’電流訊號u及12之電流值係例如為相等。 偵測單元208接收控制訊號sc,並根據控制訊號sc 來偵測輸出電壓Vout,是否達到預定之電壓位準;若是, 偵測單元係設定致能訊號,為非致能位準並迴授致 月色訊號EN至時序訊號產生單元2Q2,使時序訊號產生單 元202停止產生時序訊號CLK,及反向時序訊號ακΒ,以 終止電荷泵204之操作。如此,係可透過訊號迴授之方式 來終止電荷泵204操作’來達到降低耗電量及提高功率使 用效率之效果。 其中,偵測單元208更接收一系統致能訊號ENS,用 以致能穩壓裝置20(^系統致能訊號ENS係例如為電壓訊 號。當系統致能訊號ENS為非致能位準時,將使致能訊號 EN’係持續地位於非致能位準,進而使時序訊號產生單元 202及電荷泵204均持續地為非致能而無法產生輸出電壓 Vout’ 。當系統致能訊號ENS為致能位準時,將使得偵測 單元208開始偵測控制訊號SC來判斷電流訊號12之電流 值,並據以對電荷泵204進行控制。 請參照第2B圖,其繪示乃第2A圖中穩壓單元206的 詳細電路圖。在本實施例中,係以電流映射單元206a為 包括兩個P型金氧半導體(Metal Oxide Semiconductor,No.: TW3173PA: The pressure level is used to regulate the output voltage v〇ut, $. The biasing unit·receiving current signal 12 ′ determines whether the voltage level of the output electric appliance ^>ut reaches a predetermined voltage level according to the current signal 12, and generates a control signal sc according to the current signal~12. In the present embodiment, the fixed voltage w is, for example, the ground current = 'current signals u and 12, and the current values are, for example, equal. The detecting unit 208 receives the control signal sc, and detects whether the output voltage Vout reaches a predetermined voltage level according to the control signal sc; if the detection unit sets the enable signal, the non-enabled level is returned The moon color signal EN to the timing signal generating unit 2Q2 causes the timing signal generating unit 202 to stop generating the timing signal CLK and the reverse timing signal ακΒ to terminate the operation of the charge pump 204. In this way, the charge pump 204 operation can be terminated by means of signal feedback to achieve the effect of reducing power consumption and improving power efficiency. The detecting unit 208 further receives a system enable signal ENS for enabling the voltage stabilizing device 20 (the system enables the signal ENS to be, for example, a voltage signal. When the system enables the signal ENS to be a non-enabled level, it will enable The enable signal EN' is continuously at the non-enabled level, so that the timing signal generating unit 202 and the charge pump 204 are continuously disabled and cannot generate the output voltage Vout'. When the system enables the signal ENS to be enabled At the timing, the detecting unit 208 starts to detect the control signal SC to determine the current value of the current signal 12, and accordingly controls the charge pump 204. Please refer to FIG. 2B, which is shown in FIG. 2A. A detailed circuit diagram of the unit 206. In the present embodiment, the current mapping unit 206a includes two P-type metal oxide semiconductors (Metal Oxide Semiconductor,
號:TW3173PA MOS)電晶體Τ1及Τ2之電流鏡((:urrent Μι_)為例作說 Γ山電ΒθΜΤΐ及打^分別為電流主控端212&及電流從 屬端212b’而電流訊號㈣分別為電晶體η及η =電流。電晶體T1及Τ2之閘極(Gate)係相互耦接, ;'、玉.。虹⑻亦相互輕接,以接收輸出電壓V〇ut,,汲極 (Dr in)係刀別耦接至齊納二極體2_之負端及偏壓單元 206c如此電晶體T1及T2具有實質上相等之閉極一源 極電壓。而本實施例係以電晶體Τ1及Τ2之長寬比 (Width/Length)為相等為例作說明,這樣一來,電晶體T1 及T2係具有實質上相等之源極電流,亦即是電流訊號n 及12係為實質上相等。其中,電晶體τι係例如被配置為 順向導通之二極體(DiQde),其係溫度錢侧如為負數。 在本實施例中,預定電壓位準實質上為:_剩刺, S納一極體206b係用以將輪出電壓v〇ut,之電壓值固定 為至預定電壓位準。其中Vth為電晶㈣之臨界電壓, Vzl為齊納二極體2〇6b之崩潰電壓。當輸出電壓 之電壓位準為:驗〈㈣.㈣,亦即輸出電壓乂〇以,之電壓 位準過低未達到預定電壓位準時,電晶體71及12均為截 止’而電流訊號II及12之電流值係實質上均為零。當輸 出電壓Vout之電壓位準為:%说=叫+㈣丨,亦即輸出電壓 Vout之電壓位準達到預定電壓位準時,電晶體T1及τ2 均導通並操作於飽和區。此時,電流訊號η及12之電流 值係均大於零且為實質上相等。 偏壓單元206c包括電流源214及節點ΝΤ1,電流源 1323405No.: TW3173PA MOS) Current mirrors of transistor Τ1 and Τ2 ((:urrent Μι_) for example, Γ山Β Β ΜΤΐ and ^^ are current master terminal 212& and current slave terminal 212b' and current signal (four) are respectively The transistor η and η = current. The gates of the transistors T1 and Τ2 are coupled to each other; ', jade. Rainbow (8) is also connected to each other to receive the output voltage V〇ut, the drain (Dr The in) is coupled to the negative terminal of the Zener diode 2_ and the biasing unit 206c such that the transistors T1 and T2 have substantially equal closed-source voltages. This embodiment is an transistor Τ1. And the aspect ratio (Width/Length) of Τ2 is equal, for example, so that the transistors T1 and T2 have substantially equal source currents, that is, the current signals n and 12 are substantially equal. The transistor τι is, for example, configured as a diode-connected diode (DiQde), which is a negative value on the temperature side. In this embodiment, the predetermined voltage level is substantially: _ remaining thorn, S The nano-pole 206b is used to fix the voltage of the wheel voltage v〇ut to a predetermined voltage level, wherein Vth is a crystal The threshold voltage, Vzl is the breakdown voltage of the Zener diode 2〇6b. When the voltage level of the output voltage is: (<4). (4), that is, the output voltage is too low, the voltage level is too low. When the voltage level is normal, the transistors 71 and 12 are both off and the current values of the current signals II and 12 are substantially zero. When the voltage level of the output voltage Vout is: % said = called + (four) 丨, that is, the output When the voltage level of the voltage Vout reaches the predetermined voltage level, the transistors T1 and τ2 are both turned on and operate in the saturation region. At this time, the current values of the current signals η and 12 are both greater than zero and substantially equal. Including current source 214 and node ΝΤ1, current source 1323405
三達編號:TW3173PA 214係用以輸出-偏墨電流Ιβ由節點m導入接地位準。 節點NT1之電壓係由電流訊號12及偏壓電流^所決定。 當輸出電MVout’未達到預定電M位準時,冑晶體丁2為 截止’而電流訊號12之電流值係實質上為零。此時,節 點NT1之電壓位準將被偏壓電流IB偏壓至接近接地位 準。當輸出電壓Vout’達到預定之電壓位準時,電晶體 T2係為導通涵作於姊區。㈣,電流訊號i2之電流 值係大於零,以提升節點NT1之電壓位準從接近接地位準 開始拉高至接近輸出電壓v〇ut,之電壓位準,亦即是將節 點m之電壓位準被偏壓至高電壓位準。而在本實施例 ^節點NT1之電壓更用以作為控制訊號SC,輸出至摘測 早几2 0 8。 > Μ參照第2C圖’其纷示乃第2A圖中偵測單元2〇8的 詳、、’田電路圖。本實;^例係以彳貞測單元包括電晶體T3、 丁4及T5、緩衝器216及及閘(AndGate)218之電路為例作 說明。電晶體T3之源極係接收高電壓位準Vdd,閘極接收 接地,準’如此,使得電晶體T3恒為導通,以形成一連 接至=電壓位準Vdd之路徑,來將節點ντ2之電壓位準偏 壓至高電壓位準Vdd。電晶體Τ4及Τ5係為Ν型金氧半導 體電晶體’電晶體Τ5之源極接收接地位準,跡係與電 ,體Τ4之源極輕接’閘極用以接收系统致能訊號腿。電 =體T4之及極與電晶體T3之汲極耦接,以形成節點nt2, =極接收控制訊號%。電晶體Τ4及Τ5彼此串聯以形成-地路徑’來將節·點ΝΤ2之電壓位準偏壓至接地位準,而 1323405Sanda number: TW3173PA 214 is used for output-bias current Ιβ is introduced into grounding level by node m. The voltage of node NT1 is determined by current signal 12 and bias current ^. When the output power MVout' does not reach the predetermined electrical M level, the germanium crystal 2 is off and the current value of the current signal 12 is substantially zero. At this time, the voltage level of the node NT1 will be biased to a level close to the ground by the bias current IB. When the output voltage Vout' reaches a predetermined voltage level, the transistor T2 is fused to the 姊 region. (4) The current value of the current signal i2 is greater than zero, so as to raise the voltage level of the node NT1 from the ground level to the voltage level close to the output voltage v〇ut, that is, the voltage level of the node m Quasi-biased to a high voltage level. In the embodiment, the voltage of the node NT1 is used as the control signal SC, and is output to the second measurement after the measurement. > Μ Refer to Fig. 2C', which is a detailed view of the detection unit 2〇8 in Fig. 2A. This example is based on the circuit of the measuring unit including the transistors T3, D4 and T5, the buffer 216 and the gate (AndGate) 218. The source of the transistor T3 receives the high voltage level Vdd, and the gate receives the ground, so that the transistor T3 is always turned on to form a path connected to the voltage level Vdd to set the voltage of the node ντ2. The level is biased to a high voltage level Vdd. The transistors Τ4 and Τ5 are Ν-type MOS transistors. The source of the transistor Τ5 receives the grounding level, and the trace is electrically connected to the source of the body ’4. The gate is used to receive the system enable signal leg. The sum of the body and the body T4 is coupled to the drain of the transistor T3 to form the node nt2, and the pole receives the control signal %. The transistors Τ4 and Τ5 are connected in series to each other to form a ground path' to bias the voltage level of the node ΝΤ2 to the ground level, and 1323405
—達編遗:TW3173PA 此接地路徑係由控制訊號%及系統致能訊號ENS來控制。 在本實施例中’系統致能訊號ENS及致能訊號EN,之 致能位準均為高電壓位準,而非致能位準均為低電壓位 準。當系統致能訊號ENS為非致能位準時,無論控制訊號 SC之位準為何,致能訊號εν’均被控制為非致能位準。 此時穩壓裝置200係為非致能。當系統致能訊號ENS為致 能位準而控制訊號sc為高電壓位準時,系統致能訊號ENS 與控制訊號SC將分別致能電晶體T4及T5,以將節點NT2 之電壓位準拉低至接地位準,使得節點NT2之電壓位準為 低電壓位準,進而使得致能訊號EN,為非致能位準。如 此’彳貞測早元2 0 8係可根據處於向電壓位準之控制味發sc 來使致能訊號EN’為非致能位準,以經由時序訊號產生單 元202來非致能電荷泵204之操作。 當糸統致能訊號ENS為致能位準而控制訊號· sc為低 電壓位準時,控制訊號SC關閉電晶體T4,使得節點NT2 之電壓位準為高電壓位準’進而使得致能訊號en,•為致能 位準。如此’偵測單元208係可根據處於低電塵位準之控 制訊號SC來使致能訊號EN’為致能位準,以經由時序訊 號產生單元202來致能電荷泵204之操作。 時序訊號產生單元202例如為一般周知之時序訊號產 生電路’如第2D圖所示。時序訊號產生單元2〇2係接收 致能訊號EM’ ,以經由反向器將電壓位準反向之特性輸出 時序訊號CLK’及反向時序訊號CUB。而電荷泵2〇4亦例 如為一般通知之電荷泵電路,如第2E圖所示。電荷泵2〇4 13 1323405- 达编遗: TW3173PA This ground path is controlled by the control signal % and the system enable signal ENS. In this embodiment, the enable level of the system enable signal ENS and the enable signal EN are both high voltage levels, and the non-enable levels are low voltage levels. When the system enable signal ENS is non-enabled, the enable signal εν' is controlled to a non-enabled level regardless of the level of the control signal SC. At this time, the voltage stabilizing device 200 is disabled. When the system enable signal ENS is enabled and the control signal sc is at a high voltage level, the system enable signal ENS and the control signal SC respectively enable the transistors T4 and T5 to lower the voltage level of the node NT2. Up to the ground level, the voltage level of the node NT2 is a low voltage level, so that the enable signal EN is a non-enabled level. In this way, the early detection unit can make the enable signal EN' be disabled according to the control level of the voltage level to enable the non-enable charge pump via the timing signal generating unit 202. 204 operation. When the system enable signal ENS is the enable level and the control signal sc is the low voltage level, the control signal SC turns off the transistor T4, so that the voltage level of the node NT2 is a high voltage level, thereby enabling the enable signal en , • is the level of enabling. Thus, the detecting unit 208 can enable the enable signal EN' as an enable level according to the control signal SC at the low dust level to enable the operation of the charge pump 204 via the timing signal generating unit 202. The timing signal generating unit 202 is, for example, a well-known timing signal generating circuit' as shown in Fig. 2D. The timing signal generating unit 2〇2 receives the enable signal EM' to output the timing signal CLK' and the reverse timing signal CUB via the reverse voltage characteristic of the inverter. The charge pump 2〇4 is also, for example, a generally notified charge pump circuit as shown in Fig. 2E. Charge pump 2〇4 13 1323405
三達編號:TW3173 PA 係接收時序訊號CLK’ 、反向時序訊號CLKB及高電壓位準 Vdd,並受到時序訊號CLK’及反向時序訊號CLKB之控制 ‘· 來產生輸出電壓Vout’ 。其中,高電壓位準Vdd係例如為 電荷泵204之輸入電壓。 負载裝置210例如為快閃記憶體(F1 ash)。輸出電壓 Vout’係用以輸入至作為快閃記憶體之資料線(Bit Line),來提供電壓將電子注入快閃記憶體記憶單元 • (Memory Cell)中電晶體之懸浮層(Floating Gate),來進 行資料寫入;或提供電壓來將電子由懸浮層吸出,來進行 資料清除。 本實施例雖僅以電流訊號II及12之電流大小實質上 相同為例作說明’然’電流訊號n及12亦可為其他任意 比例。本實施例雖僅以電流映射單元2〇以為包括兩個p 型金氧半導體電晶體T1及T2之電流鏡為例作說明,然, 電流映射單元206a並不侷限於本實施例之結構’而更可 籲為其他形式之電流鏡’例如為串疊組態(Cascode)電流 鏡’或為其他可輸出兩個電流值大小相關之電流訊號之電 路結構。本實施例雖僅以將致能訊號EN,輸入時序訊號產 生器202來間接地對電荷泵2〇4進行控制,然,本實施例 之穩壓裝置200亦可選擇具有致能訊號接腳之電荷泵gw 裝置,並將致能訊號EN,直接地輸入電荷泵204來對電荷 泵204之操作進行控制。 本實施例之利用齊納二極體之穩壓單元及穩壓裝置 係根據輸出電壓來產生兩個電流值相關之電流訊號。本實 1323405Sanda number: TW3173 PA receives the timing signal CLK', the reverse timing signal CLKB and the high voltage level Vdd, and is controlled by the timing signal CLK' and the reverse timing signal CLKB to generate the output voltage Vout'. The high voltage level Vdd is, for example, the input voltage of the charge pump 204. The load device 210 is, for example, a flash memory (F1 ash). The output voltage Vout' is input to a data line (Bit Line) as a flash memory to supply a voltage to inject electrons into the floating gate of the transistor in the memory cell. To write data; or to provide voltage to suck electrons out of the suspension layer for data removal. In this embodiment, the current values of the current signals II and 12 are substantially the same as an example. The current signals n and 12 may be in any other ratio. In the present embodiment, only the current mirror unit 2 is used as an example of a current mirror including two p-type MOS transistors T1 and T2. However, the current mapping unit 206a is not limited to the structure of the embodiment. Other forms of current mirrors can be called 'Cascode current mirrors' or other circuit structures that can output two current value related current signals. In this embodiment, the charge pump 2〇4 is indirectly controlled by the input of the enable signal EN, and the voltage regulator device 200 of the present embodiment can also select the enable signal pin. The charge pump gw device and the enable signal EN are directly input to the charge pump 204 to control the operation of the charge pump 204. The voltage stabilizing unit and the voltage stabilizing device using the Zener diode of the present embodiment generate current signals related to two current values according to the output voltage.本实 1323405
三達編號:TW3173PA 施例之利用齊納二極體之穩壓單元及穩壓裝置係輸入其 中一電流訊號至齊納二極體,來對輸出電壓進行穩壓,並 '· 轉換另一電流訊號為控制訊號,以根據控制訊號來判斷輸 出電壓是否已達到預定之電壓位準。本實施例之利用齊納 二極體之穩壓單元更迴授控制訊號至電荷泵,以於輸出電 壓達到預定之電壓位準時非致能電荷泵。如此,本實施例 之利用齊納二極體之穩壓單元係可有效地改善傳統穩壓 • 裝置無法在輸出電壓達到預定之電壓位準時關閉電荷 泵,而具有耗電量高及功率使用效率低之缺點,而具有降 低耗電量及提高功率使用效率之優點。 另外,本實施例之利用齊納二極體之穩壓單元及穩壓 裝置係利用齊納二極體與實質上為順向偏壓之二極體之 電流主控端來將輸出電壓偏壓至預定電壓位準,而順向導 通之二極體之溫度係數為負數。如此,順向導通之二極體 更可對齊納二極體進行溫度係數之補償,以降低溫度對輸 ^ 出訊號位準之影響。這樣一來,本實施例之利用齊納二極 體之穩壓單元及穩壓裝置係可有效地解決傳統利用齊納 二極體之穩壓裝置輸出電壓易受到溫度影響而偏移之缺 點,而具有輸出電壓位準較為穩定之優點。 再者,本實施例之利用齊納二極體之穩壓單元及穩壓 裝置係以包括齊納二極體、電晶體及邏輯閘之簡單電路結 構,搭配負迴授電路之應用來達到穩壓與控制電荷泵之效 果。如此,本實施例之利用齊納二極體之穩壓單元及穩壓 裝置係可有效地改善傳統非利用齊納二極體之穩壓裝置 15 1323405Sanda Number: TW3173PA The Zener diode's voltage regulator unit and voltage regulator are used to input one of the current signals to the Zener diode to regulate the output voltage and '· convert another current. The signal is a control signal to determine whether the output voltage has reached a predetermined voltage level based on the control signal. In this embodiment, the voltage stabilizing unit using the Zener diode further feedbacks the control signal to the charge pump to disable the charge pump when the output voltage reaches a predetermined voltage level. In this way, the voltage stabilizing unit using the Zener diode of the embodiment can effectively improve the conventional voltage regulator. The device cannot turn off the charge pump when the output voltage reaches a predetermined voltage level, and has high power consumption and power use efficiency. Low disadvantage, but has the advantage of reducing power consumption and improving power efficiency. In addition, the voltage stabilizing unit and the voltage stabilizing device using the Zener diode of the present embodiment bias the output voltage by using a Zener diode and a current main terminal of the substantially forward biased diode. To the predetermined voltage level, the temperature coefficient of the diode that is passed through is negative. In this way, the diode can be aligned with the nano-polar body to compensate for the temperature coefficient to reduce the effect of temperature on the output signal level. In this way, the voltage stabilizing unit and the voltage stabilizing device using the Zener diode in the embodiment can effectively solve the shortcoming that the output voltage of the voltage stabilizing device using the Zener diode is easily affected by temperature and is offset. And has the advantage that the output voltage level is relatively stable. Furthermore, the voltage stabilizing unit and the voltage stabilizing device using the Zener diode of the present embodiment are stabilized by a simple circuit structure including a Zener diode, a transistor and a logic gate, and a negative feedback circuit. Press and control the effect of the charge pump. In this way, the voltage stabilizing unit and the voltage stabilizing device using the Zener diode of the embodiment can effectively improve the conventional voltage stabilizing device that does not utilize the Zener diode. 15 1323405
三達編號:TW3173PA 電路複雜及成本較高之缺點,而具有電路結構簡單及成本 較為低廉之優點。 綜上所述,雖然本發明已以一較佳實施例揭露如上, 然其並非用以限定本發明。本發明所屬技術領域中具有通 常知識者,在不脫離本發明之精神和範圍内,當可作各種 之更動與潤飾。因此,本發明之保護範圍當視後附之申請 專利範圍所界定者為準。 1323405Sanda number: TW3173PA has the disadvantages of complicated circuit and high cost, and has the advantages of simple circuit structure and low cost. In view of the above, the present invention has been disclosed in a preferred embodiment, and is not intended to limit the present invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. 1323405
三達編號·· TW3173PA 【圖式簡單說明】 第1A圖繪示傳統之利用齊納二極體之穩壓裝置的電 路圖。 第1B圖繪示乃第1A圖中齊納二極體106的電流對電 壓曲線圖。 第1C圖繪示乃傳統之非利用齊納二極體之穩壓裝置 的電路圖。 • 第2A圖繪示依照本發明較佳實施例之利用齊納二極 體之穩壓裝置的一電路圖。 第2B圖繪示乃第2A圖中穩壓單元206的詳細電路圖。 第2C圖繪示乃第2A圖中偵測單元208的詳細電路圖。 第2D圖繪示乃第2C圖中控制訊號SC、系統致能訊號 ENS及致能訊號M’之真值表。 第2E圖繪示乃第2A圖中時序訊號產生單元202的詳 細電路圖。 【主要元件符號說明】 100、200 ··穩壓裝置 EN、EN’ :致能訊號 102、202 :時序訊號產生單元 CLK、CLK’ :時序訊號 104、204 :電荷泵Sanda Number·· TW3173PA [Simple Description of the Drawing] Figure 1A shows the circuit diagram of a conventional voltage regulator using a Zener diode. Fig. 1B is a graph showing the current versus voltage of the Zener diode 106 in Fig. 1A. Figure 1C shows a circuit diagram of a conventional voltage regulator that does not utilize a Zener diode. • Fig. 2A is a circuit diagram of a voltage stabilizing device using a Zener diode in accordance with a preferred embodiment of the present invention. FIG. 2B is a detailed circuit diagram of the voltage stabilizing unit 206 in FIG. 2A. FIG. 2C is a detailed circuit diagram of the detecting unit 208 in FIG. 2A. Figure 2D shows the truth table of the control signal SC, the system enable signal ENS and the enable signal M' in Figure 2C. Fig. 2E is a detailed circuit diagram of the timing signal generating unit 202 in Fig. 2A. [Main component symbol description] 100, 200 · · Voltage regulator EN, EN': Enable signal 102, 202: Timing signal generation unit CLK, CLK': Timing signal 104, 204: Charge pump
Vout、Vout’ :輸出電壓 106、206c :齊納二極體 17 1323405Vout, Vout': output voltage 106, 206c: Zener diode 17 1323405
三達編號:TW3173PASanda number: TW3173PA
Vzl :崩潰電壓 Iz:流經齊納二極體之電流 110、210 :負載裝置 206:穩壓單元 206a :電流映射單元 212a :電流主控端 212b :電流從屬端 _ II、12 :電流訊號 VB :固定電壓 206c :偏壓單元 SC:控制訊號 208 :偵測單元 ENS :系統致能訊號 CLKB :反向時序訊號 ΤΙ、T2、T3、T4、T5 :電晶體 ® Vth :臨界電壓 214 .電流源 NT1、NT2 :節點 IB .偏壓電流 Vdd :高電壓位準 216 :緩衝器 218 :及閘Vzl: breakdown voltage Iz: current flowing through the Zener diode 110, 210: load device 206: voltage regulator unit 206a: current mapping unit 212a: current master terminal 212b: current slave terminal _ II, 12: current signal VB Fixed voltage 206c: bias unit SC: control signal 208: detection unit ENS: system enable signal CLKB: reverse timing signal ΤΙ, T2, T3, T4, T5: transistor® Vth: threshold voltage 214. current source NT1, NT2: node IB. Bias current Vdd: high voltage level 216: buffer 218: and gate
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