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TW200821814A - Voltage regulation unit with zener diode and voltage regulation device thereof - Google Patents

Voltage regulation unit with zener diode and voltage regulation device thereof Download PDF

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Publication number
TW200821814A
TW200821814A TW95141418A TW95141418A TW200821814A TW 200821814 A TW200821814 A TW 200821814A TW 95141418 A TW95141418 A TW 95141418A TW 95141418 A TW95141418 A TW 95141418A TW 200821814 A TW200821814 A TW 200821814A
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signal
voltage
current
unit
driving voltage
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TW95141418A
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TWI323405B (en
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Yung-Feng Lin
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Macronix Int Co Ltd
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Abstract

A voltage regulation unit with a Zener diode receives a driving voltage outputted from a charge pump and regulates the driving voltage roughly at a constant voltage value. The voltage regulation unit comprises a current mapping unit, a Zener diode and a biasing unit. The current mapping unit comprises a master current end and a slave current end. The master current end and the slave current end receive the driving voltage and generate a first current signal and a second current signal according to the driving voltage respectively. The Zener diode receives the first current signal and holds the driving voltage roughly at a constant voltage level. The biasing unit receives the second current signal and generates a control signal according to the second current signal. Wherein, the control signal is sent to the charge pump and used to control the charge pump generating the driving voltage.

Description

200821814200821814

• 三達編號:TW3173PA 九、發明說明: 【發明所屬之技術領域】 本發明是有關於一種利用齊納二極體(Zener Diode) 之穩壓裝置,且特別是有關於一種可節省功率損耗之利用 齊納二極體之穩壓裝置。 【先前技術】 , 請參照第1A圖,其繪示傳統之利用齊納二極體之穩 壓裝置的電路圖。致能訊號EN用以致能穩壓裝置1〇〇。時 序訊號產生早元10 2受到致能訊ί虎EN之驅動產生時序afl 號CLK,而電荷泵1〇4根據時序訊號CLK來提高輸出電壓 Vout之電壓位準驅動負載裝置11〇。 請參照第1B圖,其圖繪示乃第1A圖中齊納二極體106 的電流對電壓曲線圖。當齊納二極體106操作於崩潰區 時,具有特殊之電壓對電流特性曲線;此時無論流經齊納 ( 二極體106之電流Iz為何,齊納二極體1〇6兩端之跨壓 仍實質上等於齊納二極體106之崩潰電壓Vzl,使得輸出 電壓Vout實質上等於崩潰電壓Vzl,而達到穩壓之效果。 然,傳統之穩壓裝置100具有若干缺點。 穩壓裝置1〇〇無法於輸出電壓Vout達到預定之電壓 位準時終止電荷泵104之運作。而電荷泵1〇4係不停地運 作以提升輸出電壓Vout之電壓位準,並產生輸出電流經 由齊納二極體106導入接地位準。如此,將使得穩壓裝置 1〇〇具有耗電量車父南及功率使用率(Power Efficiency )較 6 200821814• TRIDA number: TW3173PA IX. Description of the invention: [Technical field of the invention] The present invention relates to a voltage regulator device using a Zener diode, and in particular to a power loss reduction A Zener diode voltage regulator is used. [Prior Art], refer to FIG. 1A, which shows a circuit diagram of a conventional voltage stabilizing device using a Zener diode. The enable signal EN is used to enable the voltage regulator 1〇〇. The timing signal generates the early element 10 2 and is driven to generate the timing afl number CLK, and the charge pump 1〇4 drives the load device 11〇 according to the timing signal CLK to increase the voltage level of the output voltage Vout. Please refer to FIG. 1B, which is a graph showing the current versus voltage of the Zener diode 106 in FIG. 1A. When the Zener diode 106 operates in the collapse zone, it has a special voltage-to-current characteristic curve; at this time, regardless of the current flowing through the Zener (the current Iz of the diode 106, the Zener diode 1〇6 The voltage across the voltage is still substantially equal to the breakdown voltage Vzl of the Zener diode 106, so that the output voltage Vout is substantially equal to the breakdown voltage Vzl, and the voltage stabilization effect is achieved. However, the conventional voltage regulator device 100 has several disadvantages. 1〇〇 The operation of the charge pump 104 cannot be terminated when the output voltage Vout reaches a predetermined voltage level. The charge pump 1〇4 is continuously operated to raise the voltage level of the output voltage Vout, and generates an output current via Zener II. The pole body 106 is introduced into the grounding level. Thus, the voltage regulator device 1 has a power consumption and the power utilization rate (Power Efficiency) is higher than 6 200821814.

- 三達編號:TW3173PA 低之缺點。另外,由於齊納二極體1〇β之溫度係數不為零, 使得齊納二極體106兩端之電壓會隨著溫度之變化而改 變。齊納二極體之溫度係數例如為正數。如此,穩壓袭置 100係更具有輸出電壓V〇ut會隨著溫度改變而變動之缺 點0 清參照弟1C圖,其繪示乃傳統之非利用齊納二極體 之牙€、壓裂置的電路圖。穩壓裝置1 〇係經由運算放大器Op 1 之輸出電壓Vol來致能電晶體τχ,以提升輸出電壓v〇2之 電壓位準。而穩壓裝置10更將輸出電壓v〇2迴授至運算 放大态0P1之負端,以於輸出電壓V〇2之電壓位準高於輪 出電壓VI之電壓位準時,經由運算放大器op〗非致能電 晶體Tx,並經由電流源112將輸出電壓v〇2拉低。如此, 以負迴授之方式來對輸出電壓V〇2進行穩壓。然,由於穩 壓裝置ίο係需設置運算放大器0P1來對輸出電壓v〇2進 行穩壓’如此’觀裝置1G係具有電路複雜及成本較高 之缺點。 【發明内容】 有鑑於,,本發日㈣提供—_用_ ^ ^ ^ ^ ^ 衣置其係具有耗電量較低、使 用功率杈Ί路較為簡單及成本較低之優點。 根據本發明提出-種穩壓單元,用以接收電荷豕 (Charge P_)輸出之驅動電壓,並對驅 释 穩壓單元包括:電流映射單元 延仃把 耵早兀、齊納二極體及偏壓單元。 7 200821814- Sanda number: TW3173PA Low disadvantage. In addition, since the temperature coefficient of the Zener diode 1 〇 β is not zero, the voltage across the Zener diode 106 changes with temperature. The temperature coefficient of the Zener diode is, for example, a positive number. In this way, the voltage regulator hits the 100 series and has the disadvantage that the output voltage V〇ut will change with the temperature change. 0 Refer to the 1C diagram, which is a traditional non-utilizing the Zener diode. Set the circuit diagram. The voltage regulator device 1 enables the transistor τ 经由 to output the voltage level of the output voltage v 〇 2 via the output voltage Vol of the operational amplifier Op 1 . The voltage regulator device 10 further returns the output voltage v〇2 to the negative terminal of the operational amplification state 0P1, so that when the voltage level of the output voltage V〇2 is higher than the voltage level of the wheel-out voltage VI, the operational amplifier op is used. The transistor Tx is disabled and the output voltage v〇2 is pulled low via the current source 112. In this way, the output voltage V〇2 is regulated by a negative feedback method. However, since the voltage regulator ίο needs to be provided with the operational amplifier OP1 to regulate the output voltage v 〇 2, the device 1G has the disadvantages of complicated circuit and high cost. SUMMARY OF THE INVENTION In view of the above, (4) provides the advantage of using _ ^ ^ ^ ^ ^ clothing, which has lower power consumption, simpler power usage, and lower cost. According to the invention, a voltage stabilizing unit is provided for receiving a driving voltage of a charge 豕 (Charge P_) output, and the voltage release unit includes: a current mapping unit, a 耵 耵, a Zener diode, and a bias Pressure unit. 7 200821814

三達編號:TW3173PA 電流映射單元包括電流主控端及電流從屬端。電流映射單 元用以接收驅動電壓,並根據驅動電壓於電流主控端及電 流從屬端分別產生第一電流訊號及第二電流訊號。齊納二 極體之負端耦接至電流主控端,正端接收固定電壓。齊納 二極體接收第一電流訊號,並控制驅動電壓之電壓位準實 質上等於預定電壓位準,以對驅動電壓進行穩壓。偏壓單 元用以接收第二電流訊號,並根據第二電流訊號來判斷驅 動電壓之電壓位準是否達到預定電壓位準,並根據第二電 流訊號產生控制訊號。其中,控制訊號係迴授至電荷泵, 以控制電荷泵產生驅動電壓。 根據本發明提出一種穩壓裝置,其中包括:電荷泵、 穩壓單元、偵測單元及時序訊號產生單元。電荷泵用以輸 出驅動電壓。穩壓單元包括:電流映射單元、齊納二極體 及偏壓單元。電流映射單元包括電流主控端及電流從屬 端。電流映射單元用以接收驅動電壓,並根據驅動電壓於 電流主控端及電流從屬端分別產生第一電流訊號及第二 電流訊號。齊納二極體之負端耦接至電流主控端,正端接 收固定電壓。齊納二極體接收第一電流訊號,並控制驅動 電壓之電壓位準實質上等於預定電壓位準,以對驅動電壓 進行穩壓。偏壓單元用以接收第二電流訊號,並根據第二 電流訊號來判斷驅動電壓之電壓位準是否達到預定電壓 位準,並根據第二電流訊號產生控制訊號。偵測單元用以 接收控制訊號,並根據控制訊號產生第一致能訊號。時序 訊號產生單元接收第一致能訊號,並根據第一致能訊號產 200821814Sanda number: TW3173PA The current mapping unit includes a current master and a current slave. The current mapping unit is configured to receive the driving voltage, and generate the first current signal and the second current signal respectively according to the driving voltage at the current main terminal and the current slave terminal. The negative terminal of the Zener diode is coupled to the current control terminal, and the positive terminal receives a fixed voltage. The Zener diode receives the first current signal and controls the voltage level of the driving voltage to be substantially equal to the predetermined voltage level to regulate the driving voltage. The biasing unit is configured to receive the second current signal, and determine whether the voltage level of the driving voltage reaches a predetermined voltage level according to the second current signal, and generate a control signal according to the second current signal. The control signal is fed back to the charge pump to control the charge pump to generate the driving voltage. According to the present invention, a voltage stabilizing device is provided, which comprises: a charge pump, a voltage stabilizing unit, a detecting unit and a timing signal generating unit. The charge pump is used to output the drive voltage. The voltage stabilizing unit comprises: a current mapping unit, a Zener diode and a biasing unit. The current mapping unit includes a current master and a current slave. The current mapping unit is configured to receive the driving voltage, and generate the first current signal and the second current signal respectively according to the driving voltage at the current main terminal and the current slave end. The negative terminal of the Zener diode is coupled to the current control terminal, and the positive terminal receives a fixed voltage. The Zener diode receives the first current signal and controls the voltage level of the driving voltage to be substantially equal to the predetermined voltage level to regulate the driving voltage. The biasing unit is configured to receive the second current signal, and determine whether the voltage level of the driving voltage reaches a predetermined voltage level according to the second current signal, and generate a control signal according to the second current signal. The detecting unit is configured to receive the control signal and generate the first enabling signal according to the control signal. The timing signal generating unit receives the first enabling signal and generates the first enabling signal according to the first enabling signal.

• 三達編號:TW3173PA 生時序訊號及反向時序訊號。其中,時序訊號及反向時序 訊號係輸出至電荷泵,而電荷泵根據時序訊號及反向時序 訊號產生驅動電壓。 為讓本發明之上述内容能更明顯易懂,下文特舉一較 佳實施例,並配合所附圖式,作詳細說明如下: 【實施方式】 γ 清參知弟2 A圖,其緣示依照本發明較佳實施例之利 用齊納二極體之穩壓裝置的一電路圖。穩壓裝置2〇〇包括 時序訊號產生單元202、電荷泵204、穩壓單元206及偵 測單元208。時序訊號產生單元202用以接收致能訊號 EN’ ,並據以產生時序訊號CLK’及反向時序訊號CLKB。 電荷泵204係接收時序訊號CLK’及反向時序訊號CLKB並 據以產生輸出電壓Vout’來驅動負載裝置210。 穩壓單元206包括電流映射單元206a、齊納二極體 206b及偏壓單元206c。電流映射單元206a具有電流主控 端212a及一電流從屬端212b,電流映射單元206a接收輸 出電壓Vout’ ,並將輸出電壓Vout,作為驅動電壓,以 根據驅動電壓於電流主控端212a及電流從屬端212b分別 產生電流訊號II及電流訊號12。電流訊號Π及12之電 流值係為相關。 齊納二極體206b之負端耦接至電流主控端212a,正 端接收固定電壓VB。齊納二極體206b係接收電流訊號 II,並控制輸出電壓Vout’之電壓位準實質上等於一預定 9 200821814• Sanda number: TW3173PA raw timing signal and reverse timing signal. The timing signal and the reverse timing signal are output to the charge pump, and the charge pump generates the driving voltage according to the timing signal and the reverse timing signal. In order to make the above-mentioned contents of the present invention more comprehensible, a preferred embodiment will be described below in conjunction with the accompanying drawings, and the following detailed description will be made as follows: [Embodiment] γ 清参知弟 2 A diagram, its meaning A circuit diagram of a voltage stabilizing device utilizing a Zener diode in accordance with a preferred embodiment of the present invention. The voltage stabilizing device 2A includes a timing signal generating unit 202, a charge pump 204, a voltage stabilizing unit 206, and a detecting unit 208. The timing signal generating unit 202 is configured to receive the enable signal EN', and accordingly generate the timing signal CLK' and the reverse timing signal CLKB. The charge pump 204 receives the timing signal CLK' and the reverse timing signal CLKB and generates an output voltage Vout' to drive the load device 210. The voltage stabilizing unit 206 includes a current mapping unit 206a, a Zener diode 206b, and a biasing unit 206c. The current mapping unit 206a has a current master 212a and a current slave 212b. The current mapping unit 206a receives the output voltage Vout' and uses the output voltage Vout as a driving voltage to be dependent on the current terminal 212a and the current according to the driving voltage. The terminal 212b generates a current signal II and a current signal 12, respectively. The current values of current signals 12 and 12 are related. The negative terminal of the Zener diode 206b is coupled to the current master terminal 212a, and the positive terminal receives the fixed voltage VB. The Zener diode 206b receives the current signal II and controls the voltage level of the output voltage Vout' to be substantially equal to a predetermined 9 200821814

• 三達編號:TW3173PA 電壓位準,以對輸出電壓^扯,進行穩壓。偏壓單元2〇6C 接收電流訊號12,並根據電流訊號12來判斷輸出電壓 but之電壓位準是否達到預定電壓位準,並根據電流訊 唬12產生控制訊號sc。在本實施例中,固定電壓νβ例如 為接地電位,電流訊號Π及12之電流值係例如為相等。 偵測單元208接收控制訊號SC,並根據控制訊號SC 來侦剩輸出電壓Vout’是否達到預定之電壓位準;若是, f ,測單元208係設定致能訊號EN,為非致能位準並迴授致 此戒就EN’至時序訊號產生單元2〇2,使時序訊號產生單 疋2〇2停止產生時序訊號以!^,及反向時序訊號^〇,以 〜止電荷泵204之操作。如此,係可透過訊號迴授之方式 來終止電荷泵204操作,來達到降低耗電量及提高功率使 用效率之效果。 其中’偵測單元208更接收一系統致能訊號ENS,用 ,致能穩壓裝置2〇〇。系統致能訊號ENS係例如為電壓訊 《 。當系統致能訊號ENS為非致能位準時,將使致能訊號 EN係持續地位於非致能位準,進而使時序訊號產生單元 202及電荷泵204均持續地為非致能而無法產生輸出電壓 V〇u1:’ °當系統致能訊號ENS為致能位準時,將使得偵測 留一 早7^ 208開始偵測控制訊號sc來判斷電流訊號12之電流 值’並據以對電荷泵204進行控制。 請參照第2B圖,其繪示乃第2A圖中穩壓單元206的 洋細電路圖。在本實施例中,係以電流映射單元2〇6a為 包括兩個p型金氧半導體(Metal Oxide Semiconductor, 200821814• Sanda number: TW3173PA voltage level, to regulate the output voltage. The biasing unit 2〇6C receives the current signal 12, and determines whether the voltage level of the output voltage but reaches a predetermined voltage level according to the current signal 12, and generates a control signal sc according to the current signal 12. In the present embodiment, the fixed voltage νβ is, for example, a ground potential, and the current values of the current signals Π and 12 are, for example, equal. The detecting unit 208 receives the control signal SC, and detects whether the output voltage Vout' reaches a predetermined voltage level according to the control signal SC; if so, the measuring unit 208 sets the enabling signal EN to be a non-enabled level and The feedback is caused by the EN' to the timing signal generating unit 2〇2, so that the timing signal generation unit 2〇2 stops generating the timing signal to the ^^, and the reverse timing signal ^〇, to stop the operation of the charge pump 204 . In this way, the charge pump 204 can be terminated by means of signal feedback to reduce power consumption and improve power efficiency. The detecting unit 208 further receives a system enable signal ENS, and activates the voltage stabilizing device 2〇〇. The system enable signal ENS is for example a voltage signal. When the system enable signal ENS is in an inactive level, the enable signal EN is continuously located at the non-enabled level, so that the timing signal generating unit 202 and the charge pump 204 are continuously disabled and cannot be generated. Output voltage V〇u1: '° When the system enable signal ENS is enabled, it will cause the detection to stay early 7^208 to start detecting the control signal sc to determine the current value of the current signal 12' and according to the charge pump 204 controls. Please refer to FIG. 2B, which is a circuit diagram of the voltage stabilizing unit 206 in FIG. 2A. In this embodiment, the current mapping unit 2〇6a includes two p-type metal oxide semiconductors (Metal Oxide Semiconductor, 200821814).

三達編號:TW3173PA M〇S)T及T2之電流航urrent 2係分別為電流主控端例作說 屬如212b ’而電流却 Q及言、、六 之源極電流1晶體Γ及12係分別為電曰曰曰題τ:, 源極(s〇_亦相=閑祕叫係相 〇)_)係分_接至=’以接㈣出電”咐, ΟΛΡ 要至齊納二極體206b之倉^ 及槌 Γ:如此太:晶體T1及T2具有實質上相Ϊ及偏髮單元 ,。而本實施例係以電晶體Π及Τ2上間麵1 (滿/Length)為相等為例作說明,這樣 '見比 及:;係具有實質上相等之源極電流,亦gp是*電晶趙Τ1 及12係為實質上相等。其中,電晶:電流訊^ 順向導通之二極體(DiQde),其係溫度係^被配置為 在本實施财,預定電職準實質 %為負數。 齊納二極體20613係用以將輸出電壓V〇Ut, 、^丨叫卜丨叫, 為至狀電壓位準。其巾vth為電晶體n固定Sanda number: TW3173PA M〇S) T and T2 current urrent 2 series are current main control terminal for example, such as 212b 'and current but Q and words, six source currents 1 crystal Γ and 12 series They are the electric 曰曰曰 τ:, the source (s〇_also phase = the secret is called the phase 〇) _) the system is _ connected to = 'to connect (four) power out 咐, ΟΛΡ to Zener two poles The volume of the body 206b and the 槌Γ: so too: the crystals T1 and T2 have substantially opposite and partial units, and in this embodiment, the upper surface 1 (full/Length) of the transistor Π and Τ2 are equal. For example, such a 'see ratio:: has a substantially equal source current, and gp is *Electronic crystal Zhao Yi 1 and 12 are substantially equal. Among them, electro-crystal: current signal ^ 顺通通二The polar body (DiQde), whose temperature system is configured to be in the implementation of the present invention, is substantially negative in the predetermined electric job. The Zener diode 20613 is used to output the voltage V〇Ut, Called, for the voltage level of the toe. Its towel vth is fixed for the transistor n

:?厂齊納二極體職之崩潰電壓。當輸出以 之= 錄準為:叫啼N|,亦即輸出電壓壓 立、’過低未達到預定電壓位準時,電晶體τι及T 止:而電流訊號11及12之電流值係實質上均為零。當輸 出私壓Vout之電壓位準為:驗=丨睁㈣,亦即輸出電壓 Vout之電壓位準達到預定電壓位準時,電晶體τι及丁2 均導通並操作於飽和區。此時,電流訊號η及12之電流 值係均大於零且為實質上相等。 偏壓單元206c包括電流源214及節點ΝΤ1,電流源 200821814:? The collapse voltage of the Zener diode. When the output is = the registration is: 啼N|, that is, the output voltage is pressed, 'too low does not reach the predetermined voltage level, the transistor τι and T stop: and the current values of the current signals 11 and 12 are substantially Both are zero. When the voltage level of the output Vout is V:== (4), that is, when the voltage level of the output voltage Vout reaches the predetermined voltage level, the transistors τι and D2 are both turned on and operate in the saturation region. At this time, the current values of the current signals η and 12 are both greater than zero and substantially equal. The biasing unit 206c includes a current source 214 and a node ΝΤ1, a current source 200821814

三達編號:TW3173PA 214係用以輸出-偏麈電流IB由節點跑導入接地位準。 節點m之電壓係由電流訊號12及偏壓電流_決定。 當輸出電壓Vout *達到預定電壓位準時,電晶體㈣ 截止,而電流訊號12之電流值係實質上為零。此時,節 點NT1之電壓位準將被偏壓電流Ιβ偏壓至接近接地位 準^當輸出電壓達到預定之電壓位準時,電晶體 T2係為導通亚操作於飽和區。此時,電流訊號i2之電流 值係大於零’以提升節點NT1之電準從接近接地位準 開始拉高至接近輸出電壓v〇ut,之電壓位準,亦即是將節 點NT1之電壓位準被偏壓至高電壓位準。而在本實施例 ^節點NT1之電壓更用以作為控制訊號沉,輸出至制 單元208。 "請參照第2C圖,其綠示乃第2A圖中偵測單元的 坪細電路圖。本實施例係以偵測單A 2〇8包括電晶體I ^及T5、缓衝器216及及閘㈤^)218之電路為例作 5兄明。電晶體T3之源極係接收高電壓位準㈣,閘極接收 接地位準’如此,使得電晶體T3恆為導通,以形成一連 接至咼電壓位準Vdd之路徑,來將節點NT2之電壓位準偏 壓至高電壓位準Vdd。電晶體T4及T5係為N型金氧半導 體電晶體’電晶體T5之雜接收接地位準,汲極係鱼電 晶體T4之源極輕接,閘極用以接收系統致能訊號脆、。電 晶體T4之汲極與電晶體T3之汲極耗接,以形成節點nt2, 閘極接收控制訊號%。電晶體Τ4及Τ5彼此串聯以形成— 接地路徑,來將節點NT2之電壓位準偏壓至接地位準,而 12 200821814Sanda number: TW3173PA 214 is used for output-bias current IB from the node to the ground level. The voltage at node m is determined by current signal 12 and bias current_. When the output voltage Vout* reaches a predetermined voltage level, the transistor (4) is turned off, and the current value of the current signal 12 is substantially zero. At this time, the voltage level of the node NT1 will be biased to a level close to the ground by the bias current Ιβ. When the output voltage reaches a predetermined voltage level, the transistor T2 is turned on for operation in the saturation region. At this time, the current value of the current signal i2 is greater than zero' to raise the voltage level of the node NT1 from the ground level to the voltage level close to the output voltage v〇ut, that is, the voltage level of the node NT1. Quasi-biased to a high voltage level. In the embodiment, the voltage of the node NT1 is used as the control signal sink, and is output to the unit 208. "Please refer to Figure 2C, the green diagram is the ping circuit diagram of the detection unit in Figure 2A. In this embodiment, the circuit for detecting the single A 2 〇 8 including the transistors I ^ and T5 , the buffer 216 , and the gate ( 5 ) 218 is taken as an example. The source of the transistor T3 receives the high voltage level (4), and the gate receives the ground level. Thus, the transistor T3 is always turned on to form a path connected to the 咼 voltage level Vdd to turn the voltage of the node NT2. The level is biased to a high voltage level Vdd. The transistors T4 and T5 are the impurity receiving grounding level of the N-type gold-oxygen semiconductor transistor 'Electrical crystal T5'. The source of the drain-type fish-electric crystal T4 is lightly connected, and the gate is used to receive the system-enabled signal fragile. The drain of the transistor T4 is drained from the drain of the transistor T3 to form the node nt2, and the gate receives the control signal %. The transistors Τ4 and Τ5 are connected in series to each other to form a ground path to bias the voltage level of the node NT2 to the ground level, and 12 200821814

. 三達編號:TW3173PA 此接地路徑係由控制訊號sc及系統致能訊號ENS來控制。 在本實施例中,系統致能訊號ENS及致能訊號EN,之 致能位準均為高電壓位準,而非致能位準均為低電壓位 準。當系統致能訊號ENS為非致能位準時,無論控制訊號 SC之位準為何,致能訊號ΕΝ’均被控制為非致能位準。 此時穩壓裝置200係為非致能。當系統致能訊號ens為致 能位準而控制訊號SC為高電壓位準時,系統致能訊號簡s / 與控制訊號SC將分別致能電晶體T4及T5,以將節點NT2 之電壓位準拉低至接地位準,使得節點NT2之電壓位準為 低電壓位準,進而使得致能訊號EN’為非致能位準。如 此,偵測單元208係可根據處於高電壓位準之控制訊號sc 來使致能訊號EN’為非致能位準,以經由時序訊號產生單 元202來非致能電荷泵204之操作。 當系統致能訊號ENS為致能位準而控制訊號sc為低 電壓位準時,控制訊號SC關閉電晶體T4,使得節點NT2 : 之電壓位準為高電壓位準,進而使得致能訊號EN,為致能 \ ' 位準。如此,偵測單元208係可根據處於低電壓位準之控 制訊號SC來使致能訊號EN 為致成位準,以經由時序訊 號產生單元202來致能電荷泵2〇4之操作。 時序訊號產生單元202例如為一般周知之時序訊號產 生電路,如第2D圖所示。時序訊號產生單元202係接收 致能訊號EN’ ,以經由反向器將電壓位準反向之特性輸出 時序訊號CLK,及反向時序訊號CLKB。而電荷泵204亦例 如為一般通知之電荷泵電路,如第2E圖所示。電荷泵204 13 200821814. Sanda Number: TW3173PA This ground path is controlled by the control signal sc and the system enable signal ENS. In this embodiment, the enable level of the system enable signal ENS and the enable signal EN are both high voltage levels, and the non-enable levels are low voltage levels. When the system enable signal ENS is non-enabled, the enable signal ΕΝ' is controlled to the non-enabled level regardless of the level of the control signal SC. At this time, the voltage stabilizing device 200 is disabled. When the system enables the signal ens to be the enable level and the control signal SC to the high voltage level, the system enable signal s / and the control signal SC will respectively enable the transistors T4 and T5 to set the voltage level of the node NT2. Pulling down to the ground level causes the voltage level of the node NT2 to be a low voltage level, thereby making the enable signal EN' a non-enabled level. Therefore, the detecting unit 208 can disable the enable signal EN' according to the control signal sc at a high voltage level to disable the operation of the charge pump 204 via the timing signal generating unit 202. When the system enable signal ENS is the enable level and the control signal sc is the low voltage level, the control signal SC turns off the transistor T4, so that the voltage level of the node NT2: is a high voltage level, thereby enabling the enable signal EN, To enable \ ' level. In this manner, the detecting unit 208 can cause the enable signal EN to be leveled according to the control signal SC at the low voltage level to enable the operation of the charge pump 2〇4 via the timing signal generating unit 202. The timing signal generating unit 202 is, for example, a well-known timing signal generating circuit as shown in Fig. 2D. The timing signal generating unit 202 receives the enable signal EN' to output the timing signal CLK and the reverse timing signal CLKB by the reverse voltage characteristic of the inverter. The charge pump 204 is also, for example, a generally notified charge pump circuit as shown in Figure 2E. Charge pump 204 13 200821814

• 三達編號:TW3173PA 係接收時序訊號CLK’ 、反向時序訊號CLKB及高電壓位準 Vdd,並受到時序訊號CLK’及反向時序訊號CLKB之控制 來產生輸出電壓V〇ut’ 。其中,高電壓位準vdd係例如為 電荷泵204之輸入電壓。 負載裝置210例如為快閃記憶體(ρ 1 ash)。輸出電壓 Vout’係用以輸入至作為快閃記憶體之資料線(Bit Line) ’來提供電壓將電子注入快閃記憶體記憶單元 , (Memory Cel 1)中電晶體之懸浮層(Fi〇ating Gate),來進 行貧料寫入;或提供電壓來將電子由懸浮層吸出,來進行 資料清除。 本實施例雖僅以電流訊號U及12之電流大小實質上 相同為例作說明,然,電流訊號u及12亦可為其他任意 比例。本實施例雖僅以電流映射單元2〇6a為包括兩個p =金氧半導體電晶體T1&T2之電流鏡為例作說明,然, 電流映射單元2〇6a並不侷限於本實施例之結構,而更可 4 為/、他开》式之電流鏡’例如為串疊組態(Cascode)電流 鏡’或為其他可輸出兩個電流值大小相關之電流訊號之電 路=構。本實施例雖僅以將致能訊號EN,輸入時序訊號產 生器202來間接地對電荷泵2〇4進行控制,然,本實施例 之^壓裝置200亦可選擇具有致能訊號接腳之電荷泵204 裝置,亚將致能訊號腿,直接地輸入電荷泵2〇4來對電荷 泵204之操作進行控制。 本貝施例之利用齊納二極體之穩壓單元及穩壓裝置 係根據輸出電壓來產生兩個電流值相關之電流訊號。本實 14 200821814 ^達編號:TW3173PA 施例之利用齊納二極體之穩壓單亓 中一電流訊號至齊納二極體,來對輪裝置係輪入其 轉換另一電流訊號為控制訊號, 免壓進行穩壓,並 A很據抑生卜 出電壓是否已達到預定之電壓值準。:刷訊號來判斷輸 二極體之穩壓單元更迴授控制訊號至带例之利用齊納 壓達到預定之電壓位準時非致能電荷^何泵,以於輸出電 之利用齊納二極體之穩壓單元係可如此,本實施例 $置無法在輸出電壓達到預定之電統穩壓 泵’而具有耗電量高及功率使用 丰寸關閉電荷 低耗電量及提高功率使用效率之優 =低之缺點’而具有降 另外’本實施例之利用齊納二極體之 二士糸利用齊納二極體與實質上為順向偏壓二及穩壓 、:饥主控端來將輸出電麼偏麼至預定 -虽體之 通之二極體之溫度係數為負數。,準,而順向導 更可鮮齊納二極體進戶 碩向導通之二極體 出訊競位準之影塑^又戈手'數之補償’以降低溫度對輪 體之穩屬罝- 每樣一來,本實施例之利用齊納二極 二極體之置係可有效地解決傳統利用齊約 點,而電㈣受到溫度影響而偏移之缺 再/、有輪出电壓位準較為穩定之優點。 袭置係施例之利用齊納二極體之穩虔單元及穩麗 鵪,搭西納二極體、電晶體及邏輯間之簡單電路結 果。如^ 、项授電路之應用來達到穩壓與控制電荷泵之效 装置倍!1,本實施例之利用齊納二極體之穩壓單元及穩壓 /、有放地改善傳統非利用齊納二極體之穩麗裝置 200821814• Sanda number: TW3173PA receives the timing signal CLK', the reverse timing signal CLKB and the high voltage level Vdd, and is controlled by the timing signal CLK' and the reverse timing signal CLKB to generate the output voltage V〇ut'. The high voltage level vdd is, for example, the input voltage of the charge pump 204. The load device 210 is, for example, a flash memory (ρ 1 ash). The output voltage Vout' is input to the data line (Bit Line) as a flash memory to supply voltage to inject electrons into the flash memory unit, and the suspension layer of the transistor in the (Memory Cel 1) Gate), to write poor materials; or provide voltage to draw electrons out of the suspension layer for data removal. In this embodiment, the current values of the current signals U and 12 are substantially the same as an example. However, the current signals u and 12 may be in any other ratio. In this embodiment, the current mapping unit 2〇6a is exemplified by a current mirror including two p=metal oxide semiconductor transistors T1 & T2. However, the current mapping unit 2〇6a is not limited to the embodiment. The structure, and more can be /, the other type of current mirror 'such as a cascade configuration (Cascode) current mirror ' or other circuit that can output two current value related to the current signal structure. In this embodiment, the charge pump 2〇4 is indirectly controlled by the input of the enable signal EN to the timing signal generator 202. However, the pressure device 200 of the embodiment may also select the enable signal pin. The charge pump 204 device, the sub-enable signal leg, is directly input to the charge pump 2〇4 to control the operation of the charge pump 204. The voltage stabilizing unit and the voltage stabilizing device using the Zener diode of the present embodiment generate two current signals related to the current value according to the output voltage.本实14 200821814 ^达编号: TW3173PA The example uses the Zener diode's voltage regulator unit to send a current signal to the Zener diode, and the wheel device is wheeled into another current signal as a control signal. , voltage-free voltage regulation, and A is very dependent on whether the voltage has reached the predetermined voltage value. : Brush the signal to judge the regulator unit of the input diode to feedback the control signal to the band. When the Zener voltage reaches the predetermined voltage level, the non-enable charge is used to pump the Zener diode. The voltage stabilizing unit of the body can be such that, in this embodiment, the output voltage can not reach the predetermined voltage regulator pump, and the power consumption is high, and the power usage is reduced, the charge is low, and the power consumption efficiency is improved. The advantage of the low = low has the other 'the second embodiment of the Zener diode using the Zener diode to utilize the Zener diode and the substantially forward bias and the voltage regulator: the hunger master The output voltage is biased to a predetermined value - although the temperature coefficient of the diode is negative. , Quasi, and the guide is more versatile Zener diode into the household master guide through the two poles to compete in the game of the shadow of the film ^ and Ge hand 'number of compensation' to reduce the temperature on the wheel body - In each case, the use of Zener diodes in this embodiment can effectively solve the traditional use of the singular points, while the electricity (4) is affected by the temperature and the offset is missing / / there is a wheel voltage level The advantage of being more stable. In the case of the attack system, the stable unit of the Zener diode and the stable 鹌 are used, and the simple circuit results between the Sinar diode, the transistor and the logic are taken. Such as ^, the application of the circuit to achieve voltage regulation and control of the charge pump effect device times! 1. The voltage stabilizing unit and the voltage regulator using the Zener diode of the present embodiment have improved the traditional non-utilizing Zener diodes. 200821814

• 三達編號:TW3173PA 電路複雜及成本較高之缺點,而具有電路結構簡單及成本 較為低廉之優點。 綜上所述,雖然本發明已以一較佳實施例揭露如上, 然其並非用以限定本發明。本發明所屬技術領域中具有通 常知識者,在不脫離本發明之精神和範圍内,當可作各種 之更動與潤飾。因此,本發明之保護範圍當視後附之申請 專利範圍所界定者為準。• Sanda number: TW3173PA has the disadvantages of complicated circuit and high cost, and has the advantages of simple circuit structure and low cost. In view of the above, the present invention has been disclosed in a preferred embodiment, and is not intended to limit the present invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

16 20082181416 200821814

• 三達編號:TW3173PA 【圖式簡單說明】 第1A圖繪示傳統之利用齊納二極體之穩壓裝置的電 路圖。 第1B圖繪示乃第1A圖中齊納二極體106的電流對電 壓曲線圖。 第1C圖繪示乃傳統之非利用齊納二極體之穩壓裝置 的電路圖。 第2A圖繪示依照本發明較佳實施例之利用齊納二極 f 1 體之穩壓裝置的一電路圖。 第2B圖繪示乃第2A圖中穩壓單元206的詳細電路圖。 第2C圖繪示乃第2A圖中偵測單元208的詳細電路圖。 第2D圖繪示乃第2C圖中控制訊號SC、系統致能訊號 ENS及致能訊號EN 之真值表。 第2E圖繪示乃第2A圖中時序訊號產生單元202的詳 細電路圖。 1 【主要元件符號說明】 100、200 :穩壓裝置 ΕΝ、EN’ :致能訊號 102、202 :時序訊號產生單元 CLK、CLK’ :時序訊號 104、204 :電荷泵• Sanda number: TW3173PA [Simple description of the diagram] Figure 1A shows the circuit diagram of a conventional voltage regulator using a Zener diode. Fig. 1B is a graph showing the current versus voltage of the Zener diode 106 in Fig. 1A. Figure 1C shows a circuit diagram of a conventional voltage regulator that does not utilize a Zener diode. 2A is a circuit diagram of a voltage stabilizing device using a Zener diode f 1 body in accordance with a preferred embodiment of the present invention. FIG. 2B is a detailed circuit diagram of the voltage stabilizing unit 206 in FIG. 2A. FIG. 2C is a detailed circuit diagram of the detecting unit 208 in FIG. 2A. Figure 2D shows the truth table of the control signal SC, the system enable signal ENS and the enable signal EN in Figure 2C. Fig. 2E is a detailed circuit diagram of the timing signal generating unit 202 in Fig. 2A. 1 [Description of main component symbols] 100, 200: Voltage regulator ΕΝ, EN': Enable signal 102, 202: Timing signal generation unit CLK, CLK': Timing signal 104, 204: Charge pump

Vout、Vout’ :輸出電壓 106、206c :齊納二極體 17 200821814Vout, Vout': output voltage 106, 206c: Zener diode 17 200821814

三達編號:TW3173PASanda number: TW3173PA

Vzl :崩潰電壓 Iz :流經齊納二極體之電流 110、210 :負載裝置 206 ··穩壓單元 206a :電流映射單元 212a :電流主控端 212b :電流從屬端 II、12 :電流訊號 VB :固定電壓 206c ··偏壓單元 SC :控制訊號 208 :偵測單元 ENS :系統致能訊號 CLKB :反向時序訊號 ΤΙ、T2、T3、T4、T5 :電晶體 Vth :臨界電壓 214 ·電流源 NT1、NT2 :節點 IB :偏壓電流 Vdd :高電壓位準 216 :緩衝器 218 :及閘 18Vzl: breakdown voltage Iz: current flowing through the Zener diode 110, 210: load device 206 · voltage regulator unit 206a: current mapping unit 212a: current master terminal 212b: current slave terminal II, 12: current signal VB : Fixed voltage 206c · · Bias unit SC : Control signal 208 : Detection unit ENS : System enable signal CLKB : Reverse timing signal ΤΙ , T2 , T3 , T4 , T5 : Transistor Vth : Critical voltage 214 · Current source NT1, NT2: node IB: bias current Vdd: high voltage level 216: buffer 218: and gate 18

Claims (1)

200821814 三達編號:TW3173PA 十、申請專利範圍: 1· 一種穩壓單元,用以接收一電荷栗(Charge Pump) 輸出之一驅動電壓,並對該驅動電壓進行穩壓,該穩壓單 元包括: 一電流映射單元,包括:一電流主控端及一電流從屬 :¾¾ ’ ΰ亥笔&L映射早元用以接收该驅動電壓,並根據該驅動 電壓於該電流主控端及該電流從屬端分別產生一第一電 流訊號及一第二電流訊號; 一齊納一極體,該齊納二極體之負端耦接至該電流主 控端,正端接收一固定電壓,該齊納二極體接收該第一電 流訊號,並控制該驅動電壓之電壓位準實質上等於一預定 電壓位準,以對該驅動電壓進行穩壓;以及 一偏壓單元’用以接收該第二電流訊號,以根據該第 二電流訊號來判斷該驅動電壓之電壓位準是否達到該預 定電壓位準’並根據該第二電流訊號產生一控制訊號· 其中,該控制訊號迴授至該電荷泵,以控制該電U荷泵 產生該驅動電壓。 2·如申請專利範圍第1項所述之穩壓單元,其中該 控制訊號係輸入一價測單元,該偵測單元更接收一第一致 能訊號,以根據該第一致能訊號及該控制訊號產生一第二 致能訊號。 3.如申請專利範圍第2項所述之穩壓單元,i中該 第二致能訊號係輸入一時序訊號產生單元,該時序訊號產 生單元根據該第二致能訊號產生一時序訊號及—反向^ 19 200821814 - 三達編號:TW3173PA 序訊號。 4. 如申請專利範圍第3項所述之穩壓單元,其中該 電荷泵接收該時序訊號及該反向時序訊號,以根據該時序 訊號及該反向時序訊號產生該驅動電壓,該電荷泵並輸出 該驅動電壓。 5. 如申請專利範圍第1項所述之穩壓單元,其中該 電荷泵更接收一輸入電壓,並根據該輸入電壓來產生該驅 動電壓。 #":, ^ 6. —種穩壓裝置,包括: 一電荷泵(Charge Pump),用以輸出一驅動電壓; 一穩壓單元,包括: 一電流映射單元,包括:一電流主控端及一電流 從屬端,該電流映射單元用以接收該驅動電壓,並根據該 驅動電壓於該電流主控端及該電流從屬端分別產生一第 一電流訊號及一第二電流訊號; 一齊納二極體,該齊納二極體之負端耦接至該電 流主控端,正端接收一固定電壓,該齊納二極體接收該第 一電流訊號,並控制該驅動電壓之電壓位準實質上等於一 預定電壓位準,以對該驅動電壓進行穩壓;及 一偏壓單元,用以接收該第二電流訊號,並根據 該第二電流訊號來判斷該驅動電壓之電壓位準是否達到 該預定電壓位準,並根據該第二電流訊號產生一控制訊 號; 一偵測單元,用以接收該控制訊號,並根據該控制訊 20 200821814 - 三達編號:TW3173PA 號產生一第一致能訊號;以及 一時序訊號產生單元,接收該第一致能訊號,並根據 該第一致能訊號產生一時序訊號及一反向時序訊號; 其中,該時序訊號及該反向時序訊號係輸出至該電荷 泵,該電荷泵根據該時序訊號及該反向時序訊號產生該驅 動電壓。 7. 如申請專利範圍第6項所述之穩壓裝置,其中該 偵測單元更接收一第二致能訊號,該偵測單元係根據該第 〆 二致能訊號及該控制訊號產生該第一致能訊號。 8. 如申請專利範圍第7項所述之穩壓裝置,其中該 第二致能訊號係為一系統致能訊號,以致能該穩壓裝置進 行穩壓操作。 9. 如申請專利範圍第6項所述之穩壓裝置,其中該 電荷泵更接收一輸入電壓,該電荷栗係根據該輸入電壓、 該時序訊號及該反向時序訊號產生該驅動電壓。200821814 Sanda number: TW3173PA X. Patent application scope: 1. A voltage stabilizing unit for receiving a driving voltage of a charge pump output and regulating the driving voltage. The voltage stabilizing unit includes: a current mapping unit comprising: a current master and a current slave: 3⁄43⁄4 'ΰ海笔&L mapping early element for receiving the driving voltage, and according to the driving voltage at the current master and the current slave The terminal generates a first current signal and a second current signal respectively; a Zener diode, the negative terminal of the Zener diode is coupled to the current control terminal, and the positive terminal receives a fixed voltage, the Zener diode The pole body receives the first current signal, and controls the voltage level of the driving voltage to be substantially equal to a predetermined voltage level to regulate the driving voltage; and a biasing unit 'to receive the second current signal And determining, according to the second current signal, whether the voltage level of the driving voltage reaches the predetermined voltage level and generating a control signal according to the second current signal. Feedback signal to the charge pump to control the electrical charge pump generates the U drive voltage. 2. The voltage regulator unit of claim 1, wherein the control signal is input to a price measurement unit, and the detection unit further receives a first enable signal for the first enable signal and the The control signal generates a second enable signal. 3. The voltage-sensing unit of claim 2, wherein the second enable signal is input to a timing signal generating unit, and the timing signal generating unit generates a timing signal according to the second enabling signal and - Reverse ^ 19 200821814 - Sanda number: TW3173PA sequence signal. 4. The voltage stabilizing unit according to claim 3, wherein the charge pump receives the timing signal and the reverse timing signal to generate the driving voltage according to the timing signal and the reverse timing signal, the charge pump And output the driving voltage. 5. The voltage stabilizing unit of claim 1, wherein the charge pump further receives an input voltage and generates the driving voltage according to the input voltage. #":, ^ 6. A voltage regulator device, comprising: a charge pump (Charge Pump) for outputting a driving voltage; a voltage stabilizing unit comprising: a current mapping unit comprising: a current master And a current slave unit, wherein the current mapping unit is configured to receive the driving voltage, and generate a first current signal and a second current signal respectively according to the driving voltage at the current main control terminal and the current slave terminal; a pole body, a negative end of the Zener diode is coupled to the current main terminal, and a positive terminal receives a fixed voltage, the Zener diode receives the first current signal, and controls a voltage level of the driving voltage Is substantially equal to a predetermined voltage level to regulate the driving voltage; and a biasing unit for receiving the second current signal, and determining whether the voltage level of the driving voltage is based on the second current signal A predetermined voltage level is reached, and a control signal is generated according to the second current signal; a detecting unit is configured to receive the control signal, and according to the control signal 20 200821814 - Sanda number: TW3 The 173PA generates a first enable signal; and a timing signal generating unit receives the first enable signal and generates a timing signal and a reverse timing signal according to the first enable signal; wherein the timing signal and The reverse timing signal is output to the charge pump, and the charge pump generates the driving voltage according to the timing signal and the reverse timing signal. 7. The voltage regulator device of claim 6, wherein the detecting unit further receives a second enabling signal, the detecting unit generating the first according to the second enabling signal and the control signal Consistent signal. 8. The voltage regulator of claim 7, wherein the second enable signal is a system enable signal to enable the voltage regulator to perform a voltage stabilizing operation. 9. The voltage regulator of claim 6, wherein the charge pump further receives an input voltage, and the charge pump generates the driving voltage according to the input voltage, the timing signal, and the reverse timing signal. 21twenty one
TW95141418A 2006-11-08 2006-11-08 Voltage regulation unit with zener diode and voltage regulation device thereof TWI323405B (en)

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