-1305945 九、發明說明： 【發明所屬之技術領域】. 本發月係關於種雙鎮鼓結構的製作方法，特別是一 種整口各制裝程於同—則反應室進行之雙鑲後結構的 製作方法。 【先前技術】 目前，積體電路内的多重金屬内連線（则itiievd 如嶋職tS)製程是，嵌技術為主，其又可概分為單鑲 嵌(single damascene)製程及雙鑲嵌(duai damascene)製程， 由於雙賴製程可大幅減少2()-30%的製程步驟 ，而且又能 降低導線浦塞間的接觸電阻，並增進其可靠性，所以現 今大部f”的金屬β i%線(metal ^她麵⑽丨㈣大都是採用 雙鑲叙製程。此外，為降低金屬内連線的電阻值及寄生電 谷效應’以增快訊號的傳遞速度，現行之半導體製程大多 疋先在低介電值材料（1〇w_K)所構成之介電層中蝕刻出具 有溝渠(trench)與介層洞(viah〇le)的雙鑲嵌結構，再填入銅 金屬並平坦化，以完成金屬内連線的製作。因此就雙鑲嵌 製程而言’介電層中之雙鑲嵌結構的蝕刻步驟可視為是最 重要的關鍵技術之一。 在先前技術中，不論是溝渠優先(trench-first)、介層洞優 先(via-first)或部分介層洞優先(partial-via-first)等之雙鑲嵌: .1305945 結構的餘刻步驟均是利用乾式的電漿氣體做為蝕刻介電層 的工具’其蝕刻反應室（chamber)必須處於真空狀態，且蝕 刻反應室大多採用所謂的沉積模式（deposition mode)，亦即 在独刻反應室内壁會沉積有一層高分子聚合物，其目的在 於防止電衆氣體直接接觸钱刻反應室内壁而造成金屬污 染’同時此高分子聚合物層相對於當做钱刻遮罩的光阻圖 案具有較高的钱刻選擇比。然後，在完成第一階段的钱刻 反應後’例如介層洞的❹丨製程’接著就必減進行去除 光阻圖案的灰化(ashing)製程以及清洗的㈣，隨後才能再 利用其他的蚀刻遮罩來或光阻圖案來進行第二階段的仙 反應’例如溝渠的蝕刻製程。但由於所使用的光阻大部分 編物質’因此去除光阻圖案必須實施於其他的光阻剝 除機台（photoresist stripper) ’ 亦即蝕刻 (venting)，“取出半導體晶圓並傳送至光阻剝二台中了 • 則反應室中並抽真 空，以進行下-階段的钱刻步驟。因為倘若於蚀刻反應室 中直接以氧氣電漿去除光阻，將會連同餘刻反應室内壁所 沉積的高分子聚合物層一併去除。 此外，同-姓刻反應室往往需要進行不同參數的錄刻 製程，然而，在切換不同階段之餘刻製程時，後一製程之 環境往往會受到前-製程之影響，此印所謂記憶效應 (memory effect)，此雜刻反應室内氣體不穩定的狀況往往 1305945 造成後-製程製造出之雙触結構品f不佳，進而影響半 導體元件的财度’因此’上述雙鑲嵌結構的關步驟和 去除光阻的步驟必須在不同的機台分別進行，而無法在同 一個製程反應室中完成。簡而言之’先前技術製作雙镶散 結構時，半導體晶圓必須經過破真空、不同機台間傳送、 ^真空以及機械手臂傳過程，若再加待機的時間，非 常不符合時間成本的效益，而且多段式的整合步驟也 響製程良率。 【發明内容】 據此’本發明之-目的在於提供—種雙鑲錄構的製 作方去，降低半導體元件的生產成本，並改善習知技術無 法克服之難題。 …、 一本發明係揭露一種雙鑲嵌結構的製作方法，應用於一 半導體晶圓，該半導體晶圓依序包含—基底、—導電層、 具有-介層洞之介電層、義有—溝渠圖案之硬遮:層 以及一犧牲層覆蓋該硬遮罩層與該介電層並填滿該介層 洞’該雙鑲嵌結構的製作方法係在同—㈣反應室内進行 至少以下二個連續步驟。首先，進行—第一蝕刻製程，通 入以氧氣為主之電漿氣體，蝕刻部分該犠牲層，以曝露出 該硬遮罩層、該介電層以及部分之該介層洞，然後進行一 第—蝕刻製程’通入以四氟化碳為主之電漿氣體，蝕刻部 训5945 刀該"層洞以擴大形成 程，通入以氧氣為主之μ Λ 者進行—第三餘刻製 犧牲層，使哕人思、 浆軋體以去除該介層洞中剩餘的 便該，1層洞曝露該導電層。 本發明另揭露一種整人 基底 製作方法，Q九阻灰化與蝕刻雙鑲嵌結構的 4:Γ半導體晶圓，該半導體晶圓依序包含 之介電層、-定義有—溝準 =-具有-介層洞與-溝渠 填充於該介層洞，該=案之硬遮罩層以及—光阻層 完成下列步驟。首"法係在同一蝕刻反應室中連續 主之電_去除該====== 入以四氟化碳為主料*仃侧製程，通 曝露該導電層γ漿氣體，蝕刻該保護層使該介層洞 芦H ,丨、-触結構的製作方法係關—條刻反應室内連 耐Γ ^一個連續的餘刻步驟，可大幅提高晶圓的生產效率； :U之製作方法在操作上可僅進行賴二個至四個的姓刻 f驟目而具有馬機動性、高配合度之優勢，更加提高生產線機 器運作的靈活度。 【實施方式】 為了使突顯本發明之優點及特徵，下文列舉本發明之 一較佳實施例，並配合圖示作詳細說明如下； -1305945 第1圖至第5圖為本發明之一較佳實施例。如第1圖 所示’首先提供一半導體晶圓1〇，其包含有一基底12、一 導電層14、一保護層（cap iayer)16、一具有一介層洞（via hole)24之介電層（dielectric layer) 18、一定義有一溝渠圖案 26之硬遮罩層（hard mask)20以及一犠牲層22覆蓋於硬遮 罩層20與介電層18並填滿介層洞24。於本較佳實施例中， 導電層14係為一金屬導電層，通常是由銅所構成之金屬導 電層’而保護層16與硬遮罩層20可由氮矽化合物（silic〇n nitride)、碳化矽（SiC)或氮氧化矽（silicon oxy_nitride)所構 成，又介電層18則包含低介電值材料，例如含氟二氧化石夕 (fluorinated silica glass)或有機矽玻璃（organosilicate)，至於 犠牲層22,本較佳實施例則是以光阻(photoresist)做為其主 要材質。 接著如第2圖所示，將半導體晶圓1〇置於一蚀刻反應 室内之一晶圓夾盤（chuck ’圖未示）上，且該餘刻反應室之 内壁塗有三氧化二釔(Y2〇3)等之塗層，進行一第一蝕刻製 程。該第一蝕刻製程包含： 步驟1.1 :通入氣壓介於20-100毫托耳(mT)，上、下電極 功率分別介於300-1500瓦（W)及300-1500瓦之 間，且氣體流量介於100-500每分鐘標準毫升 (standard cubic centimeter per minute, seem) • 1305945 之以氧氣（〇2)為主的電漿氣體；其較佳之氣壓 值、上下電極功率與氣體流量分別為30mT、 500/400W以及300sccm，以進行大範圍的蝕刻。 同時，該第一蝕刻製程可視製程需要，選擇性地加入步驟 1.2。 步驟1.2 :通入含氮氣(N2)與氧氣為主的電漿氣體，其氣 壓大小約介於20-100mT，上、下電極功率分別 ® 介於100-1000W及100- 1000W之間，且氮氣 和氧氣的流量分別介於l〇〇-300sccm和 10-30sccm之間，且氮氣與氧氣的流量比約為 10比1 ;又較佳之氣壓值、上下電極功率與氣 氣/氧氣之氣體流量分別為20mT' 1000/100W 以及200/20sccm，以進行較細微的餘刻。 第一蝕刻製程蝕刻犠牲層22至一預定深度，以曝露硬遮罩 • 層20、溝渠圖案26以及部分的介電層18,且介層洞24中 仍殘留部分的犠牲層22，以進行之後的溝渠蝕刻製程。 然後如第3圖所示，在同一蝕刻反應室進行一第二蝕 刻製程，通入以四氟化碳(CF4)為主之混合電漿氣體，且可 添加八I環丁烧(C4F8)、氬氣(Ar)或氧氣，以增加去除钱刻 過程中所產生之高分子聚合物的能力。由於硬遮罩20、犠 * 牲層22與介電層18的蝕刻選擇比，該混合電漿氣體將透 - 過硬遮罩20所定義之溝渠圖案26蝕刻介電層18，以擴大 1305945 形成一溝渠28，而部分的犧牲層22亦會於此第二蝕刻製 程中被蝕刻，僅留下填入介層洞24的部分犠牲層22，以 保護介層洞24底部的保護層16。於本實施例中該第二蝕 刻製程所通入之混合電漿氣體，其氣壓值係介於30-150 mT，蝕刻時的上、下電極功率分別介於150-1500 W及 150-1500W之間，且各氣體流量比（C4F8/CF4/Ar/02)約為 5-30/100-200/100-200/5-20sccm;而較佳之氣壓值、上下電 極功率與各氣體流量（C4F8/CF4/Ar/02)分別為60mT、 1200/150W 以及 10/112/150/6 seem。 如第4圖所示’在溝渠28形成後，又於同一钱刻反應 室直接進行一第三#刻製程，通入以氧氣為主的電漿氣 體’去除介層洞24内的犠牲層22，其氣壓值係介於20-50 ，韻刻時的上、下電極功率分別介於0-1500W及 鲁 〇]5〇OW之間，且氣體流量介於500-1000sccm間，其中該 第三蝕刻製程又可包含步驟3.1與步驟3.2，而且步驟3」 的操作可視時間調配或晶圓狀況而加入。 步驟3.1 :通入以氧氣為主的電漿氣體’其較佳氣壓值、 上下電極功率與氧氣流量分別為20 mT、500/0 W以及750 seem ’可有效降低蝕刻時所造成的 記憶效應。 步驟3.2 :再次通入以氧氣為主的電漿氣體，其較佳氣壓 值、上下電極功率與氧氣流量分別為2〇 mT、 -1305945 500/200 W以及300 seem，以去除介層洞24内 的犠牲層22。 由於本實施例中所採用的犠牲層22為光阻，因此第三蝕刻 製程可視為一光阻灰化製程(ashing)。 最後’如第5圖所示，接續前述之蝕刻製程，仍於同 一蝕刻反應室進行一第四蝕刻製程，用以蝕刻開介層洞24 鲁底部的保護層16，其包含： 步驟4.1:通入以四氟化碳為主的電漿氣體以蝕刻保護層 16，其氣壓值係介於20-100 mT，蝕刻時的上、 下電極功率分別介於150-1000W及150-1000W 之間，且氣體流量介於100-500sccm間，而較 佳之氣壓值、上下電極功率與氣體流量分別為 50 mT、600/150 W 以及 140 seem。 Φ 在姓刻反應完成後，考量姓刻反應室内的氣體殘存量與姓 刻反應室的穩定性，可視需要再加入以下步驟： 步驟4.2 :通入以氮氣為主的電漿氣體，其氣壓值係介於 20-100 mT，蝕刻時的上、下電極功率分別介於 0-500W及0-500W之間，且氣體流量介於 100-500 seem間；而較佳之氣壓值、上下電極 功率與氣體流量分別為60 mT、400/0 W以及 ' 260 seem，主要目的為讓殘留在蝕刻反應室内 " 的副產物軟化，以便於後續製程清除。 -1305945 步驟4上if入以氮氣為主的電漿氣體，其氣愿值係介於 HMOOmT，且氣體流量介於1〇〇 5〇〇sccm間； 而較佳之氣壓值與氣體流量分別為1〇mT以及 260 seem，主要目的為清除殘留在蝕刻反應室 的副產物。-1305945 IX. Description of the invention: [Technical field to which the invention belongs] This publication is about the production method of the double-town drum structure, in particular, a double-inlaid structure in which the entire process is carried out in the same chamber. Production method. [Prior Art] At present, the process of multi-metal interconnects in the integrated circuit (the itiievd, such as the t-sports tS) process is mainly embedded technology, which can be divided into single damascene process and dual damascene (duai). Damascene) process, because the double-dip process can greatly reduce the process steps of 2 ()-30%, and can reduce the contact resistance between the plugs and improve the reliability, so most of the current f" metal β i% The wire (metal ^ her face (10) 丨 (four) mostly adopts the dual inlay process. In addition, in order to reduce the resistance value of the metal interconnect and the parasitic electric valley effect to increase the transmission speed of the signal, the current semiconductor process is mostly in the first place. A double damascene structure having a trench and a via hole is etched into the dielectric layer formed of the low dielectric material (1〇w_K), and then filled with copper metal and planarized to complete the metal The fabrication of interconnects. Therefore, in the case of dual damascene processes, the etching step of the dual damascene structure in the dielectric layer can be regarded as one of the most important key technologies. In the prior art, whether it is trench-first , via-first or Partially-via-first dual-inlaying: The remaining steps of the .1305945 structure are the use of dry plasma gas as a tool for etching the dielectric layer. The etching chamber must be in place. In the vacuum state, and the etching reaction chamber mostly adopts a so-called deposition mode, that is, a polymer layer is deposited on the inner wall of the reaction chamber, and the purpose is to prevent the electric gas from directly contacting the inner wall of the reaction chamber. Causes metal contamination 'At the same time, this polymer layer has a higher cost-selective ratio than the photoresist pattern used as a money mask. Then, after completing the first stage of the money-etching reaction, 'for example, the layer of the hole The 丨 process' will then reduce the ashing process for removing the photoresist pattern and the cleaning (4), and then use other etch masks or photoresist patterns to perform the second stage of the reaction. Etching process. However, most of the photoresist is used because of the photoresist used. Therefore, the photoresist pattern must be removed from other photoresist stripper's. Venting, "Remove the semiconductor wafer and transfer it to the photoresist stripping station." • The chamber is evacuated to perform the next-stage credit step because if the plasma is directly treated in the etching chamber The removal of the photoresist will be removed together with the polymer layer deposited on the inner wall of the reaction chamber. In addition, the same-named reaction chamber often requires a different parameter recording process, however, in the different stages of switching In the process of engraving, the environment of the latter process is often affected by the pre-process. The so-called memory effect, the gas instability in the reaction chamber is often 1305945, resulting in a two-touch structure created by the post-process. The product f is not good, which in turn affects the financial value of the semiconductor component. Therefore, the steps of the double damascene structure and the step of removing the photoresist must be performed separately on different machines, and cannot be completed in the same process chamber. In short, when the prior art made double-insert structure, the semiconductor wafer must undergo vacuum breaking, transfer between different machines, vacuum and mechanical arm transfer. If the standby time is added, it is very inconsistent with the cost of time. And the multi-stage integration step also sounds the process yield. SUMMARY OF THE INVENTION According to the present invention, it is an object of the present invention to provide a dual-inlay recording process, which reduces the production cost of a semiconductor component and improves the problem that the conventional technique cannot overcome. The invention discloses a method for fabricating a dual damascene structure, which is applied to a semiconductor wafer, which comprises a substrate, a conductive layer, a dielectric layer having a via, and a well-drain. a hard mask of the pattern: a layer and a sacrificial layer covering the hard mask layer and the dielectric layer and filling the via hole. The dual damascene structure is fabricated in the same- (four) reaction chamber for at least two consecutive steps . First, performing a first etching process, introducing an oxygen-based plasma gas, etching a portion of the layer to expose the hard mask layer, the dielectric layer, and a portion of the via hole, and then performing a The first-etching process passes into the plasma gas mainly composed of carbon tetrafluoride, and the etching section trains 5945 knives. The layer hole is used to expand the formation process, and the oxygen-based μ 通 is used for the third time. The sacrificial layer is formed so that the layer is exposed to remove the remaining portion of the via hole, and the layer is exposed to the layer. The invention further discloses a method for fabricating a whole human substrate, a Q:9 ashing and etching double-inlaid structure of a 4: germanium semiconductor wafer, the semiconductor wafer sequentially comprising a dielectric layer, - defining a groove = - The via hole and the trench are filled in the via hole, and the hard mask layer of the case and the photoresist layer complete the following steps. The first " method is continuous in the same etching reaction chamber. _Remove the ====== into the carbon tetrafluoride-based material*仃 side process, expose the conductive layer γ slurry gas, etch the protection The layer enables the fabrication method of the interlayer hole H, 丨, and --contact structure to be related to the internal resistance of the intercalation reaction chamber. A continuous residual step can greatly improve the production efficiency of the wafer; In operation, only two to four surnames can be used to achieve the advantages of horse maneuverability and high compatibility, and the flexibility of the operation of the production line machine can be further improved. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to highlight the advantages and features of the present invention, a preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings; -1305945 Figs. 1 to 5 are a preferred embodiment of the present invention. Example. As shown in FIG. 1 , a semiconductor wafer 1 is first provided, which comprises a substrate 12 , a conductive layer 14 , a cap iayer 16 , and a dielectric layer having a via hole 24 . A dielectric mask 18, a hard mask 20 defining a trench pattern 26, and a layer 22 are overlying the hard mask layer 20 and the dielectric layer 18 and fill the vias 24. In the preferred embodiment, the conductive layer 14 is a metal conductive layer, usually a metal conductive layer made of copper, and the protective layer 16 and the hard mask layer 20 may be made of a silicon nitride compound. SiC or silicon oxy_nitride, and the dielectric layer 18 comprises a low dielectric material such as fluorinated silica glass or organosilicate. In the preferred embodiment, the photoresist is used as the main material. Next, as shown in FIG. 2, the semiconductor wafer 1 is placed on a wafer chuck (not shown) in an etching reaction chamber, and the inner wall of the residual reaction chamber is coated with antimony trioxide (Y2). 〇 3) and the like, a first etching process is performed. The first etching process comprises: Step 1.1: the inlet air pressure is between 20-100 mTorr (mT), and the upper and lower electrode powers are respectively between 300-1500 watts (W) and 300-1500 watts, and the gas The flow rate is between 100-500 standard milli centmeter per minute (the standard) • 1305945 is the oxygen gas (〇2)-based plasma gas; its preferred gas pressure value, upper and lower electrode power and gas flow rate are 30mT respectively. , 500/400W and 300sccm for a wide range of etching. At the same time, the first etching process can be selectively added to step 1.2 as needed for the process. Step 1.2: Passing a plasma gas containing nitrogen (N2) and oxygen, the gas pressure is about 20-100 mT, and the upper and lower electrode powers are respectively between 100-1000 W and 100-1000 W, and nitrogen gas. The flow rate of oxygen and oxygen is between l〇〇-300sccm and 10-30sccm, respectively, and the flow ratio of nitrogen to oxygen is about 10:1; and the preferred gas pressure value, upper and lower electrode power and gas/oxygen gas flow rate respectively It is 20mT' 1000/100W and 200/20sccm for a finer moment. The first etch process etches the layer 22 to a predetermined depth to expose the hard mask layer 20, the trench pattern 26, and a portion of the dielectric layer 18, and a portion of the layer 22 remains in the via hole 24 for subsequent Ditch etching process. Then, as shown in FIG. 3, a second etching process is performed in the same etching reaction chamber, and a mixed plasma gas mainly composed of carbon tetrafluoride (CF4) is introduced, and an eight-ring firing (C4F8) can be added. Argon (Ar) or oxygen to increase the ability to remove high molecular weight polymers produced during the engraving process. Due to the etching selectivity ratio of the hard mask 20, the 犠* layer 22 and the dielectric layer 18, the mixed plasma gas etches the dielectric layer 18 through the trench pattern 26 defined by the hard mask 20 to expand 1305945 to form a The trenches 28, and a portion of the sacrificial layer 22, are also etched during this second etch process, leaving only a portion of the sacrificial layer 22 that fills the vias 24 to protect the protective layer 16 at the bottom of the vias 24. In the present embodiment, the mixed plasma gas introduced in the second etching process has a gas pressure value of 30-150 mT, and the upper and lower electrode powers during etching are 150-1500 W and 150-1500 W, respectively. And the gas flow ratio (C4F8/CF4/Ar/02) is about 5-30/100-200/100-200/5-20sccm; and the preferred gas pressure value, upper and lower electrode power and each gas flow rate (C4F8/ CF4/Ar/02) are 60mT, 1200/150W and 10/112/150/6 seem respectively. As shown in Fig. 4, after the ditch 28 is formed, a third process is directly performed in the same chamber, and the oxygen-based plasma gas is introduced to remove the layer 22 in the via hole 24. The gas pressure value is between 20-50, and the upper and lower electrode powers are between 0-1500W and reckless]5〇OW, respectively, and the gas flow rate is between 500-1000sccm, wherein the third The etching process may in turn comprise steps 3.1 and 3.2, and the operation of step 3" may be added depending on the time blending or wafer condition. Step 3.1: Passing oxygen-based plasma gas's preferred gas pressure, upper and lower electrode power and oxygen flow rate of 20 mT, 500/0 W and 750 seem' respectively can effectively reduce the memory effect caused by etching. Step 3.2: Re-introducing oxygen-based plasma gas, the preferred gas pressure value, upper and lower electrode power and oxygen flow rate are 2〇mT, -1305945 500/200 W and 300 seem, respectively, to remove the interlayer hole 24 The layer of obscenity 22. Since the layer 22 used in the embodiment is a photoresist, the third etching process can be regarded as a photoresist ashing process. Finally, as shown in FIG. 5, following the etching process described above, a fourth etching process is performed in the same etching reaction chamber to etch the protective layer 16 at the bottom of the via hole 24, which includes: Step 4.1: Pass A plasma gas mainly composed of carbon tetrafluoride is used to etch the protective layer 16 with a gas pressure value of 20-100 mT, and the upper and lower electrode powers during etching are between 150-1000 W and 150-1000 W, respectively. The gas flow rate is between 100 and 500 sccm, and the preferred gas pressure value, upper and lower electrode power and gas flow rate are 50 mT, 600/150 W and 140 seem, respectively. Φ After the completion of the reaction of the surname, consider the residual gas in the reaction chamber and the stability of the reaction chamber. If necessary, add the following steps: Step 4.2: Pass the plasma gas with nitrogen as the main gas pressure. The system is between 20-100 mT, and the upper and lower electrodes are etched between 0-500W and 0-500W, respectively, and the gas flow rate is between 100-500 seem; and the preferred gas pressure value, upper and lower electrode power and The gas flows are 60 mT, 400/0 W and '260 seem, respectively, and the main purpose is to soften the by-products remaining in the etching chamber to facilitate subsequent process removal. -1305945 Step 4: If the nitrogen gas is the main plasma gas, the gas value is between HMOOmT and the gas flow rate is between 1〇〇5〇〇sccm; and the preferred gas pressure value and gas flow rate are 1 respectively. 〇mT and 260 seem, the main purpose is to remove by-products remaining in the etching reaction chamber.
4 4.4 ·通人以氬氣為主的錢氣體，其氣壓值係介於 20-50mT’且氣體流量介於 5G(M5〇〇sccm4 4.4 · The gas of argon-based gas, the pressure value is between 20-50mT' and the gas flow is between 5G (M5〇〇sccm)
間；而較佳之氣壓值與氣體流量分別為20 mT 與l_SCCm'主要㈣為再進_步清除殘留在 餘刻反應室的副產物。 餘刻製程後，半導體晶圓1。的介層洞24便可直 曝路導電層Μ ’以完成雙職結構的勉刻製程，又步驟 殘留ΓΓ/·3以及步驟4.4的操作可錢㈣反應室内的 、體與水氣，且可依清除狀況選擇步驟、步驟4.3 s步驟4.4以達成清潔蝕刻反應室的目的。 土於本發明之精神，本發明並不限於上述較佳實施 在同—制反應室内連續進行第—_製程、第二 於:^程、第三蝕刻製程以及第四蝕刻製輕，本發明亦可 =—_反應室中，僅進行任二個連續之雙誠結構的 步驟。如本發明所揭露之另一較佳實施例：首先提供 半導體晶圓，該半導體晶圓依序包含一基底、、 —保護;a、__、生、e 入a g 曰—溝渠、一"層洞以及一光阻層填滿該介層洞； 1305945 接著在同一蝕刻反應室内連續進行前述之第一蝕刻製程與 第二蝕刻製程，然後於另一蝕刻反應室中進行第三蝕刻製 程灰化該光阻層後，再原位（in-situ)進行第四#刻製程來姓 刻該保護層，使該介層洞可直接曝露該導電層，完成雙鑲 嵌結構的蝕刻製程。或者是在同一蝕刻反應室内連續進行 第一蝕刻製程、第二蝕刻製程及第三蝕刻製程之後，再移 至另一蝕刻反應室中進行第四蝕刻製程。是以本發明之方 ® 法具有高度之整合性、靈活度及應變性，可有效依據生產 線上之各半導體製程機台的狀況與產品類別來做適當調 整，以提高產能(throughput)。 此外，本發明之精神亦適用於不具保護層的雙鑲嵌結 構製程，請參考第6圖至第8圖，第6圖至第8圖為本發 明於不具保護層之半導體晶圓製作雙鑲嵌結構之方法示意 ❿ 圖。第6圖係提供一半導體晶圓30，其包含有一基底32、 一導電層34、具有一介層洞42之介電層36、一定義有一 溝渠圖案44之硬遮罩層38以及一光阻層40覆蓋硬遮罩層 38與介電層36並填滿介層洞42。接著如第7圖所示，依 序進行第一蝕刻製程及第二蝕刻製程，蝕刻介電層36及部 分介層洞42以擴大形成一溝渠46。最後如第8圖所示， 再經第三蝕刻製程灰化光阻層40，使介層洞42直接曝露 ' 導電層34，因而完成雙鑲嵌結構的蝕刻製程。 如前述各實施例，完成蝕刻製程的雙鑲嵌結構可再經 .1305945 由化學氣相沉積（chemical vapor deposition，CVD)、物理氣 相沈積(physical vapor deposition, PVD)或電鍵等方式選擇 性依序填入一阻障層（barrier layer)、一晶種層（seed layer) 以及一金屬導電層，例如銅、銘、鎮、金或銘等，並進行 一化學機械研磨（chemical mechanical polishing, CMP)製 程，便可同時完成金屬導線以及導電插塞的製作。 • 由於本發明所揭示之雙鑲嵌結構的製作方法係為一清 淨模式(clean mode)之製作方法，此方法中的特定試劑配方 (recipe)，可保持反應室中的潔淨，減少傳統沉積模式中製 程不穩定，此外’在半導體晶圓移出蝕刻反應室後，本發 明可再選擇性地進行一蝕刻反應室的清潔製程，以去除製 作雙鑲嵌結構過程中殘留在該蝕刻反應室内之副產物，以 降低記憶效應的產生’且因姓刻反應室内壁塗有三氧化二 • 釔塗層’能有效保護蝕刻反應室内壁不受電漿氣體侵姓， 所以完成本發明之清淨模式（clean mode)之雙鑲嵌结構的 製程後，再進行蝕刻反應室的清潔製程時，蝕刻反應室内 的下電極無須晶圓保護，故於清潔時不會有死角而更可徹 底清潔蝕刻反應室’因而可之稱為一無晶圓乾式清潔 (waferless dry clean)製程。本發明之無晶圓乾式清潔製程的 進行步驟如下： 第一清潔步驟：通入面功率之含氧氣的清潔電漿氣體做 清除的動作，該動作之清除程度可以終點 .1305945 偵測（end point detection)做確認，其氣壓 值係介於20-30mT，上、下電極功率分別 介於 1000-2000 W 及 1000-2000 W 之 間，且氣體流量介於500-1000sccm間； 而較佳之氣壓值、上下電極功率與氣體 流量分別為200 mT、2000/1500 W以及 600 seem。 • 第二清潔步驟：再次通入高功率之含氧氣的清潔電漿氣 體進一步進行時間模式（time mode)的清 潔步驟，該時間模式為設定一固定時間 以執行第二清潔步驟，以確保該蝕刻反 • ' . · _ 應室的完全潔淨，其較佳之氣壓值、上 下電極功率與氣體流量分別為200 mT、 2000/1500 W 以及 600 seem。 φ 接下來對蝕刻反應室内部不同區段進行以下的清潔步驟’ 使蝕刻反應室的狀態更加穩定。 第三清潔步驟：通入一相對低壓、高流量之含氧氣清潔 電漿氣體去除蝕刻反應室内殘留的氣 體，其較佳之氣壓值、上下電極功率與 氣體流量分別為40 mT、2000/1500 W以 及 1200 seem。 ' 第四清潔步驟：通入未施予外加電壓之含鈍氣之清潔電 • 漿氣體去除蝕刻反應室内殘留的氣體， 1305945 其較佳之氣體為氬氣，其氣壓值係介於 20-30mT，且氣體流量介於500-1000sccm 間；而較佳之氣壓值與氣體流量分別為 25 mT 以及 800 seem。 第五清潔步驟：通入含四氟化碳、氧氣與氬氣之混合清 潔電漿氣體’以保持蝕刻反應室處於穩 定的狀態，其氣壓值係介於30-100mT， 且氣體流量比（CF4/〇2/Ar)為100-150/ 0-20/ 100-200 ;而較佳之氣壓值、上下電 極功率與各氣體流量（CF4/〇2/Ar)分別為 60 mT、800/150 W 以及 140/10/150 seem。 值得注意的是’該無晶圓乾式清潔製程之實施，可介於各 半導體晶圓進行雙鎮嵌結構的蝕刻步驟間、每批次(l〇t)半 導體晶圓蝕刻製程間或任一蝕刻製程間。 如上所述，本發明係揭露一雙鑲嵌結構的製作方法， 其蝕刻製程與光阻灰化製程係於同一蝕刻反應室内進行， 可大幅減少機台轉換間所耗費的速輸時間，且由光阻所構 成的犠牲層在多次的餘刻製程巾，可確保半導體晶圓底層 的導電層免於多次餘刻製程可能it成的似'!損害；同時， 生製作方法可單獨進行任二個速續的钱刻步驟，以配合 長以、周配，且適時配合無晶®乾式清潔製程，更可增 開啓敍刻反應室清潔的乎均清潔時間（mean time 1305945 between clean)，大幅提高半導體晶.圓的製作效率。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第5圖為本發明之一較佳實施例以製作雙鑲嵌妗 構之示意圖。 第6圖至第8圖為本發明於不具保護層之半導體晶圓製作 雙鑲嵌結構之流程示意圖。 【主要元件符號說明】 10 半導體晶圓 12 基底 14 導電層 16 保護層 18 介電層 20 硬遮罩層 22 犠牲層 24 介層洞 26 溝渠圖案 28 溝渠 30 半導體晶圓 32 基底 34 導電層 36 介電層 38 硬遮罩層 40 光阻 42 介層洞 44 溝渠圖案 46 溝渠The preferred gas pressure value and gas flow rate are 20 mT and l_SCCm', respectively (four) is the re-entry step to remove the by-products remaining in the reaction chamber. After the engraving process, the semiconductor wafer 1 is used. The via hole 24 can directly expose the conductive layer Μ 'to complete the engraving process of the dual-sector structure, and the residual ΓΓ/·3 and the operation of step 4.4 can be used to (4) the reaction chamber, body and moisture, and According to the cleaning condition selection step, step 4.3 s step 4.4 is used to achieve the purpose of cleaning the etching reaction chamber. In the spirit of the present invention, the present invention is not limited to the above preferred embodiment in the same reaction chamber continuously performing the first process, the second process, the third etching process, and the fourth etching process, and the present invention is also In the reaction chamber, only the steps of any two consecutive double-homed structures can be performed. According to another preferred embodiment of the present invention, a semiconductor wafer is first provided, the semiconductor wafer sequentially includes a substrate, a protection, a, __, raw, e into an ag曰-ditch, a "layer a hole and a photoresist layer fill the via hole; 1305945, then performing the first etching process and the second etching process continuously in the same etching reaction chamber, and then performing a third etching process ashing in another etching reaction chamber. After the photoresist layer, the fourth inscription process is performed in-situ to name the protective layer, so that the via hole can directly expose the conductive layer to complete the etching process of the dual damascene structure. Alternatively, after the first etching process, the second etching process, and the third etching process are continuously performed in the same etching reaction chamber, the fourth etching process is performed by moving to another etching reaction chamber. The method of the present invention is highly integrated, flexible, and adaptable, and can be appropriately adjusted according to the condition and product category of each semiconductor processing machine on the production line to improve throughput. In addition, the spirit of the present invention is also applicable to a dual damascene structure process without a protective layer. Please refer to FIG. 6 to FIG. 8 , and FIGS. 6 to 8 illustrate a dual damascene structure for a semiconductor wafer without a protective layer. The method is shown in the figure. 6 is a semiconductor wafer 30 including a substrate 32, a conductive layer 34, a dielectric layer 36 having a via 42 , a hard mask layer 38 defining a trench pattern 44, and a photoresist layer. 40 covers the hard mask layer 38 and the dielectric layer 36 and fills the via hole 42. Next, as shown in FIG. 7, the first etching process and the second etching process are sequentially performed, and the dielectric layer 36 and the partial via holes 42 are etched to form a trench 46. Finally, as shown in FIG. 8, the photoresist layer 40 is ashed by a third etching process, so that the via hole 42 is directly exposed to the conductive layer 34, thereby completing the etching process of the dual damascene structure. According to the foregoing embodiments, the dual damascene structure completing the etching process can be selectively ordered by chemical vapor deposition (CVD), physical vapor deposition (PVD) or electric bonds. Filling a barrier layer, a seed layer, and a metal conductive layer, such as copper, Ming, Zhen, Jin, or Ming, and performing a chemical mechanical polishing (CMP) The process can complete the fabrication of metal wires and conductive plugs at the same time. • Since the dual damascene structure disclosed in the present invention is fabricated in a clean mode, the specific reagent recipe in the method can keep the reaction chamber clean and reduce the traditional deposition mode. The process is unstable, and in addition, after the semiconductor wafer is removed from the etching reaction chamber, the present invention can selectively perform an etching process of the etching reaction chamber to remove by-products remaining in the etching reaction chamber during the process of fabricating the dual damascene structure. In order to reduce the generation of the memory effect and the interior wall of the reaction chamber is coated with the antimony trioxide coating, the inner wall of the etching reaction can effectively protect the interior wall of the etching reaction from the plasma gas, thus completing the clean mode of the present invention. After the process of the damascene structure, when the etching process of the etching reaction chamber is performed, the lower electrode in the etching reaction chamber does not need wafer protection, so that there is no dead angle during cleaning and the etching reaction chamber can be thoroughly cleaned, so that it can be called a Waferless dry clean process. The steps of the waferless dry cleaning process of the present invention are as follows: The first cleaning step: the action of removing the oxygen-containing clean plasma gas of the surface power, the clearance of the action can be the end point. 1305945 detection (end point Detection) to confirm that the pressure value is between 20-30mT, the upper and lower electrode powers are between 1000-2000 W and 1000-2000 W, respectively, and the gas flow rate is between 500-1000 sccm; and the preferred air pressure value The upper and lower electrode power and gas flow rates are 200 mT, 2000/1500 W, and 600 seem, respectively. • Second cleaning step: re-passing the high-power oxygen-containing cleaning plasma gas to further perform a time mode cleaning step of setting a fixed time to perform a second cleaning step to ensure the etching Anti-. . . _ The chamber should be completely clean. The preferred air pressure, upper and lower electrode power and gas flow are 200 mT, 2000/1500 W and 600 seem, respectively. φ Next, the following cleaning steps are performed on different sections inside the etching reaction chamber to make the state of the etching reaction chamber more stable. The third cleaning step: a relatively low-pressure, high-flow oxygen-containing cleaning plasma gas is used to remove residual gas in the etching reaction chamber, and the preferred gas pressure value, upper and lower electrode power and gas flow rate are 40 mT, 2000/1500 W, respectively. 1200 seem. 'Four cleaning step: the cleaning gas containing the blunt gas is not applied with the applied voltage. The slurry gas removes the residual gas in the etching reaction chamber. 1305945 The preferred gas is argon gas, and the gas pressure value is between 20-30mT. The gas flow rate is between 500 and 1000 sccm; and the preferred gas pressure and gas flow are 25 mT and 800 seem, respectively. The fifth cleaning step: introducing a mixture of carbon tetrafluoride, oxygen and argon to clean the plasma gas 'to keep the etching reaction chamber in a stable state, the gas pressure value is between 30-100 mT, and the gas flow ratio (CF4) /〇2/Ar) is 100-150/ 0-20/100-200; and the preferred gas pressure value, upper and lower electrode power, and gas flow rate (CF4/〇2/Ar) are 60 mT, 800/150 W, and 140/10/150 seem. It is worth noting that the implementation of the waferless dry cleaning process can be performed between the etching steps of the semiconductor wafers in the double-well-embedded structure, between the batches of semiconductor wafer etching processes or any etching. Process room. As described above, the present invention discloses a method for fabricating a dual damascene structure, in which the etching process and the photoresist ashing process are performed in the same etching reaction chamber, which can greatly reduce the time required for the transmission time of the machine conversion room, and is light-receiving. The obstruction layer formed by the resistors can ensure that the conductive layer on the bottom layer of the semiconductor wafer is free from the multiple defects of the process, and the production method can be performed separately. A quick step of the money engraving, in order to match the long-term, weekly, and timely with the non-crystal dry cleaning process, can also increase the cleaning time of the cleaning chamber (mean time 1305945 between clean), greatly improved Semiconductor crystal. The production efficiency of the circle. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figures 1 through 5 are schematic views of a preferred embodiment of the present invention for fabricating a dual damascene structure. 6 to 8 are schematic views showing the process of fabricating a dual damascene structure on a semiconductor wafer having no protective layer. [Main component symbol description] 10 Semiconductor wafer 12 Substrate 14 Conductive layer 16 Protective layer 18 Dielectric layer 20 Hard mask layer 22 Bulk layer 24 Interlayer hole 26 Ditch pattern 28 Ditch 30 Semiconductor wafer 32 Substrate 34 Conductive layer 36 Electrical layer 38 hard mask layer 40 photoresist 42 via hole 44 trench pattern 46 trench