TWI467697B - Method for fabricating an interconnection structure - Google Patents

Description

Method for manufacturing interconnect structure

This invention relates to a semiconductor process and, more particularly, to a method of fabricating an interconnect structure.

Dual damascene technology with ultra low-k materials is currently known for high-accumulation, high-speed logic IC chip fabrication and semiconductor fabrication below 0.18 micron. Metal interconnect solution. The reason is that copper has low resistance (30% lower than aluminum) and better resistance to electromigration resistance, while ultra-low dielectric materials can help reduce the RC delay between metal wires. It can be seen that the ultra-low dielectric material with copper metal dual damascene interconnect technology is becoming more and more important in the integrated circuit process.

The copper metal dual damascene interconnect process can be divided into three types: trench first type, via first form and self-aligned type. In the double damascene process in which the trench is formed first, since the trench is formed first, a part of the ultra-low dielectric material at the bottom of the trench is removed to form a via hole. Therefore, the polymer formed in the process is often left on the sidewalls and the bottom of the via hole (that is, the surface of the copper metal), resulting in an increase in resistance value and an RC delay effect. In order to solve this problem, the trench and the via hole are cleaned before the copper metal is filled into the via hole to remove the polymer remaining on the sidewall and bottom of the trench and the via hole.

Conventional cleaning processes are mostly dry cleaning, which uses a plasma cleaning process to remove the polymer from the trenches and vias. However, since the ultra-low dielectric material layer reacts with hydrogen ions and increases the dielectric constant of the ultra-low dielectric material layer, the conventional reactive pre-clean (RPC) process is not suitable for use. In a dual damascene structure of an ultra-low dielectric material layer. To this end, it is conventionally proposed to perform a plasma cleaning process with argon gas, which can avoid the problem of dielectric constant shift in the process of ultra-low dielectric material layer in the process, but the double produced by this method The mosaic structure has the problem of insufficient reliability.

In U.S. Patent No. 6,713,402, "Method for the removal of the etch-stop layer etch", it is disclosed that after the formation of the via hole, the substrate is transferred to the operating temperature. In a plasma cleaning chamber at 310 ° C, a plasma containing hydrogen was introduced to remove residual polymer. However, in addition to affecting the adhesion of the interface between the layers, the organic gas released in such a high-temperature cleaning process is also susceptible to chemical reaction with hydrogen ions and formation of by-products. At this time, an ultra-low dielectric material belonging to a porous material will easily adsorb these by-products, so that these by-products adhere to the sidewalls and the bottom of the via hole, resulting in a decrease in the process yield of the dual damascene structure.

Therefore, how to remove the polymer produced by etching the ultra-low dielectric material layer in a simpler and more efficient manner without destroying the dual damascene structure during the cleaning process is still an urgent problem to be researched and improved in the industry.

In view of the above, an object of the present invention is to provide a method for fabricating an interconnect structure that can effectively remove by-products generated in a process without damaging the interconnect structure to improve process yield.

The present invention provides a method of fabricating an interconnect structure in which a substrate is first provided, wherein a first conductive layer has been formed on the substrate. Next, an ultra-low dielectric material layer is formed on the substrate, and a portion of the ultra-low dielectric material layer is removed to form an opening to expose the first conductive layer. Then, a gas is introduced to perform a dry cleaning process to clean the surface of the first conductive layer exposed by the opening. Among them, the dry cleaning process has an operating temperature of 50 °C.

In an embodiment of the invention, the gas comprises hydrogen.

In an embodiment of the invention, the gas content of the gas is 20% of the total content.

In an embodiment of the invention, the gas further comprises an inert gas such as helium.

In one embodiment of the invention, the ratio of hydrogen to helium in the gas is 1:4.

In an embodiment of the invention, in the gas, the flow rate of hydrogen gas is 200 sccm, and the flow rate of helium gas is 800 sccm.

In an embodiment of the invention, before forming the ultra-low dielectric material layer, the method further comprises forming a first barrier layer covering the first conductive layer on the substrate, and removing a portion of the ultra-low dielectric material layer And further comprising removing a corresponding portion of the first barrier layer to form the opening to expose a portion of the first conductive layer.

In an embodiment of the present invention, before removing a portion of the ultra-low dielectric material layer, further comprising forming a hard mask layer on the ultra-low dielectric material layer, and then removing a portion of the hard mask layer to The layer of the ultra-low dielectric material is exposed to form the opening.

In one embodiment of the invention, a method of forming the opening includes first removing a first portion of the layer of ultra low dielectric material to form a trench. Then, the second portion of the ultra-low dielectric material layer located in the trench is removed to form a via hole to form the opening with the trench.

In an embodiment of the invention, the second conductive layer is filled in the opening to electrically connect the second conductive layer to the first conductive layer.

In an embodiment of the invention, before the filling the second conductive layer, the second barrier layer is further formed to cover the sidewall of the opening.

In an embodiment of the invention, the dielectric constant of the ultra-low dielectric material layer Between 1.9 and 2.5. For example, the dielectric constant of the ultralow dielectric material layer is, for example, 2.0.

The invention performs a dry cleaning process in an operating environment between room temperature and 100 ° C after forming an opening in the ultra low dielectric material layer to reduce the gas used in the cleaning process and the residual in the opening. The exhaust gas generated by the reaction of the product, in turn, prevents excessive exhaust gas from being completely removed from the opening and affecting the electrical properties of the subsequently formed interconnect structure.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

1 is a schematic cross-sectional view showing an interconnect structure in a partial process in an embodiment of the present invention. Referring to FIG. 1 , a substrate 110 is first provided, wherein a dielectric layer 112 and a first conductive layer 114 have been formed on the substrate 110 , and the first conductive layer 114 is embedded in the dielectric layer 112 , for example. Specifically, the material of the first conductive layer 114 is, for example, copper. Next, an ultra low-k material layer 120 is formed on the substrate 110 to cover the first conductive layer 114. In the present embodiment, the material of the ultra-low dielectric material layer 120 is, for example, AMAT's BlackDiamond II, and its dielectric constant is between 1.9 and 2.5, and preferably 2.0, but the invention is not limited thereto.

In addition, in this embodiment, before the formation of the ultra-low dielectric material layer 120, a first barrier layer 115 may be formed on the substrate 110, which is formed, for example, of tantalum nitride to avoid the first conductive layer 114. Metal atoms diffuse into the ultra low dielectric material layer 120.

Continuing, a portion of the ultra-low dielectric material layer 120 and the corresponding first barrier layer 115 are removed to form an opening 122 exposing the first conductive layer 114. In detail, the opening 122 is formed by, for example, using a patterned photoresist layer (not shown) as a mask and etched. Moreover, after removing the patterned photoresist layer, The by-products generated in the etching process are prevented from remaining in the opening 122 to affect the yield of the subsequent process, and then the dry cleaning process is performed. In this embodiment, the plasma cleaning process is used to remove the residuals remaining in the opening 122. product. Since the Aktiv pre-clean (abbreviated as APC) process has high cleaning efficiency, and the interconnect structure of the cleaning process can have sufficient electron migration reliability, the embodiment is, for example, cleaning the opening by APC. 122. In detail, in the present embodiment, the plasma cleaning process is performed by introducing the gas G, wherein the gas G includes, for example, hydrogen gas. Since hydrogen radicals released by hydrogen gas can react with by-products remaining in the opening 122 to form a gas, it is possible to simultaneously perform pumping in the cleaning process to extract these gas products.

It should be noted that since the radical of hydrogen is easily reacted with the residue containing ruthenium at a high temperature (for example, above 150 ° C) to form an exhaust gas, the exhaust gas is completely removed before the conductive metal is filled in the opening 122. Then, subsequent electrical processing will result in electrical damage to the first conductive layer 114. Therefore, in this embodiment, the operating temperature of the cleaning process is controlled between room temperature and 100 ° C, and preferably between room temperature and 60 ° C, for example, 50 ° C, to reduce the free radicals and hydrogen content of hydrogen. The amount of waste gas generated by the reaction of the residue. The term "room temperature" as used herein refers to a temperature which does not cool or heat the working environment, and is usually about 25 ° C, but it is not intended to be within the scope of the present invention.

2A to 2D are respectively a dense interlayer plug of a Wafer Acceptance Test (WAT) after a cleaning process on an internal wiring structure on a wafer at different temperatures according to an embodiment of the present invention. A schematic diagram of a chain (Via Chain), and this embodiment shows oblique regions of electrical defects on the wafer 210. Referring to FIG. 2A to FIG. 2C, when the temperature of the cleaning process is 310 ° C, 200 ° C, and 150 ° C, respectively, a high proportion of electrical defective regions are subsequently measured on the wafer 210 . however, When the temperature of the cleaning process is controlled to 50 ° C, only a small number of electrically defective regions are subsequently measured on the wafer 210 as shown in FIG. 2D. Therefore, it can be seen that the temperature is controlled to be 100 ° C or less in the process of cleaning the opening 122 of FIG. 1 , and the process yield of the interconnect structure can be effectively improved.

Please continue to refer to FIG. 1 . In addition, in order to avoid excessive amount of hydrogen introduced, it may react with the by-products remaining in the opening 122 to generate excessive exhaust gas, and may not be completely extracted. In other embodiments, Reduce the amount of hydrogen in the dry cleaning process, and thus reduce the exhaust gas generated by the reaction of hydrogen and by-products. For example, in a dry cleaning process, hydrogen and an inert gas such as helium may be simultaneously introduced. Here, the hydrogen content in the gas G is, for example, 20%. For example, a preferred ratio of hydrogen to helium may be 1:4, and a flow rate of hydrogen may be 200 sccm, and a flow rate of helium may be 800 sccm.

The process disclosed in the above embodiments of the present invention is suitable for fabricating any interconnect structure having an ultra-low dielectric material layer. To familiarize the person skilled in the art with the present invention, the process of the dual damascene structure is exemplified below. The drawings are intended to further illustrate the invention, but are not intended to limit the invention.

3A-3B are schematic cross-sectional views showing a process of fabricating a dual damascene structure by first forming a trench first in an embodiment of the present invention. Referring to FIG. 3A, a substrate 310 is first provided, on which a dielectric layer 312 and a first conductive layer 314 are formed, wherein the first conductive layer 314 is embedded in the dielectric layer 312 and formed on the first conductive layer 314. There is a first barrier layer 316 which is composed, for example, of silicon nitride. Next, an ultra-low dielectric material layer 320, an etch stop layer 330, a hard mask (HM) 340, and a cap layer 350 are formed on the first barrier layer 316, wherein the ultra-low dielectric material layer The material of 320 is, for example, AMAT's BlackDiamond II, but the invention is not limited thereto. Moreover, the dielectric constant of the ultra-low dielectric material layer 320 is approximately between 1.9 and 2.5. Preferably, it is 2.0. The material of the etch stop layer 330 may be bismuth oxynitride (SiON), and the material of the hard mask layer 340 may be titanium nitride (TiN). Moreover, the cap layer 350 may be a single layer structure or a composite layer structure such as ruthenium oxynitride/ruthenium oxide.

Then, a portion of the cap layer 350, the hard mask layer 340, the etch stop layer 330, and a portion of the ultra-low dielectric material layer 320 below it are removed to form the trenches 322 in the ultra-low dielectric material layer 320. In this embodiment, for example, some of the film layers are removed by lithography, and the etching process is terminated at a certain depth of the ultra-low dielectric material layer 320 by the control of the etching parameters, thereby forming the trenches 322. After the trench 322 is formed, a portion of the ultra-low dielectric material layer 320 and the corresponding first barrier layer 316 in the trench 322 are removed to form a via 324. Here, the via 324 and the trench 322 constitute an opening 321 exposing the first conductive layer 314.

Specifically, the via hole 324 is formed by first forming a patterned photoresist layer (not shown) on the ultra low dielectric material layer 320 to expose a portion of the ultra low dielectric material layer 320 within the trench 322. Then, the photoresist layer is patterned as a mask, and the ultra-low dielectric material layer 320 and the corresponding first barrier layer 416 are etched to form via holes 324. Then, the remaining patterned photoresist layer is removed.

As described above, since the by-products generated in the process are often left in the opening 321 when the remaining patterned photoresist layer is removed, a dry cleaning process must be performed to remove the after-etch process. By-products remaining in the trench 422 and the via 424. For example, in this embodiment, the gas G is introduced into the working environment at a temperature between room temperature and 100 ° C to perform a plasma cleaning process, and the preferred operating temperature is between room temperature and 60 ° C. , for example, 50 ° C. The gas G may include hydrogen. The plasma cleaning process at a temperature between room temperature and 100 ° C can reduce the waste generated by the reaction of hydrogen radicals with ruthenium-containing residues. Therefore, in addition to effectively removing the by-products in the trench 322 and the via 324, the present embodiment can reduce the difficulty in completely extracting the exhaust gas in the trench 322 and the via 324.

Further, in the gas G of the present embodiment, the proportion of hydrogen is about 20% to 50%, and the remainder may be an inert gas such as helium. Specifically, in the gas G used in the present embodiment, the ratio of hydrogen gas to helium gas may be 1:2 or 1:4. In the embodiment where the ratio of hydrogen to helium is 1:4, the flow rate of hydrogen gas is, for example, 200 sccm, and the flow rate of helium gas is 800 sccm.

It can be seen from the above that the present embodiment can reduce the amount of hydrogen used in the dry cleaning process by reducing the operating temperature in the dry cleaning process to prevent hydrogen from reacting with by-products remaining in the opening to generate excessive exhaust gas. The generation of exhaust gas is further reduced to avoid adverse effects on the electrical properties of the formed dual damascene structure in subsequent processes due to exhaust gas detachment.

4 is a comparative graph of copper signals measured by Auger electron spectroscopy (AES) in the opening after the openings in the openings are cleaned by different dry cleaning processes after the openings are formed in the foregoing process. Please refer to FIG. 3A and FIG. 4 at the same time, the two points E1 and E2 on the horizontal axis coordinate respectively represent two internal connection structures for dry cleaning process with different working temperatures, and the vertical axis coordinate value is measured in the opening. Copper signal. Among them, the interconnect structure represented by E1 is the above APC cleaning process under the high temperature working environment of 310 ° C, and the interconnect structure represented by E2 is the above APC cleaning process under the working environment of 50 ° C. In contrast, the average value of the copper signal corresponding to E2 is greater than the average value of the copper signal corresponding to E1. It can be seen that the APC cleaning process in a working environment of 50 ° C can effectively clean the residue in the trench 422 and the via 424 to avoid the APC cleaning process in a working environment at a high temperature of 310 ° C. The first conductive layer 314 is covered by the residue, so that more copper can be measured. Signal.

Referring to FIG. 3B, a second conductive layer 360 is filled in the trench 322 and the via 324 to form a dual damascene structure 300. The material of the second conductive layer 360 is, for example, copper, and the detailed process of filling the second conductive layer 360 is well known to those skilled in the art and will not be described herein.

In addition, before the second conductive layer 360 is filled in the embodiment, a second barrier layer 370 is formed to cover the sidewalls and the bottom of the trench 322 and the via 324 to avoid the second conductive layer 360 being subsequently filled. The metal ions in the diffusion diffuse into the ultra-low dielectric material layer 420 through the sidewalls of the trench 322 and the via 324. In the process of forming the second barrier layer 370, the thickness of the second barrier layer 370 at the bottom of the via hole 324 can be determined by adjusting parameters to reduce the subsequently filled second conductive layer 360 and the first The impedance between the conductive layers 314.

The invention performs a dry cleaning process in an operating environment between room temperature and 100 ° C after forming an opening in the ultra low dielectric material layer to reduce the gas used in the cleaning process and the residual in the opening. The exhaust gas generated by the reaction of the product can avoid excessive exhaust gas and is difficult to completely withdraw. Moreover, in addition to controlling the operating temperature, the present invention can also reduce the amount of hydrogen used in the dry cleaning process to achieve the same effect.

Based on the above, the present invention can not only effectively clean the by-products remaining in the opening, but also prevent the exhaust gas generated in the cleaning process from remaining in the opening and adversely affecting the electrical properties of the interconnect structure, and further maintaining The reliability of the connection structure also increases the process yield.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

300‧‧‧Dual inlay structure

110, 310‧‧‧ base

112, 312‧‧‧ dielectric layer

114, 314‧‧‧ first conductive layer

115, 316‧‧‧ first barrier layer

120, 320‧‧‧ ultra low dielectric material layer

122,321‧‧‧ openings

210‧‧‧ wafer

322‧‧‧ Ditch

324‧‧‧Intermediate hole

330‧‧‧etch stop layer

340‧‧‧hard mask layer

350‧‧‧Top cover

360‧‧‧Second conductive layer

370‧‧‧second barrier layer

G‧‧‧ gas

1 is a schematic cross-sectional view showing an interconnect structure in a partial process in an embodiment of the present invention.

2A to 2D are respectively schematic diagrams of parameter testing of a wafer after a cleaning process on an internal wiring structure on a wafer at different temperatures according to an embodiment of the present invention.

3A-3B are schematic cross-sectional views showing a process of fabricating a dual damascene structure by first forming a trench in an embodiment of the present invention.

4 is a comparative graph of copper signals measured in the openings after the openings in the openings are cleaned by different dry cleaning processes after the openings are formed in the foregoing process.

310. . . Base

312. . . Dielectric layer

314. . . First conductive layer

316. . . First barrier layer

320. . . Ultra low dielectric material layer

322. . . ditch

324. . . Via hole

321. . . Opening

330. . . Etch stop layer

340. . . Hard mask layer

350. . . Roof layer

G. . . gas

Claims (14)

A method of fabricating an interconnect structure includes: providing a substrate, wherein a first conductive layer is formed on the substrate; forming an ultra-low dielectric material layer on the substrate; removing the portion of the ultra-low dielectric material a layer to form an opening to expose the first conductive layer; and a gas to be subjected to a dry cleaning process to clean the surface of the first conductive layer exposed by the opening, wherein the dry cleaning process works The temperature is 50 °C. The method of manufacturing an interconnect structure as described in claim 1, wherein the gas comprises hydrogen. The method for manufacturing an interconnect structure as described in claim 2, wherein the hydrogen content in the gas is from 20% to 50% of the total content. The method of manufacturing an interconnect structure as described in claim 2, wherein the gas further comprises an inert gas. The method of manufacturing an interconnect structure as described in claim 4, wherein the inert gas comprises helium. The method for manufacturing an interconnect structure according to claim 5, wherein the ratio of hydrogen to helium in the gas is 1:2 to 1:4. The method for manufacturing an interconnect structure according to claim 6, wherein in the gas, the flow rate of hydrogen gas is 200 sccm, and the flow rate of helium gas is 800 sccm. The method for manufacturing an interconnect structure according to claim 1, wherein before forming the ultra-low dielectric material layer, further comprising forming a first barrier layer over the substrate to cover the first conductive layer, And removing a portion of the ultra-low dielectric material layer, further comprising removing a corresponding portion of the first barrier layer to form the opening to expose a portion of the first conductive layer. The method for manufacturing an interconnect structure according to claim 1, wherein before removing the portion of the ultra-low dielectric material layer, the method further comprises: forming a hard mask layer on the ultra-low dielectric material layer. And removing a portion of the hard mask layer to expose the layer of the ultra-low dielectric material to form the opening. The method of manufacturing the interconnect structure of claim 9, wherein the method of forming the opening comprises: removing a first portion of the ultra-low dielectric material layer to form a trench; An ultra-low dielectric material layer is located in a second portion of the trench to form a via and to form the opening with the trench. The method for manufacturing an interconnect structure according to claim 9 further includes filling a second conductive layer in the opening to electrically connect the second conductive layer to the first conductive layer. The method for fabricating an interconnect structure according to claim 11, wherein before filling the second conductive layer, further comprising forming a second barrier layer to cover sidewalls of the opening. The method of fabricating an interconnect structure as described in claim 1, wherein the ultra low dielectric material layer has a dielectric constant of between 1.9 and 2.5. The method for fabricating an interconnect structure as described in claim 13 wherein the ultra low dielectric material layer has a dielectric constant of 2.0.