TWI301647B - Chip package and process for the same - Google Patents

Description

1301647 IX. Description of the Invention: [Technical Field] The present invention relates to a wafer structure and a wafer assembly process, and particularly relates to a kind of high-electricity Wei Zhijing (four) device and its riding crystal 4S 〇[Prior Art] With the rapid advancement of technology of poor news products, human beings want to quickly obtain information thousands of miles away. It is no longer a difficult situation to achieve time-saving advantages, through the construction of high-scale capital reduction The product can be dazzled. With the integration of new products and the integration of various circuit designs, the latest single-chip offers more functions than ever before. Due to the rapid changes in the semi-conducting technology, the mass production of the copper process is successful, and the integration of the circuit can be carried out. Most of the signal transmission can be in the same single chip, so that the transmission path of the signal can be shortened and the performance of the chip can be improved. 0曰 After the wafer fabrication is completed, the wire is electrically connected to the substrate by using a wire or a wire. Decoration, whether it is a wire or a convex ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SUMMARY OF THE INVENTION [J] In view of the above, it is an object of the present invention to provide a wafer structure and a wafer structure that can be connected to a circuit and a circuit of a semiconductor wafer to improve electrical performance. In order to achieve the object of the present invention, the present invention provides a wafer package comprising a half conductor wafer and a circuit connecting member. The semiconductor wafer has a first line, and the connecting member has a second line, wherein the second line 2 of the circuit connecting member is in contact with the first line of the semiconductor wafer. The emirate further provides a wafer package comprising a semiconductor wafer, a conductive layer and a circuit connecting member, wherein the semiconductor wafer has a first line, and the electrical 1301647 has a second line, and the conductive layer is connected. — the road, and the composition of the conductive layer includes the metal particles of the polymer and the majority of the metal layer of the 'the first line of the metal layer'; the first one also provides a circuit connecting member, wherein the circuit ϋ, the hemp road _ "The first line of the g-body chip. In addition, the present invention also proposes a wafer assembly system. First, a semiconductor wafer is provided, wherein a half-mtt: 丄 step: 3 also: for a circuit connection member, wherein: The member has a second line of a two-wire two-conductor circuit connecting member, and the metal particles of the conductive layer are electrically connected to the first (four) one line for the present invention. Nothing (four), special direct ί:: ίί=ί==: In: the line of the semiconductor chip can be large-faced _ sex:; = ^ 1301647 to improve the riding relationship between the semiconductor wafer and the circuit connection components. In addition, the semiconductor crystal line can pass through the line containing the wire compound and the metal layer of the large-area connection-circuit connecting member, so that the semiconductor chip and the circuit connecting member can be greatly changed. . ^Simplified system The contents of the above-mentioned components of the drawings are represented by the same reference numerals, and the components represented by the same number are explained in the following. Second, the first embodiment of the wafer assembly, in the first embodiment of the wafer assembly, the semiconductor wafer has a thick metal line, located in the surface layer of the semiconductor wafer, the semiconductor crystalline thick metal line can be connected directly / contact The wiring of the substrate. As shown in the following, the circuit configuration of the thick metal line and the substrate of the semiconductor wafer is used as the signal transmission in the semiconductor. FIG. 1 shows the wafer assembly in accordance with the first embodiment of the present invention. A schematic cross-sectional view of a front semiconductor wafer and a substrate, wherein a cross-sectional portion of the thick metal line cut through the semiconductor wafer is formed by cutting a section of the semiconductor wafer along an extending path of the thick metal line, and a section of the line cut through the substrate is Along the path of the line on the substrate, the section of the substrate is cut perpendicularly. The semiconductor wafer 100 includes a half of the conductor substrate 110, a plurality of thin film dielectric layers 122, 124, 126, a plurality of thin film wiring layers 132, 134, 136, and a protective layer 140. The semiconductor substrate 11 has a plurality of electronic components 112. The electronic components 112 are disposed on a surface layer of the active surface 114 of the semiconductor substrate 11. The semiconductor substrate 110 is, for example, a germanium substrate, and is doped with pentavalent or trivalent ions. For example, boron ions or phosphorus ions, thereby forming a plurality of electronic components 112 on the surface layer of the semiconductor substrate 110, such as a metal oxide semiconductor or a transistor 1301647, can be formed by chemical gas deposition, and a multilayer film can be formed. The electrical layers 122, 124, 126 are on the active surface 114 of the semiconductor substrate ι10, wherein the thin film dielectric layers 122, 124, 126 are, for example, oxonium compounds, arsenide compounds or oxynitride compounds, and each of the thin film wiring layers 132. 134, 136 are respectively disposed on one of the thin film dielectric layers 122, 124, 126, wherein the material of the thin film wiring layers 132, 134, 136 includes, for example, aluminum, copper or tantalum. The thin film dielectric layers 122, 124, and 126 have a plurality of via holes 121, 123, and 125, and the thin film wiring layers 132, 134, and 136 may be connected to each other by the via holes 121, 123, and 125 of the thin film dielectric layers 22, 124, and 126. Electrically connected and electrically connected to the electronic component 112. The protective layer 140 is disposed on the thin film dielectric layers 122, 124, 126 and the thin film wiring layers 132, 134, 136, wherein the thickness z of the protective layer 14 is, for example, greater than 〇35 μm and the structure of the protective layer 140 is It is a composite layer composed of a nitrile compound layer, an oxonium compound layer, a phosphorous-phosphorus glass layer or at least one of the above materials. The protective layer 140 has a plurality of openings 142 exposing the thin film wiring layer 136 at the top layer. The thick metal line 150 is located on the protective layer 14 , and is electrically connected to the thin film circuit layer 136 via the opening 142 of the protective layer M , wherein the thickness of the thick metal line 15 大于 is greater than the thickness of the thin film circuit layers 132 , 134 , 136 . . The bumps 160 are substantially aligned with the openings 142 of the protective layer 14 and are electrically connected to the thin film wiring layer 136. In the process, the thick metal line 15 〇 and the bump 16 〇 can be completed simultaneously by the same process, so the thick metal line and the bump 16 〇 can have the same metal layer structure, the thick metal line 15 〇 and the bump 16 〇 The metal layer structure is described in detail later, skipped here first. It is worth noting that the thickness j of the thick metal line 15 is substantially the same as the thickness of the bump 160. The thickness of the road 15 (4) and the thickness of the bump 〇 are larger than, for example, more preferred. More than 5 microns. The form of the substrate 200 may include a hard board or a soft board. The hard board is generally formed by overlapping layers of 1301647 multilayer circuit layers and insulating layers, such as a common four-layer board, a six-layer board or an eight-layer board on the market. The material of the insulating layer is, for example, a polymer or ceramic: porcelain. The soft board is composed of, for example, a circuit layer and an insulating layer, and the circuit layer is located on the insulating layer, wherein the material of the insulating layer is, for example, a polymer, and the thin layer has a thin thickness. Has a large flexibility. As mentioned above, the 丞 丞 200 can be in the form of a hard or soft board. The substrate 200 = if there is a - circuit layer 210 and a solder mask layer 22G, which is located at the top of the substrate, and the cover layer 22 is positioned on the circuit layer 210 of the substrate 2 to protect the circuit layer 1 ' The layer 21 has a line and a pad, and the opening 222 of the solder mask layer 220 exposes the line 212 and the interface 214 of the circuit layer 21 . In addition, in the form of a line, the thick metal line of the semiconductor wafer may be extended in the front of the semiconductor wafer in any direction, such as a linearly extending form, a curved extension, or a discontinuous recess. A 2 minute extension path, and the substrate line 212 may also extend along any = toward the top of the f substrate 200, such as a form that extends like a straight line, a curved form, or an extended line with a discontinuous portion. The thick metal line 15 of the semiconductor wafer 100 can be aligned with the line 212 of the board 200 when the thick metal line 150 and the thin line 00 of the substrate are bonded. In one embodiment, the thick line of the semiconductor wafer 100 has a line 212 such as an inductor tree of the shape, as shown in FIG. 9 and FIG. The line 212 is cast, and FIG. 1 is a schematic plan view of the semiconductor wafer in FIG. 1 = this 3 to the flat *. Referring to FIG. 2, the winding path of the inductive component 150 of the body wafer 100 is in a mirror relationship with the winding path of the inductive component 212 of the substrate 21301647, and the inductive component 212 of the substrate 2 is along the path. The path 11〇〇 extends, for example, from the path 11 .. X point = to the Y point of the path 1100; the inductive component 150 of the semiconductor wafer 100 • extends along the path 1200, such as from the path 12 The point extends to the y point of path 1200. Referring to FIG. 2, a cross-sectional view of the wafer structure after the semiconductor wafer and the substrate of FIG. 1 are bonded is shown. After the semiconductor wafer 1 and the substrate 2 are provided, a bonding step may be performed so that the thick metal lines 15 of the semiconductor wafer 1 can be directly connected to the line 212 of the substrate 200, and the semiconductor wafer 1 The bumps 160 can be directly connected to the pads 214 of the substrate 2 . Next, a polymer layer 170 may be filled between the semiconductor wafer 1 and the substrate 2, and the e-rich layer 17 is coated around the thick metal line 150 and around the bump 160. A plane 1000 is defined which is substantially parallel to the main-, moving surface 114 of the semiconductor substrate u, wherein the region where the thick metal line 150 is connected to the substrate line 212 and the extent s on the plane 1000 is, for example, greater than 5 〇〇. Micron, or for example greater than 800 microns, or for example greater than 1200 microns; the area of the region where the thick metal line 150 is connected to the substrate line 212 is projected onto the plane 1 〇 (9), for example, greater than 30,000 square microns, or for example greater than 8 〇, 〇〇〇 square microns, or for example greater than 150,000 square microns. In one embodiment, referring to FIG. 1A and FIG. 1B, when the inductive component 212 of the substrate 200 directly contacts the inductive component of the semiconductor wafer 1

At 150 o'clock, A, B, C, D, E, F, G of the inductive component 212 of the substrate 200

The regions are in direct contact with the a, b, c, d, e, f, g regions of the inductive element 15A of the semiconductor wafer. Please refer to FIG. 2A , which is a schematic plan view showing the connection area of the two inductive elements 212 , 150 of FIG. 1A and FIG. 1B joined to the plane 1 ,, where the two inductive elements 150 , 212 are connected ( FIG. 2A 1301647 The area of the slashed line) the extent of the projection onto the plane 1000 (the distance of the path 12q〇 extending from the X point to the y point) is, for example, greater than 500 microns, or for example greater than 800 microns, or for example greater than 12 microns. The area where the two inductive elements 15〇, 212 are connected (the area marked with a diagonal line in FIG. 2A) is projected onto the area on the plane 1〇〇〇; for example, is greater than 30,000 square microns, or is, for example, greater than 80, 〇〇〇 square micron, Or it is, for example, greater than 150,000 square microns. Referring to FIG. 2, in the electrical transmission, one of the electronic components 112 in the semiconductor chip 1 (such as the electronic component n2a) is adapted to output an electronic signal, and the electronic signal passes through the thin film circuit layers 132, 134, After passing through the protective layer 140, the 136 is transferred to the thick metal line 150 and the line 212 of the substrate 200, passes through the protective layer 140, and is transferred to other semiconductor wafers 100 via the thin film wiring layers 136, 134, and 132. At least one of the electronic components 112 (than the 'electronic component 112b'); at this time, the thick metal line 15 of the semiconductor wafer 100 and the line 212 of the substrate 200 can be used for signal transmission in the semiconductor wafer. In addition, the electronic signal can be transmitted to the substrate 2 after being transferred from the electronic component 112a to the thick metal line 150 and the line 212 of the substrate 200; at this time, the thick metal line 150 and the substrate 2 of the semiconductor wafer 100 are The line 212 can also be used for signal transmission between the semiconductor wafer 100 and the substrate 200. In the electrical transmission of the bumps 160, the semiconductor wafers 1 can transmit electronic signals to the substrate 200 through the bumps 160, or can receive the electronic signals transmitted from the substrate 200 through the bumps 16A. As described above, the thick metal line 150 of the semiconductor wafer 100 and the line 212 of the substrate 2 can be used as a lateral transmission between the semiconductor wafer 100 and the substrate 200 in addition to the lateral transmission of the electronic signal. Since the thick metal line 150 of the semiconductor chip 100 is directly in contact with the line 212 of the substrate 2, the thick metal line 15 of the semiconductor wafer 100 can be connected to the line 212 of the substrate 200 in a large area. The efficiency of electrically connecting the semiconductor wafer 11 1301647 10 〇 to the substrate 200 is increased, and the generation of noise can be reduced. In the electrical transmission of the electronic signal, the thick metal 150 of the semiconductor wafer 100 and the line 212 of the substrate 200 serve as signals in the semiconductor wafer 100; and serve as a signal between the semiconductor wafer 100 and the substrate 200. Passed]. However, the application of the present invention is not limited thereto, and the thick metal line 150 of the semiconductor wafer and the line 212 of the substrate 200 may also be used only for signal transmission in the semiconductor wafer, not as the semiconductor wafer 1 and the substrate 2. In the meantime, the line 212 of the substrate 200 is in a state of being electrically disconnected from the other lines in the substrate 2 . In other implementations, the substrate 200 can also be adapted to output an electronic signal, 'the line 212 that is transferred to the substrate 200, and the thick metal line 15〇, and then pass through the protective layer 140 of the semiconductor wafer 100, and through the thin film circuit layer. 136, 134, : U2 are transferred to at least one electronic component 112 (such as electronic components 112a and 112b) within semiconductor wafer 100. In FIGS. 1 and 2, the thick metal line 150 is formed directly on the protective layer 140. However, the 'thick metal line 15' may be formed on the protective layer 180 on the protective layer, as shown in FIG. A cross-sectional view of another wafer package in accordance with a first embodiment of the invention is shown. Referring to FIG. 3, a polymer layer 180 is formed on the protective layer 14A. The polymer layer has a plurality of openings π], which are substantially aligned with the openings 142 of the protective layer 140, and the thick metal lines 15 are formed in the polymerization. The layer 180 is attached to the thin film wiring layer 136 via the opening 182 of the polymer layer 18 and the opening 142 of the protective layer 140. It is noted that the thickness h of the bump 160 protruding beyond the opening 182 of the polymer layer 180 is, for example, substantially the same as the thickness j of the thick metal line 15A on the polymer layer 180, and the thick metal line 150 The same as the bump 160 has the same metal layer structure, wherein the thickness h of the bump 160 protruding beyond the opening 182 of the polymer layer 180 and the thickness j of the thick metal line 150 located on the polymer layer 180 are greater than i. Micro 12 1301647 meters, in preferred cases, such as greater than 5 microns. The thickness k of the polymer layer 18〇 is, for example, greater than 1 μm, and the material of the polymer layer 1 (10) is, for example, polyimide (PI), benzocyclobutene (BCB), polyarylene. Parylene, porous dielectric material or elastomer. In FIGS. 1 to 3, the thick metal line 150 is permeable to the protective layer 14: the opening 142 is connected to the top film layer 136 in a small area; however, the thick metal line 150 may also be through the protective layer 14. The large opening 142 is connected to the top film layer 136 over a large area, as shown in FIG. 4 and FIG. 5, which is a cross-sectional view showing another form of the wafer structure according to the first embodiment of the present invention, wherein the top film line The layer 136 has a thin film line 137, and the opening ι 42 of the protective layer 14 exposes the thin film line 137 over a large area, so that the thick metal line 15 〇 can connect the thin film line 137 exposed by the opening 142 of the protective layer 140 over a large area. The above-mentioned large-area connection is as follows. Referring to Figures 4 and 5, the first case of large-area connection: defines a plane 1000 which is substantially parallel to the active surface 114 of the semiconductor substrate 11 and the thick metal line 150 is connected to the thin film line 137. The area projected onto the plane 1000 by the area is divided by the film line 137 projected onto the plane 1 (: the ratio of the areas is, for example, greater than 〇·5, or such as greater than 〇·8, or such as substantially equal to one. The second case of large-area connection: the opening of the protective layer 140, the area of the 142 chrome-out film line 137 is, for example, greater than 3 〇, 〇〇〇 square micron, or, for example, greater than 80,000 square microns, or such as greater than 15 〇, 〇〇〇 square micron. A third case of large-area connection: the area where the thick metal line 150 is connected to the thin film line layer 136 is projected to the plane 1 延伸, for example, the extension distance t is greater than 500 μm, or for example More than _micron, or, for example, greater than 1200 micrometers. As long as it meets any of the above, it can be said that the thick-line circuit 150 is a large-area connection of the top film circuit layer 136. In the embodiment, when the thick metal line 15 of the semiconductor wafer 100, such as 13 (S) 1301647, is a spiral inductor element, the gold thin film green 137 IX IX, the order I is a green road 150 large area connection diagram Figure 4 and Figure V are the inductive components of the job. As shown in Figure 5A, the area where the thick metal line and the film line are connected to the flat 10 (8) is projected into a meandering H t schematic 'where thick metal, line and The thin 臈 line is the path bile extension, for example, it extends from the P point of the path to the q point of the road 1200. 1Please refer to the ® 5 input, the area where the two inductance elements l5〇, l37 are connected to the plane, 1000 The area on the upper side (the area of the oblique line in Fig. 5A) divided by the area on which the film line I37 is thrown onto the plane (the area enclosed by the broken line in Fig. 5A) is, for example, greater than 0.5 ' or, for example, greater than 〇·8, or For example, it is substantially equal to ι. In addition, the opening 142 of the protective layer 140 exposes the area of the thin film line 137 (the area marked with a diagonal line in FIG. 5A) such as being greater than 3 〇 planes greater than 8 〇, _ gradual, or such as greater than Outside, the area where the two inductive elements 150, 137 are connected ( 5A middle-hatched area) the extended distance projected onto the plane 1000 (the distance from the path 12〇〇&v point to the point w in Figure 5A) is, for example, greater than 500 microns, or such as greater than 8 microns, or For example, referring to FIG. 4 and FIG. 5, in electrical transmission, one of the electronic components 112 in the semiconductor chip (8) (for example, the electronic component 112a) is adapted to output an electronic signal, the electronic signal. After passing through the thin film circuit layers 132 and 134, the film 212 can be transferred to the thin film line 137, the thick metal line 150, and the substrate 200, and then transferred to other electronic components in the semiconductor wafer 1 via the thin film wiring layers 134 and 132. At least one of 112 (such as electronic component 112b); at this time, the thin film line 137, the thick metal line 150 and the line 212 of the substrate 200 can be used for signal transmission in the semiconductor wafer. In addition, the electronic signal can be transmitted to the substrate 200 after being transferred to the film line 137, the thick metal line 15 and the 1301647 line 212 of the substrate 2; at this time, the film is thick and thick metal lines! The line 212 of the substrate 200 and the substrate 200 can also be used for signal transmission of H13曰7, 刚+ and substrate 2 曰1. In addition, the substrate is also suitable for = an electronic signal, which is transmitted to the substrate 212 and the semiconductor wafer 1 〇〇 = the metal line 150 and the thin film line 137, and then transferred to the semiconductor wafer via the thin film wiring layers 134, 2 At least - electronic components m (such as sub-elements 112a and 112b). In addition, in terms of electrical transmission of the bumps 160, the semiconductor wafer 1 can be pulled through the bumps 160 to transmit electronic signals to the substrate 2 (8), or the electronic signals transmitted from the substrate 200 can be received through the bumps. As described above, the thin film line nr outer shunt 212 of the semiconductor wafer 1 can be connected to the thin film line 137 and the substrate 2 〇〇 $ 2 = 12 in addition to the horizontal signal 150 of the electronic signal, so that at least the electron can be added. The cross-sectional area of one of the transmission paths of the signal can improve the transmission quality of the electronic signal. The difference is that the semiconductor wafer 100 is disposed on the polysilicon layer (10). Referring to FIG. 4, the semiconductor wafer 100 is formed after the thick metal line 150 and the bump layer 136. The thickness h of the bump 160 is, for example, approximately 5=2, and 150. The thickness [and the metal layer structure 'thickness h' of the bump 160 is thick: 150 metal layer structure 'where the bump 160 rhododendron A, and the thickness j of the metal line is, for example, greater than 1 micrometer, in the preferred case, For example, the system is larger than 5 microns. FIG. 5 'after forming the protective layer 140' also forms a pattern Ί::1 on the protective layer 140, the thickness of the polymer layer 180 is kb 糸; 1 micron, and the material of the polymer layer 180 is, for example, polyamine. 15 1301647 ^olyimide 'PI), phenylcyclobutene (bcB), polyaryl ether (parylene), porous dielectric material or elastomer. The polymer sound 180 has an opening 182 exposing the top film layer 136 of the top layer, including exposing the film line 137. Then, a thick metal line and a bump 160 are formed on the thin film wiring layer 136±, wherein the thickness h of the bump 160 protruding from the outside of the opening 182 of the polymer layer (10) is substantially the same as that of the protruding layer 180, for example. The thickness of the thick metal line 15〇 outside the opening 182, and the gold structure of the convex 16〇 is the same as the metal layer of the thick metal line ,%, wherein the protrusion protruding beyond the opening 182 of the polymer layer 180 The thickness of the block 16 is, for example, greater than 1 micron, and preferably, for example, greater than 5 microns, the thickness of the thick metal line 15 outside the opening 182 of the protruding polymer layer 180 is, for example, greater than 1 micron. In preferred cases, such as greater than 5 microns. Referring to FIG. 4 and FIG. 5, after the thick gold line 150 and the bump 160 of the semiconductor wafer 1 are fabricated, the bonding step may be performed, so that the thick metal line 15 of the semiconductor wafer 100 can be directly connected to the substrate 2 The bumps 212' and the bumps 16 of the semiconductor wafer 1 can be connected to the pads 214 of the substrate 200 in direct contact. Next, a polymer layer 17 may be filled between the semiconductor wafer 100 and the substrate 200, and the polymer layer 17 is coated around the thick metal line 150 and around the bump 160. 2. The thick metal line of the semiconductor wafer and the circuit of the substrate are used as the signal transmission between the semiconductor wafer and the substrate. Please refer to FIG. 6 to FIG. 9 , which illustrate another type of negative wafer structure according to the first embodiment of the present invention. The semiconductor wafer 100 of FIG. 6 to FIG. 9 is the same as the semiconductor wafer 100 of FIG. 2 to FIG. 5, and the substrate 200 of FIG. 6 to FIG. 9 is identical to the substrate 200 of FIG. 2 to FIG. The details are different here; the difference is that the thick metal line 15 of the semiconductor wafer and the line 212 of the substrate 2 are only used as the signal transmission between the semiconductor wafer 100 and the substrate 200, and not as 16 1301647. The signal transmission in the semiconductor wafer 100 is as follows. Referring to FIG. 6 and FIG. 7, one of the electronic components 112 in the semiconductor chip 1 (for example, the electronic component U2a) is adapted to output an electronic signal through the thin film circuit layer. 132, 134, 136 pass through the protective layer 140, and then transferred to the thick metal line 15 () of the semiconductor wafer loo and the line 212 of the substrate 200, and then transferred to the substrate 2A; at this time, the semiconductor wafer 100 The thick metal line 150 and the line 212 of the substrate 200 can be used for signal transmission between the semiconductor wafer 100 and the substrate 200. In other implementations, the substrate 200 is also adapted to output an electronic signal, which is transmitted to the line 212 of the substrate 200 and the thick metal line I% of the semiconductor wafer 1 , and then passes through the protective layer 140 of the semiconductor wafer 100, and The at least one electronic component 112 (such as the electronic component 112a) in the semiconductor wafer 1 is transferred via the thin film wiring layers 136, 134, 132. Referring to FIG. 8 and FIG. 9, one of the electronic components 112 in the semiconductor wafer 1 (for example, the electronic component U2a) is adapted to output an electronic signal through the thin film circuit layer. After 132 and 134, the circuit 212 is transferred to the thin film line 137, the thick metal line 150 and the substrate 200, and then transferred to the substrate 200. At this time, the thick metal line 150 of the semiconductor wafer 1 and the line 212 of the substrate 200 are It can be used for signal transmission between the semiconductor wafer 1 and the substrate 200. In other implementations, the substrate 200 is also adapted to output an electronic signal, which is transmitted to the line 212 of the substrate 200 and the thick metal line 1% of the semiconductor wafer 1 and the thin film line 137, and then through the thin film wiring layers 134, 132. At least one electronic component 112 (such as electronic component 112 &) within the semiconductor wafer 100 is transferred. Referring to FIG. 6 to FIG. 9 , in terms of electrical transmission of the bumps 160 , the semiconductor wafer 100 can transmit electronic signals to the substrate 2 through the bumps 160 or can be received by the substrate 200 through the bumps 160 . Electronic signal. 17 1301647 After the thick metal line 150 of the semiconductor wafer 100 and the substrate 200 are used for lateral transmission of the electronic signal, it can also serve as a longitudinal transfer between the substrate and the substrate 200. Since the semiconductor chip is connected to the Langxian County board, the thick metal line 150 of the m 100 can be used for a large area of the electric offif line 212, so that the performance of the electrical connection between the semiconductor wafers can be greatly increased, and the noise can be reduced. The production.

Or a ground-sink mr paste line and a substrate transfer system source bus line 10 to FIG. 13 , which is a cross-sectional view showing another embodiment of the first embodiment of the present invention, wherein FIG. 10 to FIG. The semiconductor wafer 1 of the 13 is similar to the semiconductor wafer 1 of FIG. 2 to FIG. 5, and the substrate of FIG. 1 to FIG. 13 is identical to the substrate 200 of FIG. 2 to FIG. 5, and details are not described herein again. The only difference is that the thick metal lines 15 〇 of the semiconductor wafer and the substrate are used as a power bus or ground bus, as described below. Referring to FIG. 13 to FIG. 13, when the thick metal line 15 of the semiconductor wafer 1 and the line 212 of the substrate 200 are used as a power bus, the thick metal line 150 of the semiconductor wafer and the line 212 of the substrate 200 are, for example. The power busbar 135 is electrically connected to the semiconductor wafer J00, for example, provided by the thin film circuit layer 134, and is also electrically connected to the power busbars in the substrate 2A. Since the thick metal line 15 of the semiconductor wafer 100 is connected to the circuit 212' of the substrate 2 in a large area in direct contact and electrically connected to the power bus 135 in the semiconductor wafer 100, the power bus of the semiconductor wafer 100 can be reduced. 135 The degree of voltage change due to signal interference, and the semiconductor wafer 1〇〇 can provide a relatively stable power supply voltage. " Or, in other implementations, the thick metal line 150 of the semiconductor crystal and the line 212 of the substrate 200 are electrically connected to the power supply 1301647 of the semiconductor wafer 1 , L row = 5 ' but However, an electrical disconnection occurs between the lines in the substrate 2A. W,, and FIG. 10 to FIG. 13 'When the line 212 of the thick metal line 150 si厪*0 of the semiconductor wafer 100 is used as the ground bus, the semiconductor wafer 100: =, , , the path 150 and the line 212 of the substrate 200 For example, the grounding busbar 135 is electrically connected to the semiconductor, such as provided by the thin film circuit layer 134, and is connected to the grounding busbar in the substrate 2A. Since the semiconductor wafer-formed thick metal line 150 is connected to the substrate 200 in a large-area direct contact, and the turtle is connected to the ground bus 135 in the semiconductor wafer 100, the ground bus 135 of the semiconductor wafer 1GG is received by the signal. The degree of dryness and the degree of semiconductor wafers can provide a relatively private pressure. Alternatively, the thick metal line 150 of the semiconductor wafer 100 and the base U-line 212 are electrically connected to the semiconductor wafer, and the electrical lines between the lines in the substrate 2 and the substrate 2 are electrically disconnected. The thick metal circuit of the ϋ conductor chip is used for signal transmission in the wire board, and is used for the power bus or ground bus of the substrate, and the moon ^ ", 囷 14 and FIG. 15 ' A cross-sectional view of another package of the first embodiment of the present invention, wherein the semiconductor wafer of FIG. 14 and FIG. 15 is a semiconductor wafer of FIG. 2 and FIG. 3, and the substrate of FIGS. 14 and 15 20 (H-ray is the substrate of Figure 2 and Figure 3, and will not be described here; but the difference is that the thick metal line (9) of the semiconductor wafer (8) is excited by the semiconductor wafer, the circuit layers 132, 134, 136 is in a state of electrical disconnection, and the semiconductor chip contacts the thick metal line 150 and the line 212 of the substrate 200 as the signal transmission in the substrate 2, or as the power supply of the substrate 2 For the use of row or ground busbars, as follows: = Figure 14 and Figure 15, when the thick metal line of the semiconductor wafer - [, the line 212 of the soil board u 00 is used as the signal transmission in the substrate 2" , an electronic signal is suitable for transmission and substrate transmission via the substrate to the substrate

(S 19 1301647 2 The thick metal line 150 of the wafer 100 is transferred to the substrate via the substrate 212 and the thick metal line 150 of the semiconductor wafer 100. Then, the electronic signal is not transmitted to the circuit. The thick metal line 150 of the semiconductor wafer 100 is directly transferred to the semiconductor wafer 1 via the line 212 of the substrate 2QQ. As described above, the thick metal line 15 of the semiconductor wafer 1 and the line 212 of the substrate 2 (8) may serve only as a substrate. The electronic signal transmission in the 2 〇〇 is not used for the signal transmission in the semiconductor wafer or as the signal transmission between the semiconductor wafer and the substrate 200. The 150 series directly contacts the line 212 of the substrate 2, so that the thick metal line 150 of the semiconductor wafer 100 can electrically connect the line 212 of the substrate 2 to a large area, so that the electrical transmission quality of the electronic signal can be increased. Referring to FIG. 14 and FIG. 15, when the thick metal line 15 of the semiconductor wafer 100 and the line 212 of the substrate 200 are used as the power supply bus of the substrate 200, the semiconductor crystal The thick metal line 丨5〇 of the sheet 100 and the line 212 of the substrate 2 are suitable for electrically connecting the power busbars in the substrate 200, wherein the thick metal lines 150 of the semiconductor wafer and the power source in the semiconductor wafer 100 An electrical disconnection is formed between the bus bars. Since the thick metal lines 15 of the semiconductor wafer are directly connected to the circuit 212 of the substrate 200 and electrically connected to the power busbars in the substrate, the substrate 200 can be reduced. The power busbar is subjected to voltage variations due to signal interference, and the substrate 2〇〇 can provide a relatively stable power supply voltage. ', Please refer to FIG. 14 and FIG. 15, when the semiconductor wafer 1 is thick metal line 15〇 When the line 212 of the substrate 200 is used as the ground bus bar of the substrate 200, the thick metal line 150 of the semiconductor wafer 100 and the line 212 of the substrate 2 are suitable for electrically connecting the ground bus bars in the substrate 200, wherein the semiconductor wafer 1〇〇 The thick metal line 150 and the ground bus in the semiconductor wafer 1 are electrically disconnected. Since the thick metal line 15 of the semiconductor wafer 100 is directly connected Contacting the ground 212 of the substrate 130 and electrically connecting to the ground busbar in the substrate 2, for example, to reduce the voltage of the grounding busbar of the substrate 2〇 due to signal interference. To the extent that the substrate 2〇〇 can provide a relatively stable ground voltage. 5. Metal Layer Structure of Thick Metal Circuit and Substrate Line of Semiconductor Wafer Referring to Figure 16, there is shown a cross-sectional view showing one of the metal layer deposition structures of the thick metal lines of the semiconductor wafer in the first embodiment of the present invention. The thick metal line 150 of the semiconductor wafer 1 includes an underlying metal layer 1511 and a top metal layer 1516, and the underlying metal layer 1511 is directly formed on the protective layer 140, for example (FIG. 1, FIG. 2, FIG. 6, Figure 1A and Figure 14), on the polymer layer 18〇 (as shown in Figures 3, 7, 11 and 15) or on the top film line 137 (Figure 4, Figure 5, Figure 8, As shown in FIG. 9 , FIG. 12 and FIG. 13 , the top metal layer 1516 is located on the underlying metal layer 1511 , wherein the material of the underlying metal layer 1511 is, for example, a titanium alloy, a titanium nitride compound, a group or a nitro compound. The material of the top metal layer 1516 is, for example, gold, and the thickness of the top metal layer 1516 is "for example, greater than 1 micrometer, and in a preferred case, for example, greater than 5 micrometers. In addition, the bumps of the semiconductor wafer 1 are also The metal layer structure as shown in FIG. 16 may be the same as that of the thick metal line 15A. Referring to FIG. 17, a metal layer stacking structure of a thick metal line of a semiconductor wafer in the first embodiment of the present invention is illustrated. Schematic diagram of the cross section. The aforementioned semiconductor wafer 100 The metal line 150 includes, for example, an underlying metal layer and a top metal layer 1526, and the top metal layer 1526 is positioned on the underlying metal layer 152i, wherein the underlying metal layer 1521 is formed, for example, by an adhesion/barrier layer 1522, a copper layer. The layer 1523, a nickel layer 1524 and a gold layer 1525 are formed, and the adhesion/barrier layer 1522 is directly formed on the protective layer 14 (for example, as shown in FIG. 1, FIG. 2, FIG. 6, FIG. 10 and FIG. 14). , on the polymer layer 180 (as shown in Figure 3, Figure 7, Figure 丨丨 and Figure 15) or on the top film line 137 (Figure 4, Figure 5, Figure 8, Figure 9, Figure 21, 1301647 i ^ 13 The copper layer 1523 is formed on the adhesion/barrier layer 1522, and the layer is on the copper layer 1523. The gold layer 1525 is the material of the adhesive layer/block layer 1522, such as titanium or titanium. The crane alloy m or the nitrogen compound, or the adhesion/barrier layer 1522 can also be formed by the == and the gold layer, wherein the chrome-copper alloy layer is "the top layer of the metal layer is formed on the underlying metal layer 1521. The material of the layer metal layer 1526 is, for example, tin-lead alloy, tin-bismuth, tin-silver, and the thickness j2 of the top metal layer 1526, such as it is not, in the preferred case, For example, the system is larger than 5 microns. In addition, the bumps 160 of the wafer 100 may also have a metal layer structure as shown in FIG. 17 in association with the thick metal lines 15 . A schematic cross-sectional view of a metal layer stacking structure in the circuit of the substrate in the first embodiment of the present invention is shown in Fig. 18'. The circuit 2 η of the substrate 2 includes, for example, a bottom gold and a top metal layer (4), and a top metal layer, which is located on the underlying metal layer, wherein the underlying metal layer is made of a copper layer 2112 and a nickel. The layer 2113 is formed. The copper layer 2112 is, for example, tied to the insulating layer of the substrate 200, and the nickel layer 2113 is positioned on the copper layer 2112. The top metal layer 2116 is positioned on the nickel layer 2113 of the underlying metal layer 2111, and the material of the top metal layer 2116 is, for example, gold. In addition, the pads 2 of the substrate 2 may also have a metal layer structure as shown in FIG. 18 of the line 212_ of the substrate 200. Ming Shenguan 19' is a schematic cross-sectional view showing a metal layer stacking structure of the substrate in the first embodiment of the present invention. The substrate 212 of the substrate 2 includes, for example, an underlying metal layer 2121 and a top metal layer 2126. The top metal layer 126 is located on the underlying metal layer 2121, wherein the underlying metal layer 2121 is formed, for example, by a copper layer/ 2122, a nickel layer 2123 and a gold layer 2124, the copper layer 2122 is, for example, on the insulating layer of the substrate 2, the nickel layer 2123 is on the copper 22 1301647 layer 2122, and the gold layer 2124 is in the nickel layer. On layer 2123. The top metal layer 2126 is fastened to the gold layer 2124 of the underlying metal layer 2121, and the top metal ^ 2126 is made of solder of tin boat alloy, tin, tin silver alloy or tin silver copper alloy. 2126 may be formed on the gold layer 2124 of the underlying metal layer 2121 by electroplating, for example, or the top metal layer 2126 may be cured by a lean solder through a reflow step, that is, by using a screen printing method. A cream solder (not shown) is formed on the gold layer 2124 of the underlying metal layer 2121 of the substrate 2, and then the thick metal 15 of the semiconductor wafer 100 can be connected to the cream solder, followed by reflow soldering. The step of forming a solid solder 2126 on the gold layer 2124 of the underlying metal layer 2121, such that the solder 2126 can be connected to the thick metal line 15 of the semiconductor wafer 1 and the gold layer 2124 of the underlying metal layer 2121 of the substrate 2 . In addition, the pads 2 of the substrate 2 may have the same metal layer structure as shown in FIG. 19 as the lines 212 of the substrate 200. Referring to Fig. 20, there is shown a cross-sectional view showing a metal layer stacking structure of a substrate line in the first embodiment of the present invention. The substrate 2<2> of the substrate 2 includes an underlying metal layer 2131 and a top metal layer 2136, and the top metal layer 2136 is tied to the underlying metal layer 2131, wherein the underlying metal layer 2131 comprises, for example, copper. On the insulating layer of the substrate 200. The material of the top metal layer 2136 is, for example, tin-lead alloy, tin, tin-silver alloy or tin-silver-copper alloy solder, wherein the top metal layer 2136 can be formed on the underlying metal layer 2131 by means of electric ore; for example, the top metal The layer 2136 may also be formed by curing the cream solder through the reflow step, that is, the solder can be formed by screen printing (not shown) on the underlying metal layer 2131 of the substrate 2, and then the semiconductor. The thick metal line 15 of the wafer 100 can be connected to the cream solder, and then a solid solder 2136 can be formed on the underlying metal layer 2131 via the reflow process, so that the solder can be connected to the semiconductor wafer 1 through the solder 2136. 23 1301647 belongs to the underlying metal layer 2131 of the line 150 and the substrate 2 . In addition, the pads 214 of the substrate 200 may have the same metal layer structure as shown in the circuit 212 of the substrate 2. In the present invention, the connection manner of the thick metal line 150 of the semiconductor wafer 100 and the line 212 of the substrate 200 can be roughly divided into two mechanisms. The first type is a gold-gold/sa-bonding method, that is, a semiconductor wafer. The material of the top metal layer of the thick metal line I% is gold, and the material of the top metal layer of the line 212 of the substrate 200 is also gold. When the semiconductor wafer 1 is bonded to the substrate 200, the semiconductor wafer is The top metal layer of the thick metal line 150 of 100 can be connected to the top metal layer of the line 212 of the substrate 2 through gold-gold eutectic bonding. For example, the thick metal line U0 of the semiconductor wafer 100 has the structure shown in FIG. The metal layer structure, the line 212 of the substrate 200 has a metal layer structure as shown in FIG. 1S, in which case the material of the top metal layer 1516 of the thick metal line 15 of the semiconductor wafer 100 and the top metal layer 2116 of the thin line 212 of the substrate The material is gold. When the thick metal line 150 of the semiconductor wafer is bonded to the line 212 of the substrate 200, the top metal layer 1516 of the thick metal line 150 of the semiconductor wafer is utilized by the gold-gold alloy. The top metal layer 212 of the wiring substrate 200 ^ 2116 then engage said square. The second type of soldering is the solder bonding method, that is, the material of the top layer metal layer of the semiconductor wafer 1 is thick. The material of the top metal layer is solder. When the semiconductor wafer (10) and the board 200 are bonded, the semiconductor wafer is discussed. The top layer of the thick metal line (9) can be connected to the substrate line 2ΐ2 by solder bonding. Example 2, the structure of the semiconductor wafer 1 厚 thick metal line 150

Alternatively, the material of the top metal layer of the line 212 of the substrate 200 may be the conductor 曰: 厚, the thick metal line 15 of the sheet 100, and the slab layer of the metal layer as shown in FIG. @200层金24 1301647 is a coating material. When the semiconductor wafer 100 is bonded to the substrate 200, the thick metal lines 15 of the semiconductor wafer can be joined to the top metal layer of the substrate 212 by solder bonding. For example, the circuit 212 of the substrate 2 has a metal layer structure as shown in FIG. 20 or FIG. 20, and the material of the top metal layer -2126 or 2136 of the line 212 of the substrate 2 is solder, when the semiconductor wafer is used. When the thick metal wire 15 15 is bonded to the line 212 of the substrate 200, the thick metal line 150 of the semiconductor wafer 1 is bonded to the substrate 2 2 126 or 2136 by solder bonding, if it is a semiconductor wafer. The thick metal line 15 is as thick as the gold layer of the top metal layer 1516. In the preferred case, the top metal layer 2126 or 2136 of the line 212 is, for example, thick.

Alternatively, the material of the top metal layer of the line 212 of the thick metal line 15G-^ of the semiconductor wafer may be the same as that of the substrate, and the metal layer may be soldered. The method of connecting the substrate path 15 (for example, the thick metal wire of the semiconductor wafer 100 and having the metal layer structure as shown in the 'the metal line structure of the substrate 200' has a metal layer as shown in FIG. 19 or FIG. Structure =; = the material of the top metal layer 1526 and the thickness of the wire = the thickness of the h h H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H湓t The thick metal line (9) may be in direct contact with the thick metal line 350 of the thick metal wire conductor 300 of the same side and the substrate path 15 in addition to the above-mentioned side of the substrate path 15 < S ) 1301647 Ϊίϊ 'As shown in FIG. 21 to FIG. 47, the structure and material of the semiconductor wafer 100 are described in detail in the implementation of the semiconductor wafer 100, and the cup material is here. In the figure, there are several implementation possibilities: the interconnection of the two thick metal lines of the semiconductor chip and the semiconductor chip is used as the signal transmission in one of the semiconductor wafers. Please refer to FIG. 21 and FIG. 22 first, wherein FIG. 21 A cross-sectional view of a wafer assembly mounted on a first semiconductor wafer in accordance with a second embodiment of the present invention, wherein the cross-sectional portions of the thick metal lines of the two semiconductor wafers are cut perpendicularly along the extension path of the two thick metal lines, respectively. A cross-section of the corresponding semiconductor wafer is obtained; FIG. 22 is a cross-sectional view showing the wafer structure after the bonding of the two semiconductor wafers in FIG. Referring to FIG. 21, the semiconductor wafer 300 includes a semiconductor substrate 31, a plurality of thin film dielectric layers 322, 324, and 326, a plurality of thin film wiring layers 332, 334, and 336, and a protective layer 340. The semiconductor substrate 31 has a plurality of electronic components 312 ′. The electronic components 312 are disposed on a surface layer of one of the active surfaces 314 of the semiconductor substrate 31 , wherein the semiconductor substrate 310 is, for example, a germanium substrate, and is doped with pentavalent or trivalent ions. For example, boron ions or phosphorus ions are used to form a plurality of electronic components 312 on the surface of the semiconductor substrate 31. The electronic components 312 are, for example, metal oxide semiconductors or transistors. A plurality of thin film dielectric layers 322, 324, 326 may be formed on the active surface 314 of the semiconductor substrate 310 by means of chemical gas deposition, wherein the thin film dielectric layers 322, 324, 326 are, for example, oxygen oxide compounds, nitrogen oxides. Each of the thin film dielectric layers 322, 334, and 336 is disposed on one of the thin film dielectric layers 322, 324, and 326, and the material of the thin film wiring layers 332, 334, and 336 includes aluminum, for example. , copper or enamel. The thin film dielectric layers 322, 324, 326 have a plurality of via holes 321, 323, 325, and the thin film wiring layers 332, 334, 336 can be electrically connected to each other by the via holes 321 , 323 , 325 of the thin film dielectric layers 322 , 324 , 326 . The connection is made and electrically connected to the electronic component 312. 26 1301647 The protective layer 340 is disposed on the thin film dielectric layers 322, 324, 326 and the thin film wiring layers 332, 334, 336, wherein the thickness Z of the protective layer 340 is, for example, greater than 〇35 μm, and the structure of the protective layer 34〇 For example, it is a composite layer of a nitrogen arsenide compound layer, an oxonium compound layer, a phosphorous silicate glass layer or at least one of the above materials. The protective layer 340 has a plurality of openings 342 that expose the thin film wiring layer 336 located on the top layer. The thick metal line 350 is disposed on the protective layer 340 and electrically connected to the thin film wiring layer 336 via the opening 342 of the protective layer 340, wherein the thick metal wiring 35 is thicker than the thickness of the thin film wiring layers 332, 334, and 336. The pad 360 is substantially aligned with the opening 342 of the protective layer 340 and electrically connected to the thin film wiring layer 336. In the manufacturing process, the thick metal line 350 and the interface 360 can be completed simultaneously by the same process, so the thick metal line 350 and the pad 36 can have the same metal layer structure, and the thick metal line 350 and the pad 36 are The metal layer structure will be described in detail later, skipped here first. It should be noted that the thickness J of the thick metal line 350 is substantially the same as the thickness 接 of the pad 36 Η, wherein the thickness J of the thick metal path 350 and the thickness η of the pad 36 比如 are, for example, greater than i μm. In the best case, for example, the system is larger than 5 microns. In the form of a line, the thick metal lines 150, 350 of the two semiconductor wafers may be respectively extended in the direction of the semiconductor wafer, such as a straight line extending form, curve in any direction. The extended form or the extended path with discontinuous concave portions. In a preferred case, the conductive metal wafers (10), the thick metal lines 15G, 35() may be thick metal lines 350 of the scale semiconductor wafer. Referring to FIG. 22', after the two semiconductor wafers 100, 300 are provided, the step of bonding can be performed 'so that the thick metal lines (9) of the semiconductor wafer can be directly contacted to connect the thick metal lines 35 of the semiconductor wafer, and the semiconductor 27 1301647 The bumps 160 of the wafer 100 can be directly connected to the pads 360 of the semiconductor wafer. Then, a polymer layer 17 can be filled between the two semiconductor wafers 1 and 300, and the polymer layer 170 is wrapped around the thick metal lines 150 and 35, and the bumps 160 and the pads are also covered. Around 360. A plane is defined that is substantially parallel to the active surface n4 of the semiconductor substrate 110, wherein the area of the junction of the two thick metal lines 150, 350 is projected onto the plane 1000 such that the distance s is greater than 500 microns, or for example greater than 8 inches. Micron, or for example greater than 1200 microns; the area of the two thick metal lines 150, 350 connected to the plane 1000 is, for example, greater than 30, _ square microns, or such as greater than 80,000 square microns, or such as greater than (8) square microns . In this embodiment, the connection relationship between the thick metal lines 15 〇 and 350 of the semiconductor wafers 100 and 300 is the same as the connection relationship between the thick metal lines 150 of the semiconductor wafer 1 (10) and the line 212 of the substrate 200 in the first embodiment. For a more detailed description, reference may be made to the embodiment in which the thick metal line 150 of the semiconductor wafer and the line 212 of the substrate 200 are the inductive elements in the first embodiment. For the connection relationship between the thick metal lines 15 〇 and 35 半导体 of the semiconductor wafers 100 and 300 in this embodiment, please refer to FIG. 22, in the electrical transmission, the electron 兀f 112 in the semiconductor wafer 1 〇〇 One of them (for example, electronic component 112a) is adapted to output an electronic signal 'this electronic signal passes through the thin film circuit layers 132, 134, 136 and through the protective layer 140, and then to the thick metal lines 15 〇, 35 〇 And then passed through the thin film circuit layer 136, 134, 132 to at least one of the semiconductor wafers 1 〇 〇 112 (for example, the electronic component iub), and thereafter, the semiconductor wafer 1〇 The thick metal line 15 is transported from the electronic component 112a to the thick metal line 28 1301647 150, 350, and can also be transferred into the semiconductor wafer 3, for example, through the protective layer 340 and through the film. The circuit layers 336, 334, 332 are transferred to the electronic component 312a; at this time, the thick metal line 15 of the semiconductor wafer 100 and the thick metal line 350 of the semiconductor wafer 3 can also serve as the two semiconductor wafers 1 and 3 Use. In addition, referring to FIG. 22, one of the electronic components 312 in the semiconductor chip 3 (such as the electronic component 312a) is also adapted to output an electronic signal, which is passed through the thin film circuit layers 332, 334, and 336. After the protective layer 14 is turned over,

Transfer to the thick metal lines 350, 150, and then through the protective layer 140 of the semiconductor wafer 1 and through the thin film wiring layers 136, 134, 132 to at least one electronic component 112 within the semiconductor wafer 1 (such as Electronic component 112a 112b)

As described above, the thick metal lines 15 of the semiconductor wafer 100 and the thick metal lines 350 of the semiconductor wafer 30 can be used as the lateral transmission between the two semiconductor wafers 100, 300 in addition to the lateral transmission of the electronic signals. Since the thick metal line i50 of the semiconductor wafer 100 is directly connected to the thick metal line 350 of the semiconductor wafer 300, the thick metal line of the semiconductor wafer 1 can be electrically connected to the thick metal of the semiconductor wafer 3 by a large area. The line 350 can greatly increase the performance of the electrical connection between the two semiconductor wafers, and can reduce the generation of noise. In addition, referring to FIG. 22, the semiconductor wafer 1 can transmit electronic signals to the semiconductor wafer 300 through the bumps 16 of the semiconductor wafer 1 and the pads 360 of the semiconductor wafer 300, or can be received by the semiconductor wafer 3. The electronic signal from the 。. In FIGS. 21 and 22, thick metal lines 150, 350 are formed directly on the protective layers 140, 340, respectively; however, the thick metal lines 150, 350 may also be formed on the protective layers 140, 340, respectively. On the layer; or, 29 1301647 can also be thick metal lines 35 〇 formed on the polymer layer on the protective layer 34 厚 thick metal lines 15 〇 line directly formed on the protective layer 14 ;; or, can also be thick metal The line 15 is formed on the polymer layer on the protective layer 14〇: and the thick gold, the line 35 is directly formed on the protective layer 34〇, as shown in FIG. 23, which shows the first embodiment of the present invention. Another cross-sectional view of the wafer structure. Here, only the embodiment in which the thick metal line of one of the above is disposed on the polymer layer is not shown, and other structures not shown in the thick metal line disposed on the polymer layer can be configured in the thick metal line of FIG. The structure on the aggregate (4) and so on. Referring to FIG. 23, a polymer layer 180 is formed on the protective layer 14A. The polymer layer 180 has a plurality of openings 182 substantially aligned with the openings 142 of the protective layer 14'. The thick metal lines 150 are formed in the polymerization. The layer 18 is on the top layer and is connected to the film via the opening 182 of the polymer layer I80 and the opening 142 of the protective layer 14〇: the wiring layer 136. The thick metal line 350 is formed in direct contact on the protective layer 340^ and via The opening 342 of the protective layer 340 is connected to the thin film wiring layer 336. It is noted that the thickness h of the bump 16 which protrudes beyond the opening 182 of the polymer layer 18 is, for example, substantially the same as in the polymer layer 18 The thickness j of the thick metal line 150 is thick, and the thick metal line 15 〇 and the bump 16 () have the same metal layer structure 'the thickness h of the bump 160 protruding from the opening 182 of the polymer layer 18 与The thickness j of the thick metal line 15〇 on the polymer layer 18〇 is, for example, greater than 1 micrometer, and preferably, for example, greater than 5 micrometers. The thickness k of the polymer layer 180 is, for example, greater than 1 micrometer, and The material of the polymer layer 180 is, for example, a poly P〇lyimide (PI), benzocyclobutene 'BCB, polyaryl ether (paryiene), porous dielectric material or elastomer, etc. In Figures 21 to 23, thick metal lines 150, 350 through a small opening 142, 342 of the protective layer 140, 340 small area connection of the top film circuit layer 30 1301647 136, 336, however, thick metal lines 15 〇, 35 〇 can also pass through 40, 340 The large opening σ 142, 342 is connected to the top layer of the thin layer ^ = 6, 336, including the following possible implementations. The first implementation situation: thickness = line 150 is a small area to connect the top layer _ film circuit layer. 136 gold% 〇 The thin film circuit layer is connected to the top layer in a large area; the second embodiment of the thick metal line 150 is a thin film connecting the top layer of the film, the circuit layer η/thick metal line 35, and the thin film layer of the top layer is connected to the top layer. As shown in FIG. 24 and FIG. 25; the third embodiment: the thick metal circuit (9) and the current thin film circuit layers 136 and 336 are connected to the top layer in a large area, as shown in FIG. The second implementation scenario and the third implementation scenario are not In the first embodiment, the thick metal lines of FIGS. 24 to 27 can be connected to the structure of the thin film wiring layer of the top layer in a large area, and so on. Referring to FIG. 24 to FIG. 27, in the semiconductor wafer, the top layer The film circuit layer 136 has a film line 137, and the opening 142 of the protective layer 14 exposes the film line 137 over a large area, so that the thick metal line 15 〇 can connect the film exposed by the opening 142 of the protective layer 140 over a large area. Line 137. A plane 1000' this plane 1〇00 is substantially parallel to the surface of the semiconductor substrate ιι 114. The area where the thick metal line 150 is connected to the film line 137 is projected onto the plane 1 除 divided by the film. The ratio of the area on the line 137 is, for example, greater than G.5, or such as ^ or, for example, substantially equal to one. The opening 142 of the protective layer 14 暴露 exposes the area of the thin film line 137, for example, greater than 30,000 square microns, or such as greater than 80, 〇〇〇 square microns, or such as greater than 15 〇, 〇〇〇 square microns. The region where the thick metal line 150 is connected to the thin film wiring layer 136 is projected to the plane 1 and the extended distance t is, for example, greater than 500 micrometers, or such as greater than 8 micrometers or greater than 1200 micrometers. In the present embodiment, the connection relationship between the metal chip 150 and the thin film line 37 of the semiconductor wafer 1 shown in FIGS. 24 to 27 is the same as that shown in FIGS. 4 to 5 in the first embodiment. The connection relationship between the thick metal lines of the semiconductor wafer 100 and the film lines 137, as described in more detail, can refer to the thick metal lines 15 of the semiconductor wafer 100 exemplified in the first embodiment. The thin line 137 is an embodiment of an inductor element. If the description is made with reference to this part, a clearer understanding of the connection relationship between the thick metal line 15 of the semiconductor wafer 100 and the film line 137 in this embodiment will be provided. In addition, in addition to the thick metal line 150 being able to connect the top film layer 136 over a large area, the thick metal line 350 can also be connected to the thin film line layer 336 in a large area, as shown in Figs. 26 and 27. The top film line 336 has a thin film line 337, and the opening 342 of the protective layer 340 exposes the thin film line 337 over a large area, so that the thick metal line 350 can connect the thin film line exposed by the opening 342 of the protective layer 340 over a large area. 337. A plane 1050 is defined which is substantially parallel to the active surface 314 of the semiconductor substrate 31, and the area of the area where the thick metal line 350 is connected to the thin film line 337 is projected onto the plane 1050 divided by the film line 337 projected onto the plane. The ratio of the area on the 1〇5〇 is, for example, greater than 0.5, or such as greater than 〇8, or such as approximately equal to 1. The opening 342 of the protective layer 340 exposes the area of the thin film line 337, for example, greater than 30,000 square microns, or such as greater than 8 Å, 〇〇〇 square micron, or such as greater than 150,000 square microns. The area of the thick metal line 35A connected to the thin film wiring layer 336 is projected onto the plane 1050 by an extension T, for example, greater than 500 microns, or such as greater than 8 microns, or greater than 1200 microns. The connection relationship between the thick metal line 350 and the thin film line 337 of the semiconductor wafer 300 shown in FIG. 26 and FIG. 27 in this embodiment is the same as that of the semiconductor wafer shown in FIGS. 4 to 5 in the first embodiment. The connection relationship between the thick metal line 15〇 and the film line 丨37, for a more detailed description, refer to the thick metal line 15〇 and the film line 137 of the semiconductor wafer 100 exemplified in the first embodiment 32 1301647. For the embodiment of the inductive component, if the description of this section is referred to, a clearer understanding of the connection relationship between the thick metal line 350 of the semiconductor wafer 300 and the thin film trace 337 in the present embodiment will be provided. Referring to FIG. 24 and FIG. 25, one of the electronic components 112 in the semiconductor chip 1 (for example, the electronic component 112a) is adapted to output an electronic signal via the thin film circuit layer 132. And 134, passing to the film line 137 and the thick metal lines 150, 350, and then transmitting to at least one of the other electronic components I} in the semiconductor wafer 1 via the thin film wiring layers 134, 132 (for example, electronic Element 112b); at this time, the thick metal line 150 of the semiconductor wafer 100 and the thick metal line 35 of the semiconductor wafer 300 can be used for signal transmission in the semiconductor wafer 100. In addition, the electronic signal can be transmitted to the semiconductor wafer 300 after being transferred from the electronic component 112a to the thin film wiring 137 and the thick metal wiring 15〇, 35〇, for example, through the protective layer and through the thin film wiring layers 336, 334, 332 is transmitted to the electronic component 312a; at this time, the thick metal line 150 of the semiconductor wafer 100 and the thick metal line 350 of the semiconductor wafer 3 can also be used for signal transmission between the semiconductor wafers 1 and 3. In addition, referring to FIG. 24 and FIG. 25, one of the electronic components 312 (such as the electronic component 312a) in the semiconductor chip 3 is also adapted to output an electronic signal via the thin film circuit layers 332, 334. And 336 is transmitted through the security layer 340 to the thick metal lines 350, 150 and the thin film line 137, and then transmitted to the at least one electronic component 112 (such as an electron) in the semiconductor wafer 1 via the thin film wiring layers 134, 132. Elements ii2a, 112b). 24 differs from FIG. 25 in that the semiconductor wafer 1 is provided with a polymer layer 180 on the protective layer 140. The structure of the semiconductor wafer 100 of FIGS. 24 and 25 is similar to that of the first embodiment. 4 and the structure of the semiconductor 33 I3〇l647 of the semiconductor chip of Fig. 5, will not be described here. FIG. 26 and FIG. 27 'In the electrical transmission, one of the semiconductor wafers 〇Q-two το 112 (for example, the electronic component U2a) is adapted to rotate the electronic signal, the electronic signal Via the thin film wiring layers 132, 134, it is transferred to the j film line 137, the thick metal lines 15A, 350, and the thin film line 337, and then transferred to the other of the semiconductor wafers 1 / 2 by the thin film wiring layers 134, 132. At least one of the sub-elements 112 (such as the electronic component 112b); at this time, the thick metal line 150 of the semiconductor wafer 100 and the thick metal line 350 of the semiconductor wafer 3 can be used for signal transmission in the semiconductor wafer 1 . In addition, the electronic signal can be transferred to the semiconductor wafer after being transferred from the electronic component 112a to the thin film line 137, the thick metal lines 150, 350 and the thin film line 337, for example, via the thin film wiring layers 334, 332 to the electronic component 312a. At this time, the thick metal line 150 of the semiconductor wafer 100 and the thick metal line 350 of the semiconductor wafer 3 can also be used for signal transmission between the two semiconductor wafers 1 and 3. In addition, referring to FIG. 26 and FIG. 27, one of the electronic components 312 in the semiconductor wafer 300 (such as the electronic component 312a) is also adapted to output an electronic signal. The electronic tiger is transmitted to the film via the thin film circuit layers 332 and 334. Lines 337, thick metal lines 350, 150, and thin film lines 137 are then transferred via thin film line layers 134, 132 to at least one electronic component 112 (such as electronic components 112a, 112b) within semiconductor wafer 1 . 26 is different from FIG. 27 in that the semiconductor wafers ι, 3 配置 have the polymer layers 180, 380 disposed on the protective layers 14 〇 340, wherein the semiconductor wafer 100 of FIGS. 26 and 27 has a structure. The structures of the semiconductor wafer 100 of FIGS. 4 and 5 in the first embodiment are omitted, and will not be described again. Referring to FIG. 26, after the protective layer 34 is formed on the semiconductor wafer 300, a thick metal line 350 and a pad 360 are simultaneously formed on the thin film circuit layer 336 34 1301647, wherein the thickness H of the pad 360 is substantially the same as The thickness J of the thick metal line 350, and the metal layer structure of the pad 360 is substantially the same as the metal layer structure of the thick metal line 350, wherein the thickness η of the pad 360 and the thickness J of the thick metal line 350 are greater than 丨. Micron, in preferred cases, such as greater than 5 microns. However, referring to FIG. 27, after the protective layer 34 is formed, the semiconductor wafer 300 is further patterned to form a polymer layer 38 on the protective layer 34, and the thickness K of the polymer layer 380 is greater than 丨 micron, for example. The polymer layer is, for example, polyimide (PI), benzene, benzocyclobutene 'BCB, polyarylene ether, porous electrical material, or elastomer. The polymer layer 38A has an opening 382 that exposes the top film layer 336 of the top layer, including exposing the film line 337. Then, the thickness of the thick metal line 350 and the pad 36 can be simultaneously formed on the film circuit layer, wherein the thickness of the pad 36 protruding from the opening 382 of the polymer layer 380 is substantially the same as that of the polymer. The thickness of the ^if ί 外 outside the opening 382 of the object layer 38 且 and the metal layer structure of the pad 36 (four) is substantially the same as the metal layer structure of the thick metal line 350, wherein the pads protruding beyond the polymer layer · = opening 382 The thickness η of 360 is, for example, greater than i micrometers, such as greater than 5 micrometers in the lower layer; the thickness of the thick metal wiring 35G protruding beyond the opening 382 of the polymer layer; for example, if the system is greater than ^, for example, the system is larger than 5 micron. Two-thick metal lines interconnected by a flat-yield μ ^ half-body wafer are used for signal transmission between two semiconductor chips. Please refer to FIG. 28 to FIG. 33, which is a second embodiment of the present invention. A schematic cross-sectional view of another 2 wafer structure, wherein the semiconductors of the semiconductor wafers of FIG. 28 to the circle of the semiconductor M mnrwn + body day slices 28 to 33 are similar to those of FIGS. 22 to 27 respectively. Semiconductor wafer double, 3 5 1301647 will not be repeated here; the only difference is that the thick metal lines 150, 350 of the semiconductor wafers 100, 300 are only used for signal transmission between the two semiconductor wafers 1 and 3, and not as the semiconductor wafer 100. For the signal transmission, as described below, referring to FIG. 28 and FIG. 29, one of the electronic components 112 in the semiconductor wafer 1 (for example, the electronic component n2a) is suitable for outputting one in electrical transmission. The electronic signal is transmitted through the thin film circuit layers 132, 134, and 136 and through the protective layer 140, and then transferred to the thick metal wires of the semiconductor wafer 1 and 3, =0, 350, and then passed through the semiconductor wafer. The protective layer 34 is transferred to one of the electronic components 312 (such as the electronic component 312a) in the semiconductor wafer 3 via the thin film wiring layers 336, 334, 332. Alternatively, the electronic component 312 in the semiconductor wafer 300 One of the components (such as the electronic component 312a) can also be adapted to output an electronic signal, which is transmitted to the semiconductor wafer via the thin film circuit layers 2, 334, and 336 and through the protective layer 340. 3〇〇, 1〇〇 thick metal lines 350, 150, then pass through the protective layer 140 of the semiconductor wafer 1 and are transferred to the electronic components in the semiconductor wafer via the thin film wiring layers ι36, 134, 132 One of the 112s (for example, the electronic components 112 &) is at this time, the thick metal lines 150, 350 of the semiconductor wafers 100, 300 are used for signal transmission between the semiconductor wafers 100, 300. Referring to Figures 30 and 31, In electrical transmission, one of the electronic components 112 in the semiconductor wafer 1 (such as the electronic component 112a) is adapted to output an electronic signal, and the electronic signal is transmitted to the thin film circuit 137 via the thin film wiring layers 132, 134 and The thick metal lines 150, 350 of the semiconductor wafer 1 , 3 , then pass through the protective layer 340 of the semiconductor wafer 300 and are transferred to the electronic components 312 in the semiconductor wafer 300 via the thin film wiring layers 336, 334, 332. One of them (such as electronic component 312a). Alternatively, one of the components 312 in the semiconductor wafer 300 (such as the electronic component 3i2a) may also be adapted to rotate an electronic signal through the thin film wiring layers 332, 334, 336 and through the 36 1301647 overprotective layer. After 340, it is transferred to the semiconductor wafer 300, the thick metal lines 350, 150 and the thin film line 137, and then transferred to one of the electronic components 112 in the semiconductor wafer 100 via the thin film wiring layers 134, 132 (such as electronic components). 112a). At this time, the thick metal lines 15 of the semiconductor wafers 1 and 300 are used for signal transmission between the semiconductor wafers 100 and 300. One of them (such as electronic component 112a). At this time, 300 thick metal lines 15 〇, 35 〇 as a semiconductor cover, please refer to FIG. 32 and FIG. 33, in electrical transmission, one of the electronic components 112 in the semiconductor wafer 1 (such as the electronic component 112a) Is suitable for outputting an electronic signal transmitted through the thin film wiring layers 132, 134 to the thin film wiring 137, the thick metal wirings 15〇, 35〇 of the semiconductor wafers 1, 300, and the thin film wiring 337, and then via the thin film wiring Layers 334, 332 are transferred to one of electronic components 312 (such as electronic component 312;) within semiconductor wafer 300. Alternatively, one of the electronic components 312 within the semiconductor wafer 3 (such as the electronic component 312a) may also be adapted to output an electronic signal that is transmitted via the thin film wiring layers 332, 334 to the thin film wiring 336, the semiconductor wafer. 300, 100 thick metal lines 35, please and film line 137, then = film line layers 134, 132 are transferred to the semiconductor chip 100 within the semiconductor wafer 1 chip, between the sheets 100, 300 as described above, Semiconductor wafer 100,

37 1301647 The conductor wafer is finely connected, and the semiconductor wafer (10) can transfer the value t to the semiconductor wafer or can receive the electronic signal transmitted from the semiconductor wafer 3〇0. ^ Connected two thick metal lines are used as a power bus or ground bus. Referring to Figures 34 to 39, there is shown a cross-sectional view of another type of wafer assembly in accordance with a second embodiment of the present invention, wherein The semiconductor wafer 1 of FIGS. 34 to 39 is the same as the semiconductor wafer 1 of FIG. 22 to FIG. 27, respectively, and the semiconductor wafer 3G0 of FIG. 34 to the same is the semiconductor wafer of FIGS. 22 to 27, It will not be described here; the only difference is that the thick metal line 150 \350 of the semiconductor wafer touch is used as a power bus or ground bus, as described below. Referring to FIG. 34 to FIG. 39, when the thick metal lines 150 and 350 of the semiconductor wafers 100 and 3 are used as power supply busbars, the semiconductor wafers 1 and the thick metal lines 150 and 35 (the M series are electrically connected to The semiconductor wafer 1 braided power bus 135 is provided, for example, by a thin film wiring layer I%, and is also electrically connected to a power bus 335 within the semiconductor wafer 300, such as provided by a thin film wiring layer 334. The thick metal circuit of the cymbal 100 is connected to the thick metal line 35 of the semiconductor wafer 300 in a large area in direct contact, and is electrically connected to the power bus bars 135 and 335 in the semiconductor wafer 1 and 300, thereby reducing the semiconductor. The power supply busbars 135, 335 of the wafers 100, 300 are subjected to voltage variations due to signal interference, and the semiconductor wafers 1 and 3 can provide a relatively stable power supply voltage. "Please refer to FIG. 34 to FIG. 39. When the thick metal lines 150 and 350 of the semiconductor wafers 100 and 300 are used as ground bus bars, the thick metal lines 150 and 350 of the semiconductor wafers 1 and 3 are electrically connected to the semiconductor. The ground busbar 135' within the chip 1 is, for example, provided by the thin film wiring layer 134, and is also electrically connected to the ground busbar 335 within the semiconductor wafer 300, such as provided by the thin film wiring layer 334. 38 1301647 The thick metal line 150 of the semiconductor wafer 100 is connected to the metal line 350 of the semiconductor wafer 300 in a large area by direct contact, and is electrically connected to the ground bus bars 135 and 335 in the semiconductor wafer 100, 300, so that the semiconductor crystal chip can be reduced. The grounding busbars 135 and 335 of 1〇0 and 3〇〇 are subjected to voltage variation due to signal interference, and the semiconductor wafers 1 and 300 can provide relatively stable ground voltage. 〜4·2 semiconductor wafers are mutually Connected two thick metal lines are used as one of the half-signal transmissions in the conductor wafer. Referring to Figures 40 to 43, there are shown schematic cross-sectional views of another type of wafer assembly in accordance with a second embodiment of the present invention, wherein 40 is the same as the semiconductor wafer 100 of FIG. 22, and the semiconductor wafer 100 of FIG. 41 and FIG. 43 is the same as the half of FIG. The semiconductor wafer 300 of FIG. 4 and FIG. 41 is the same as the semiconductor wafer 300 of FIG. 22, and the semiconductor wafer 300 of FIG. 42 and FIG. 43 is identical to the semiconductor wafer 300 of FIG. The difference is that the thick metal line 15 of the semiconductor wafer and the thin film wiring layers 132, 134, and 136 in the semiconductor wafer 100 are electrically disconnected, and the semiconductor wafer 100, 300 The thick metal lines 15 and 350 are used for signal transmission in the semiconductor wafer 300 as described below. Referring to FIG. 40 to FIG. 43, when the thick metal of the semiconductor wafers 1 and 300 and the channels 150 and 350 are used for signal transmission in the semiconductor wafer 3, one of the electronic components 312 in the semiconductor wafer 300 is used. (for example, the electronic component 312a) is adapted to output an electronic signal, which is transmitted through the protective layer 340 via the thin film wiring layers 332, 334, and 336, and then transferred to the thick metal wiring 350 of the semiconductor wafer 3, (10), 150, then passing through the protective layer 34A, and transmitted to at least one of the other sub-components 312 (such as the electronic component 312b) in the semiconductor wafer 300 via the = film wiring layer 336, 334, 332; wherein the electron The signal is not transmitted to the semiconductor wafer lion via the semiconductor wafer 300, the thick metal line 35〇, 39 1301647. At this time, the thick metal line 35 of the semiconductor wafer line (9) and the material wafer 3〇0 can be used for signal transmission in the semiconductor wafer 3 (8), and is not used for the transmission of the semiconductor wafer. It is also used for signal transmission between 1 and 3 of semiconductor wafers. Since the thick metal line W of the semiconductor wafer 100 is in direct contact with the thick metal line 350' of the body wafer 300, the thick gold line 150 of the semiconductor wafer 1 can electrically connect the thick metal line of the semiconductor wafer 3 to a large area. 350, this can increase the electrical transmission quality of the electronic signal. And the two-thick metal circuit of the semiconductor chip is used as a power bus or ground bus of one of the semiconductor chips. Referring to FIG. 44 to FIG. 47, the first embodiment of the present invention is illustrated. FIG. 44 and FIG. 46 are semiconductor wafers of FIG. The wafer 100, and the semiconductor wafer 300 of FIG. 4 and FIG. 41 are identical to the semiconductor wafer 3 of FIGS. 34 to 37. The semiconductor wafer 300 of FIG. 42 and FIG. 41 is identical to the semiconductor of FIGS. 38 and 39. The wafer 3 is not described here; however, the difference is that the thick metal line 15 of the semiconductor wafer surface and the thin film wiring layers 132, 134, and 136 in the semiconductor wafer 100 are electrically disconnected. Further, the thick metal lines 15 〇 and 35 半导体 of the semiconductor wafers 100 and 3 are used as power supply bus bars or ground bus bars of the semiconductor wafer 300 as described below. Referring to FIG. 44 to FIG. 47, when the thick metal line 15 of the semiconductor wafer 100 is used as the power bus of the semiconductor wafer 300, the thick metal lines 150 and 350 of the semiconductor wafer 1 are suitable for electrical connection. The % source busbar 335' of the semiconductor wafer 3 is supplied, for example, by a thin film wiring layer 334 of a semiconductor wafer 3?q, wherein the thick metal lines 150, 350 of the semiconductor wafer 1〇〇, 3〇〇 A 1301647 ^ open circuit is formed between the power bus and the power bus in the semiconductor wafer. Since the thick metal line 35 (4) of the semiconductor contact is directly connected to the thick metal line 35 of the semiconductor wafer 300 and electrically connected to the power bus 335 in the semiconductor wafer 300, the power of the semiconductor chip 3 can be reduced. The bus bar 335 is generated by signal interference, and the semiconductor wafer 300 can provide a relatively stable electric current. Referring to FIG. 44 to FIG. 47, when the semiconductor wafer is just a thick metal line 15 as a semiconductor wafer. When the grounding busbar of 300 is used, the semiconductor wafers and the thick metal wires 15G and 35G are suitable for electrically connecting the grounding busbars 335 of the semiconductor wafers. The grounding busbars 335 are, for example, the thin film wiring layers 334 of the semiconductor wafers 3 (9). Provided, in which the semiconductor wafer is just gold, the metal, the semiconductor wafer, and the grounding busbar of the semiconductor wafer is formed. Since the thick metal line 150 of the semiconductor wafer is directly connected to the semiconductor wafer, the semiconductor wafer is directly contacted. The thin thick metal line 350, and electrically connected to the ground bus 335' of the = can be shouted less semiconductor wafers No disturbance generates a voltage varying degree 'can be alkylene and the semiconductor wafer 300 to provide more stable the ground voltage.

6. The metal layer structure of the two thick metal lines of the interconnected semiconductor wafers - in the embodiment, the metal layer of the semiconductor wafer _ thick metal line MO as shown in FIG. 16 or FIG. 17 A schematic cross-sectional view of one of the metal layer stacking structures of the semiconductor wafer 3 in the second embodiment of the present invention. The half-thick thick metal line 350 includes, for example, an underlying metal layer 3511 and a ΐ: Ϊ23516, and the underlying metal layer 3511 is formed directly on the protection layer 图0 i?l zn FIG. 21 to FIG. 25, FIG. 28 to FIG. 31, FIG. As shown in Fig. 37, Fig. 1, =1, Fig. 44 and Fig. 45) or the top film line 3 (Fig. 27, Fig. 32, Fig. 33, Fig. %, Fig. %, Fig. 42, Fig. 43, Figure 1301647 = 47 No) 'The top metal layer 3516 is in the underlying metal layer. Upper: The material of the second middle layer gold ^| layer 3511 is, for example, Titanium alloy, titanium nitride, and a group of nitrogen compounds, and the top metal layer 3516 is made of gold, 9 metal layer 3516. The thickness J1 is, for example, greater than 1 micron, and in the preferred case 'such as greater than 5 microns. Further, the pad of the semiconductor wafer 3 may have a metal layer structure as shown in Fig. 48 which is the same as the thick metal line 350. Please refer to item 49, which shows a schematic cross-sectional view of one of the metal layer stacking structures of the semiconductor wafer·=metal line 350 in the second embodiment of the present invention. The thick metal line 35 of the half-body wafer 300 includes, for example, an underlying metal layer 3521 and a top metal layer 3526. The top metal layer 3526 is positioned on the underlying metal layer 3521, wherein the underlying metal layer 3521 is bonded or resisted, for example. The barrier layer 3522, a copper layer 35=3, a nickel layer 3524 and a gold layer 3525 are formed, and the adhesion/barrier layer 3522 is formed directly on the protective layer 340, for example (FIG. 21 to FIG. 25, FIG. 28 to FIG. 31: FIG. 34 to FIG. 37, FIG. 40, FIG. 41, FIG. 44 and FIG. 45) or the top film line 337 (FIG. 26, FIG. 27, FIG. 32, FIG. 33, FIG. 38, FIG. 42. FIG. 43, FIG. 46 and FIG. 47), a copper layer 3523 is formed on the adhesion/barrier layer 3522, a nickel layer 3524 is formed on the copper layer 3523, and a gold layer 3525 is formed on the nickel layer 3524. The material of the adhesion/barrier layer 3522 is, for example, titanium, titanium tungsten alloy, titanium nitride compound, button or nitrogen compound, or the adhesion/resistance layer 3522 may also be formed by sequentially depositing a chromium layer and a chromium-copper alloy layer. The chromium-copper alloy layer is located on the chromium layer. The top metal layer 3526 is formed on the gold layer 3525 of the underlying metal layer 3521, and the material of the top metal layer 3526 is, for example, solder of tin-lead alloy, tin, tin-silver alloy or tin-silver-copper alloy, and the top metal layer 3526 The thickness J2 is, for example, greater than 1 micron, and in the preferred case, such as greater than 5 microns. Further, the pads 36 of the semiconductor wafer 300 may have the same metal layer structure as shown in Fig. 17 as the thick metal lines 350. In the present invention, the thick metal lines 15 〇, 35 〇 42 1301647 of the semiconductor wafers 100, 300 can be roughly divided into two mechanisms, the first type is a gold-gold conjugate interface, that is, the semiconductor wafer i 〇〇,细之,^ ==== (4) If the shirt, - ίίϊΐίi, the top metal layer of the line 150 can be connected to the semiconductor wafer through the gold-gold combination = a thick 3 _ The thick metal line 150 has a thick metal line 350 as shown in Fig. H 48 (5) 300, and has a thick metal line 150 of the semiconductor wafer (10) and a top metal of the thick metal line 350 of the semiconductor wafer 300. + Conductor Day 300 300 thick metal line 35〇 joint, metal line 15〇 top metal layer 151 total = semi-conducting t-wafer, thick metal line 35〇 top metal layer Γ6 way to join Li Wei iTf system The way the tan is bonded is that the material of the semiconductor wafer is thicker than the material of the metal layer of the θ metal layer. When the semiconductor wafer is 300, the top metal layer of the thick metal line 150 of the chip 100 can be体 semiconductor wafer body wafer 300 Thick metal lines 350. For example, when the thick metal lines 350 of the dies 300 are joined, the thickness of the semiconductor wafer 100 is entirely 线. The top metal layer is bonded to the semi-conductive 2f dry metal line 350 by solder bonding. If the thick thickness of the semiconductor wafer 300 is 35, the thickness of the top metal layer is as shown in Fig. 48, and the thickness of the thick metal line 15 of the semiconductor wafer 10 is thick. Even _ riding. The 敎 layer may, for example, be a top layer of a thin metal line 35G of a semiconductor wafer, a gold foil, a 1301 647 f 1 = a silicon wafer, and a 30 Å junction, a thick metal 半导体 of the semiconductor body wafer 300. The way to connect the semi-conducting qnn * @ a wide-line metal layer of the 350 line. For example, the semiconductor wafer conductor 曰H line 350 has a metal layer structure as shown in Fig. 49, and a thick metal line 35 of t3°° at half time. The material of the top metal layer 3526 is S = Zhao =. !, 0, 3 ° 0 thick metal line 15 °, 35. == Conductor Crystal 300 is a line 150 that is joined by a solder joint to the top metal layer 3526 of the thick metal line 350. If the semiconductor system is thick, it is not shown, the top metal layer 1516 嫱 Γ Γ layer, in the preferred case, the 'thick metal of the semiconductor wafer 3 ' 、 、 、 、 、 The thickness is very high on the tin layer. And 350 is a semiconductor wafer (10), a thick metal line of 3GG, and a material of the genus tf, and the semiconductor wafers 100, 3 (8) are in the thick metal line of the semiconductor wafer 100. The method is to connect the thick metal of the semiconductor wafer coffee === 曰 metal layer. For example, the gold=wire line shown by the semiconductor wafer 17 has a thick metal line 35 〇 构 构 构 构 , , , , , , , , , , , , , , , , , , , , , , , , , , , , The material of the top layer j layer 3526 of the thick metal line 350 of the two lithographic wafers 300 is made of squama. When the semiconductor wafer _, the lion line 150, 350 is joined, the top layer metal layer i of the semiconductor wafer is utilized. The top metal layer 3526 of the metal line 350 is bonded by solder bonding. +¥体曰曰片3〇0 Thick t wafer construction of the third real %^ In the above embodiment, the semiconductor wafer 100 thick metal 魄 150 150 150 150 150 150 150 150 150 As described in the embodiment, either the thick metal line 35q of the other semiconductor wafer 3GG is directly connected, as described in the second embodiment 1301647. However, the application of the present invention is not limited thereto, and the thick metal line 15 of the semiconductor wafer may be electrically connected to a circuit connecting member 4 through the conductive layer 450 containing the polymer 452 and a plurality of metal particles. The circuit 412, as shown in FIG. 5A to FIG. 54, wherein the structure and material of the semiconductor wafer 1 are described in detail in the first embodiment, and will not be described again, and the circuit connecting member 4〇〇 For example, any shape, semiconductor wafer or substrate. In this embodiment, the circuit connecting member is, for example, a glass substrate. Generally, the circuit layer 41 of the glass substrate 400 is formed, for example, by a transparent oxide oxide. In the actual shed, the circuit layer includes, for example, a line. 412 and pad 414. In the following description, there are several possible implementation scenarios: 1) The thick metal line of the semiconductor wafer and the circuit of the glass substrate are used as the signal transmission in the semiconductor wafer. Please refer to FIG. 50 and FIG. 51 first, wherein FIG. 50 shows A cross-sectional view of a semiconductor wafer and a glass substrate prior to assembly in accordance with a third embodiment of the present invention, wherein the cross-sectional portions of the thick metal lines cut through the semiconductor wafer are vertically cut along the extended path of the thick metal lines, respectively. FIG. 51 is a cross-sectional view showing the wafer structure of the semiconductor wafer in FIG. 50 after being bonded to the glass substrate. Please refer to FIG. 50' before the semiconductor wafer 1 is bonded to the glass substrate 4, such as an anisotropic conductive paste (ACP) or an anisotropic conductive film (ACF). The conductive layer 450 may be formed on the glass substrate 400 first, and is formed on the wiring 414 of the glass substrate 4 and the pad 414 of the glass substrate 400. The composition of the conductive layer 450 includes a polymer 452 and a plurality of metal particles 454, and the metal particles 454 are distributed in the polymer 452. In the form of a line, the line 412 of the glass substrate 400 may extend at the top of the glass substrate 400 in any direction, such as in a form that extends like a straight line, in the form of a curved extension, or an extension having a discontinuous concave portion. Road 45 1301647 Trail. In a preferred case, the thick metal line 150 of the semiconductor wafer 100 is in a mirror relationship with the line 412 of the glass substrate 400, so that the thick metal line of the semiconductor wafer 100 when the semiconductor wafer 100 and the glass substrate 400 are bonded. 150 can be aligned with the line 412 of the glass substrate 4 . In the case of the Bega, the thick metal line 150 of the semiconductor wafer 100 and the line 412 of the glass substrate 400 are, for example, spiral inductor elements, as shown in FIG. 50B, wherein FIG. 50A is the glass substrate 4 in FIG. A schematic plan view of a line projected onto a plane 1050; FIG. 5B is a plan view of the thick metal line 15 of the semiconductor wafer 100 of FIG. 5 projected onto a plane 1〇〇〇. Referring to FIG. 50A and FIG. 50B, the winding path of the inductive component 15A of the semiconductor wafer 1 and the winding path of the line 412 of the glass substrate 4 are in a mirror relationship, and the inductive component of the glass substrate 400 The 412 system extends along the path 11〇〇, for example, from the X point of the path 1100 to the γ point of the path 11〇〇, and the inductive element 150 of the semi-body plate 100 extends along the path 1200, such as from The X point of path 1200 extends to the point of path 12〇〇. Referring to FIG. 51, after the semiconductor wafer 1 and the glass substrate 400 are provided, a bonding step may be performed, so that the thick metal line 150 of the semiconductor wafer 1 can be pressed into the conductive layer 45 on the glass substrate 4? In the crucible, the thick metal line 150 of the semiconductor wafer 100 can be electrically connected to the metal substrate 454 of the conductive layer 45 电, and the bump 160 of the semiconductor wafer can pass through the conductive layer 450. The metal particles 454 are electrically connected to the pads 414 of the glass substrate 400. At this time, the polymer 452 of the conductive layer 450 may coat the periphery of the thick metal line 15〇 and the bump 16〇 of the semiconductor crystal 100. A plane 1000 is defined which is substantially parallel to the active surface 114 of the semiconductor substrate 11 , wherein the thick metal line 15 of the semiconductor wafer 00 and the line 412 of the glass substrate 4 are projected onto the overlapping area of the plane 1 〇〇〇 The extension distance [ratio (S) 46 1301647 is greater than 500 microns, or such as greater than 800 microns, or such as greater than 1200 microns; the thick metal line 15 of the semiconductor wafer and the line 412 of the glass substrate 4 The area of the overlap region projected onto this plane 1 比如 is, for example, greater than 30,000 square microns, or such as greater than 8 〇, 〇〇 () square microns, or such as greater than 150,000 square microns. In one embodiment, referring to FIG. 50A and FIG. 50B, when the inductive component 412 of the glass substrate 400 is bonded to the inductive component 150 of the semiconductor wafer 100 through the conductive layer 450, the A, B, and C of the inductive component 412 of the glass substrate 400. The D, E, F, and G regions respectively connect the a, b, c, d, e, f, and g regions of the inductor element 150 of the semiconductor wafer 1 through the conductive layer 45. Referring to FIG. 51A, a schematic plan view of the connection region of the inductive component 412, 15A of FIG. 50A and FIG. 50B after bonding is performed on the plane 1000, wherein the two inductive components, 412 are projected onto the overlapping area on the plane 1000. The extension distance (the area of the oblique line in Fig. 51A) (the distance of the path 1200 extending from the X point to the y point) is, for example, greater than a curse, a micrometer, or, for example, greater than 800 micrometers, or, for example, greater than 12 micrometers, The area of the overlapping regions (the areas marked with diagonal lines in FIG. 51A) projected by the inductive elements 150, 412 onto the plane 1 比如 is, for example, greater than 3 〇, 〇〇〇 square micron, or, for example, greater than 80,000 square microns, or for example More than 15 〇, (8) 〇 square micron. Referring to FIG. 51, in electrical transmission, one of the electronic components 112 in the semiconductor chip 1 (such as the electronic component n2a) is adapted to output an electronic signal via the thin film circuit layers 132, 134, After passing through the protective layer 140, the 'transmission to the thick metal line 15〇 and the glass substrate 4〇〇 is then passed over the protective layer 140 and transferred to the semiconductor wafer 1 via the thin film wiring layers 136, 134, 132. At least one of the other electronic components 112 (such as the electronic component 112b); at this time, the thick wiring 150 of the semiconductor wafer and the wiring 412 of the glass substrate can be used as the transmission of the semiconductor wafer. . In addition, the electronic signal can be transmitted to the glass substrate 4 after being transferred from the electronic component 112a to the thick metal line 150 and the line 412 of the glass substrate 400. At this time, the thick metal line 15 of the semiconductor wafer 100 The line 412 with the glass substrate 4 can also be used for signal transmission between the semiconductor wafer 100 and the glass substrate 4. On the electrical transmission of the bumps 160, the semiconductor wafer 1 can transmit the electronic signals to the glass substrate 4 through the bumps 160, or can receive the electronic signals transmitted from the glass substrate 400 through the bumps. As described above, the thick metal line 15 of the semiconductor wafer and the line 412 of the glass substrate 400 can be used as a lateral transmission between the semiconductor wafer 100 and the glass substrate 400 in addition to the lateral transmission of the electronic signal. The thick metal line 150 of the wafer 100 is connected to the line 412 of the glass substrate 400 through the conductive layer 450, thereby greatly increasing the performance of the semiconductor wafer: the electrical connection between the stomach 1 and the glass substrate 400, and Reducing noise = production, production of the above-mentioned electronic signal electrical transmission 'semiconductor wafer 1 thick metal line 150 and glass substrate 400 line 412 for the signal transmission in the semiconductor wafer 1 At the same time, it is used for signal transmission between the semiconductor wafer 1 and the glass substrate 4. However, the application of the present invention is not limited thereto, and the semiconductor wafer 100 The thick metal line 150 and the line 412 of the glass substrate 400 can also be used as a signal transmission in the semiconductor wafer 100, and not as a signal transmission between the semiconductor wafer 1 (8) and the glass substrate 400. 412 is in a state of electrical disconnection with other lines in the glass substrate 400. In other embodiments, the glass substrate 400 may also be adapted to output two electronic signals, which are transmitted to the line 412 of the glass substrate 400 and the thick metal line 15 The protective layer 140 is then passed through the semiconductor wafer 100 and transferred to at least 48 1301647 112 (such as the electronic components 112a and 112b) in the semiconductor wafer via the thin, 136, 134, 132. In Figures 50 and 51 The thick metal line 15 is formed directly on the protective layer 4; however, the thick metal line 15 can also be formed on the polymer layer 18G on the protective layer 'as shown in FIG. 52', which is depicted in accordance with the present invention. A cross-sectional schematic view of another wafer assembly of the third embodiment, in which the position and material of the polymer layer are described in detail in the first embodiment, will not be described here. 0 to 52, the thick metal line 15 is connected to the thin film circuit layer 136 of the top layer through the small opening 142 of the protective layer 14; however, the thick line 15 can also be transmitted through the protective layer 14 The large-area, "top-layered thin film wiring layer 136' of the opening 142 is shown in Figs. 53 and 54 and is a cross-sectional view showing another form of wafer construction in accordance with a third embodiment of the present invention. The connection relationship between the thick metal lines 15A and _ lines 137 of the semiconductor wafer shown in the present invention is the same as that of the thick metal lines 150 and the thin film lines of the semiconductor wafer 100 shown in Fig. 4 of the first embodiment. 137 connections _ 'more detailed description of the side, can refer to the first; = 匕 的 的 semiconductor wafer 1 厚 thick metal line 15 〇 and film line = system for the example of the article It is to be understood that the connection relationship between the thick metal line 15 半导体 of the semiconductor wafer and the film line printing is only more clearly understood. Referring to FIG. 53 and FIG. 54, in the electrical transmission, one of the semiconductor wafers (such as the electronic component 112a) is adapted to rotate a dice signal, and the electronic signal passes through the thin film wiring layer 132. After 134, the second transmission to the film line m, the thick metal line (10) and the glass substrate can be transmitted to at least one of the other electronic components 112 in the semiconductor wafer 1 via the thin film circuit layers 134, 132 ( For example, the electronic component mb) 'At this time' the thin film line 137, the thick metal line 15 〇 and the glass base 4 犯 can be used as a signal miscellaneous in the semiconductor wafer 100. Only 49 1301647 outside 'this electronic signal can be transmitted to the glass substrate 4 (8) after being transferred to the film line 137, the thick metal line 150 and the glass-based/reverse 400 line 412; at this time, the film line 137, the thick metal line The line 412 between the 150 and the glass substrate 400 can also be used for signal transmission between the semiconductor wafer 100 and the glass substrate 400. In addition, the 'glass substrate 40 () is also suitable for outputting an electronic signal, which is transmitted to the glass substrate '400 line 4+12 and the semiconductor wafer 1's thick metal line 15〇 and the film line 137, and then through the thin film circuit layer. 134, 132 are transmitted to at least one electronic component U2 (such as electronic components 112a and 112b) within the semiconductor wafer 101. In addition, in terms of electrical transmission of the bumps 160, the semiconductor wafer 1 can transmit electronic signals to the glass substrate 400 through the bumps 16 or can be received by the glass substrate 4 through the bumps 160. As described above, the thin film line 137 of the semiconductor wafer, the thick metal line 150 and the line 412 of the glass substrate 400 can be used as a semiconductor wafer in addition to the lateral transmission of the electronic signal. The longitudinal transfer between the substrate 20 is: the thick metal line 150 is connected to the thin film line 137 and the line 412 of the glass-substrate 400 in a large area, so that at least the cross-sectional area of the transmission path of one part of the electronic signal can be increased, so Improving the transmission quality of the electronic signal. 2. The thick metal line of the semiconductor wafer and the circuit of the glass substrate are used as the signal transmission between the semiconductor wafer and the glass substrate. Figs. 55 to 58 show the third aspect according to the present invention. A cross-sectional view of another type of cymbal assembly of the embodiment, wherein the semiconductor wafers 1 of FIGS. 55 to 58 are respectively fabricated in half of the domain 2 of the first embodiment cap 2 The wafer substrate of the present invention is the same as that of the glass substrate 4 of FIG. 5 to FIG. The thick metal line 15〇 and the glass substrate 4〇〇 are only used for signal transmission between the semiconductor wafer and the glass substrate 4, and are not used for signal transmission in the semiconductor wafer 1 Referring to FIG. 55 and FIG. 56, in electrical transmission, one of the electronic components 112 in the semiconductor chip 1 (for example, the electronic component n2a) is adapted to rotate an electronic signal, the electronic signal. After passing through the thin film wiring layers 132, 134' 136 and passing through the protective layer 140, the thick metal lines 15 of the semiconductor wafer 1 and the wiring 412' of the glass substrate 400 are then transferred to the glass substrate ^qq; The thick metal line 150 of the semiconductor wafer 100 and the line 4U of the glass substrate 4 can be used for signal transmission between the semiconductor wafer 100 and the glass substrate 400. In other implementations, the glass substrate 400 is also suitable for outputting a battery. The signal is transmitted to the line 412 of the glass substrate 400 and the thick metal line 1 150 of the semiconductor wafer 1 , and then passes through the protective layer 14 半导体 of the semiconductor wafer 100 and transmitted to the semiconductor via the thin film wiring layers 136 , 134 , 132 . At least one electronic component 112 (such as electronic component 112a) in the chip 1 i i. Referring to FIG. 57 and FIG. 58, one of the electronic components 112 in the semiconductor wafer 1 is electrically transferred (for example, The electronic component 112a) is adapted to output an electronic signal, which is transmitted through the thin film circuit layers 132, 134 to the film line 137, the thick metal line 150 and the glass substrate 4, and then transmitted to the glass. In the substrate 400, the thick metal line 150 of the semiconductor wafer and the line 412 of the glass substrate 400 can be used for signal transmission between the semiconductor wafer 100 and the glass substrate 400. In other applications, the glass substrate 400 is also suitable for outputting an electronic signal, and is transmitted to the line 412 of the glass substrate 400 and the thick metal line 150 and the thin film line 137 of the semiconductor wafer 1 , and then through the thin film circuit layer 134 , 132 is transmitted to at least one electronic component 112 (such as electronic component 112a) in the semiconductor wafer 100. Please refer to FIG. 55 to FIG. 58 . In terms of electrical transmission of the bump 160 , the semiconductor wafer 100 can pass through the bump 160 . The electronic signal is transmitted to the glass substrate 4 (/, or the electronic signal transmitted from the glass substrate 400 can be received through the bump 160. 51 1301647 As described above, the semiconductor wafer is said to be a thick metal wire. ¥4_ The longitudinal transfer between the substrate and the substrate. Since the thick metal line 150 of the wafer is transmitted through the conductive layer 45, the wiring of 400 can greatly increase the efficiency of the semi-=== connection with the glass. And can reduce the production of _. The flow line or the line of the circuit and the glass substrate as a power source hui ί # 159 to Figure 62', which shows another schematic diagram according to the third embodiment of the present invention, wherein Figure 59 to Figure 62 The semiconductor wafer _ is not the same as the half of the second embodiment of FIG. 2 to FIG. 5 in the first embodiment. The glass substrate of the 5th #5G to w 54 is not described here, but only the rotating wafer 丨 (8) The thick 跋 150 and the line 412 of the glass substrate 400 are used as a power bus or sink, as described below. The claw is sharp and thin, as shown in Fig. 59 to Fig. 62 'When the thick metal line of the semiconductor wafer (9) /, the glass substrate When the line 412 of the 400 is used as the power bus, the thick metal line 150 of the semiconductor wafer and the line 412 of the glass substrate 400 are electrically connected to the power bus 135 of the conductor wafer, for example, by a thin film line. Layer 134: a power busbar for and 'electrically connected to the glass substrate 4 〇〇 β. Since the thick metal line 150 of the semiconductor wafer 100 is connected to the wiring 412 of the glass substrate 400 over a large area through the conductive layer 450, and Electrically connected to the power bus 135 in the semiconductor wafer 1 ,, this can reduce the degree of voltage change caused by the signal interference of the power bus bar U5 of the semiconductor wafer 1 , and the semiconductor chip 1 〇〇 can provide A relatively stable power supply voltage. Alternatively, in other implementations, the thick metal line 15 of the semiconductor wafer and the line 412 of the glass substrate 400 are electrically connected to the semiconductor wafer 1 52 52 1301647 = the platoon 135, but with the line in the glass substrate 4 呈现 电 广 广 广 % % % % , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , When the bus bar is grounded, the semiconductor wafer 〇〇 ί ί ί 15G and the glass substrate 412 are electrically connected to the ground bus 135 in the day 100, for example, by the thin film circuit layer 134 and also powered. The ground is connected to the ground bus bar in the glass substrate 400. Since the thick metal line 150 of the body wafer 100 is connected to the glass substrate 400 through the conductive layer 45, and is electrically connected to the ground in the semiconductor wafer hall, the row 135 can reduce the semiconductor wafer 1 The grounded bus bar 135 is subjected to voltage variations due to signal interference, and the semiconductor wafer 100 can provide a relatively stable ground voltage. Alternatively, in other implementations, the thick metal line 150 of the semiconductor wafer and the line 412 of the glass substrate 4 are electrically connected to the ground bus 135 of the semiconductor wafer 1 but with the glass substrate 4 The electrical lines between the wires in the crucible are electrically disconnected. 4. The thick metal circuit of the semiconductor wafer is used for signal transmission in the glass substrate or as the power bus or ground bus of the substrate. Please refer to FIG. 63 and 64, which is a cross-sectional view showing another type of wafer structure according to a third embodiment of the present invention, wherein the semiconductor wafers of FIGS. 63 and 64 are identical to the semiconductor wafers of FIG. 2 and FIG. 3, respectively. The glass substrate 400 of FIG. 63 and FIG. 64 is the same as the glass substrate 4 of the foregoing, and will not be described herein; however, the difference lies in the thick metal line 15 of the semiconductor wafer 100 and the semiconductor wafer. The film circuit layers 132, 134, and 136 in the 100 are electrically disconnected, and the thick metal line 150 of the semiconductor wafer and the line 412 of the glass substrate 4 are used as signals in the glass substrate 4 transmission Used, a glass substrate or a power bus or a ground bus 400 of purposes, as described below. 53 1301647 Referring to FIG. 63 and FIG. 64, when the thick metal line 15 of the semiconductor wafer 100 and the line 412 of the glass substrate 400 are used for signal transmission in the glass substrate 400, an electronic signal is suitable for passing through the glass substrate. The line 412 transferred to the glass substrate 4 and the thick metal line 15 of the semiconductor wafer 1 are transferred to the glass via the line 412 of the glass substrate 400 and the thick metal line 15 of the semiconductor wafer 100. The other lines of the substrate 400 are not directly transferred into the semiconductor wafer 100 via the line 412 of the glass substrate 400 and the thick metal line 150 of the semiconductor wafer 100. As described above, the thick metal line 150 of the semiconductor wafer and the line 412 of the glass substrate 400 can be used only for the electronic signal transmission in the glass substrate 400, and not for the signal transmission in the semiconductor wafer 1 or It is used for signal transmission between the semiconductor wafer 100 and the glass substrate 4. Since the thick metal line 15 of the semiconductor wafer 100 is connected to the line 412 of the glass substrate 400 through the conductive layer 450 over a large area, the electrical transmission quality of the electronic signal can be increased. Referring to FIG. 63 and FIG. 64, when the thick metal line 15c of the semiconductor wafer 1 and the glass substrate 412 are used as the power supply bus of the glass substrate, the thick metal line 15 〇 and the glass substrate of the semiconductor wafer The lion line 412 is adapted to electrically connect the power busbars within the glass substrate 4, wherein the thick metal lines 150 of the semiconductor wafer 100 are electrically disconnected from the power flow lines within the semiconductor wafer. Since the thick metal line (10) of the semiconductor wafer is connected to the glass substrate 4 through the conductive layer 45, the f is connected to the power bus in the glass substrate 400, thereby reducing the power supply of the glass plate. The busbar generates a voltage change due to signal interference, and the glass substrate 4GG can provide a relatively stable power supply voltage. Pangu = 63 and FIG. 64. When the semiconductor wafer is thick metal, the ground bus of the semiconductor wafer substrate 400 is connected to the metal line 150 and the glass substrate 400. The line 54 1301647 is suitable for electrically connecting the glass substrate. The ground bus bar of the 〇N, the thick metal line 15 of the 5 chip is electrically disconnected from the 33 rows of the semiconductor wafer 1 (). Since the thickness of the semiconductor wafer is 15=the line 412 of the glass substrate 4GG is connected to the glass substrate 4GG through the conductive layer 45G, the grounding busbar connected to the glass substrate 400 is connected to the grounding busbar in the glass substrate 400. The resulting knowledge 'and the glass substrate 400 can provide a relatively stable grounding. IV. Conclusion In summary, the wafer assembly and the process of the present invention can be directly connected to the circuit due to the half-body connection The line of the lining, the conductive layer of the chelating compound and the metal particles are connected to the circuit to connect the circuit of the thick metal line of the semiconductor chip and the circuit connecting member v'曰]. On the right side of the large-area electrically connected semiconductor chip, the thick metal line and the circuit connection age line _ as the job of the Saki, the circuit of the conductor track and the circuit connection component can provide a more stable signal transmission right area electrical connection The circuit of the thick metal line and the circuit connecting member of the semiconductor wafer is used as an electric surface or a flow (4), and the wiring of the semiconductor crystal line and/or the circuit connecting member can provide a relatively stable power supply voltage or ground voltage. Although the present invention has been disclosed above in the preferred embodiments, it is not intended to limit the invention, and any such person is not in the age and range of the female gamma. This is the definition of the scope of the patent application attached to the post. BRIEF DESCRIPTION OF THE DRAWINGS A cross-sectional view of a semiconductor TO sheet and a substrate before assembly is constructed in accordance with the first embodiment of the present invention. 1A is a plan view schematically showing a line 212 of a substrate 2 in FIG. 2 projected onto a plane 1〇5〇 55 1301647. To the plane reading butterfly _ dirty shadow joint 彳 ^ crystal, the first "real; the body wafer and the substrate and the substrate line _ as a rotating body (9) ^ job line diagram 2 Α, which shows Figure 1 Α and Figure 1 Β two The connected connection area is projected onto the plane _ on the plane _., Figure 5 Α shows the thick metal line field in Fig. 4 and Fig. 5 projected onto the plane touch _ (four) _., the 转 连接 之 构 ί ί ί Γ According to the present invention, the other type of wafer system is in accordance with the first embodiment of the present invention. Another type of wafer of the embodiment: the intention is 'the thick metal circuit of the semiconductor wafer is used as the substrate=the secret input is used for the electric ridge or the ground bus of the wire plate. 6 and 17 are shown in The first embodiment of the present invention is a schematic diagram of a metal layer stacking structure of a thick metal line of a semiconductor wafer. FIG. 18 to FIG. 20 respectively illustrate a metal layer stacking of a circuit of a substrate in the first embodiment of the present invention. Schematic diagram of the structure. The wafer assembly of the second embodiment of the conductor invention is arranged in a group like FIG. 22 to 27 is a schematic diagram showing the semiconductor wafer and the substrate of the second embodiment of the present invention, and the two-thick metal circuit in which the semiconductor crystals are connected to each other as a signal transmission in the rotating wafer. use.

S 56 1301647 type crystal line, between two semiconductor wafers = two cross-sections of interconnected two-thick metal sheet structure θ other than the m-type embodiment of the other-type crystal line system as a power bus or interconnected Two thick metal lines = two thick metals of its connection, one of the green layers 350, one of the metal layer stacking structure, the sound guide (four), the micro-channel of the glass, the secret of the glass substrate is the use of the video in the rotating wafer . _ Figure == Medium glass substrate injury f 5GB is a schematic plan view of the thick metal line 15 of the semiconductor wafer in Fig. 50 on the plane 1000. Figure 51A is a schematic plan view showing the connection area of the interface of the inductive elements 412, 150 of Figures 50A and 50B projected onto the plane 1000. 55-58 illustrate cross-sectional views of another type of wafer structure in accordance with a third embodiment of the present invention, wherein the thick metal lines of the semiconductor wafer and the glass substrate are used as signal transmission between the semiconductor wafer and the glass substrate. use. 59 to FIG. 62 are schematic cross-sectional views showing another type of wafer structure 57 1301647 according to a third embodiment of the present invention, wherein the thick metal line of the semiconductor wafer and the circuit of the glass substrate are used as a power bus or ground bus. . 63 and FIG. 64 are schematic cross-sectional views showing another embodiment of a wafer structure according to a third embodiment of the present invention, wherein the thick metal line of the semiconductor wafer is used for signal transmission in a glass substrate or as a power supply sink of the substrate. Used for row or ground bus. [Description of main component symbols] 1 〇〇: semiconductor wafer 110: semiconductor substrate 112, 112a, 112b · electronic component 114: active surface, 121, 123, 125: via holes 122, 124, 126: thin film dielectric layer 132, 134, 136: film circuit layer 135: power bus bar or ground bus bar 137: film line 140: protective layer 142: opening of protective layer 150 · thick metal line 160: bump 170: polymer layer 180: polymer layer 182: opening of polymer layer 200: substrate 210: wiring layer 212 · wiring 214: bonding pad 220: solder mask layer 300: semiconductor wafer 58 1301647 310 · semiconductor substrate 312, 312a, 312b: electronic component 314: active surface 321 , 323 , 325 : vias 322 , 324 , 326 : thin film dielectric layers 332 , 334 , 336 : thin film wiring layer 335 : power bus or ground bus 337 : thin film wiring 340 : protective layer 342 : opening of the protective layer 350: thick metal line 360: pad 380: polymer layer 382: opening of polymer layer 400: glass substrate - 410: wiring layer 412: line 414: pad 450: conductive layer 452: polymer 454: metal particle 1000 , 1050: surface 1100, 1 200: path 59

Claims (1)

1301647 [Application Scope] ------ 1. A wafer package comprising: a semiconductor wafer comprising: a stone substrate; a first dielectric layer positioned above the germanium substrate; a transistor, Positioned below the first dielectric layer; a first circuit layer on the first dielectric layer; a second circuit layer 'located above the first circuit layer, and the second circuit layer The material comprises copper; a second dielectric layer is disposed between the first circuit layer and the second circuit layer; a protective layer is disposed on the second circuit layer, and the protective layer is an inorganic material layer The inorganic material layer includes a nitrogen-containing compound; and a first metal layer is disposed on an upper surface of the protective layer and contacts the upper surface, and the first metal layer transmits a first layer in the protective layer a first contact of the opening contacting the second circuit layer and a second opening of the transparent layer contacting the second contact of the second circuit layer. The thickness of the first metal layer is greater than the first a circuit layer and a thickness of the second circuit layer are located on the upper surface The first metal layer has a thickness greater than 5 micrometers, and the transistor is located below the first metal layer, the first metal layer includes a titanium-containing metal layer and a first copper layer, wherein the titanium-containing metal layer Positioned on the protective layer, on the first contact, and on the second contact, and the first copper layer is on the titanium-containing metal layer; a hard plate is located on the semiconductor wafer Above, the hard board includes a plurality of third circuit layers, a plurality of insulating layers and a second metal layer, wherein the second metal layer comprises a first copper layer, a first nickel layer and a tin-containing metal layer. a nickel layer 1301647 is located between the two copper layers and the tin-containing metal layer, the second metal sound first metal layer connects the first contact and the second contact; and (c) passes the polymer a layer between the hard plate and the protective layer. 2. The wafer structure of claim 1, wherein the material of the A electrical layer comprises a nitrogen compound. The wafer according to the first aspect; wherein the wafer of the second dielectric layer item, wherein the inorganic material is first finely packed, wherein the nitriding point and the = Connected to the UrS ^ package, wherein the first sub-layer 2" is in the wafer structure described in the first item, wherein the titanium-containing gold 8 is as described in the patent application scope i, The electronic component output - the signal is g = j, and then transmitted to the other metal component of the semiconductor chip. The crystal + the input wheel of the patent range i is the __: Rolling out the wafer structure of the first item, wherein the hard conductor is crystallographically read and then transferred to the semimetal; the metal mi is the crystal of the first item, wherein the first 13 The wafer assembly of claim 1, wherein the first 1301647 metal layer further comprises a second nickel layer, and the second nickel layer is on the first copper layer. The wafer assembly of claim 1, wherein the first metal layer further comprises a second nickel layer and a gold layer, and the second nickel layer is On the first copper layer, the gold layer is on the second nickel layer. The titanium-containing layer includes titanium in which the tin is contained, wherein the tin is contained therein, wherein the tin is contained therein, wherein the tin is contained therein, wherein the second portion is 15. The metal layer of the wafer structure described in the first aspect of the patent is a qinghe alloy layer. 16. The metal layer of the wafer structure as described in claim 1 is a layer of a nitrogen compound. The wafer-forming metal layer of the first aspect is a tin-alloy layer. 18. The wafer-forming metal layer according to claim 1 is a tin layer. The wafer-forming metal layer is a tin-silver alloy layer. 20. The wafer-forming metal layer according to claim 1 is a tin-silver-copper alloy layer. 21. As described in claim 1 The wafer assembly metal layer is above the first metal layer. 22. A wafer package comprising: a semiconductor wafer 'including a chopped substrate; a first dielectric layer positioned above the germanium substrate a transistor positioned below the first dielectric layer as a first line a layer, a second circuit layer on the first dielectric layer, located above the first circuit layer, and the material of the second circuit layer comprises copper; a second dielectric layer is located at the first Between the circuit layer and the second circuit layer; 62 1301647 a protective layer on the second circuit layer, and the protective layer is an inorganic material layer, the inorganic material layer comprises a nitrogen-containing compound; a layer disposed on the protective layer and contacting the protective layer, wherein the first polymer layer has a thickness greater than 1 micrometer; and a first metal layer positioned on an upper surface of the first polymer layer and in contact The upper surface, and the first metal layer contacts a first contact in the first polymer layer and a first contact in the second circuit layer and a pass in the first polymer layer The second opening contacts a second contact of the second circuit layer, the first metal layer has a thickness greater than a thickness of the first circuit layer and the second circuit layer, and the first metal is located on the upper surface The thickness of the layer is greater than 5 microns, and the transistor is located under the first metal layer The first metal layer includes a titanium-containing metal layer and a first copper layer, wherein the titanium-containing metal layer is on the first polymer layer, on the first contact, and in the second And the first copper layer is on the titanium-containing metal layer; a hard plate is disposed above the semiconductor wafer, and the hard board includes a plurality of second circuit layers, a plurality of insulating layers and a second metal a layer, wherein the second metal layer comprises a second copper layer, a first nickel layer and a tin-containing metal layer, the first nickel layer being between the second copper layer and the tin-containing metal layer, the first The second metal layer connects the first contact and the second contact through the first metal layer; and a second polymer layer is disposed between the hard plate and the first polymer layer. The wafer assembly of claim 22, wherein the material of the first dielectric layer comprises a nitrogen compound. The wafer package of claim 22, wherein the material of the electric layer comprises an oxygen compound. The wafer package of claim 22, wherein the unstructured layer further comprises an oxygenate. 63 1301647 The wafer structure according to Item 22 of the nitrogen compound, wherein the wafer component output-signal described in Item 22 of the Guide Day Λ 明 专 专 , , , , , , , , , , , 再 再 54 54 54 54 54 54 54 To the other of the semiconductor crystals, at least one of the metal-conductor wafers, the electronic component, the second component, and the third component, the half-layer, after the half-layer, is transmitted to the =output_, the signal is passing The wafer cassette of claim 22, wherein the board outputs a signal passing through the first semiconductor unit, the hard semiconductor crystal-electronic component. And (4) after the retransmission to the 31. The wafer as described in claim 22, a metal layer is directly connected to the second metal layer. <,, wherein the wafer is structured as described in claim 22, and the metal layer further comprises a gold layer. ^ /, in the first-to-all of the items; the structure, wherein the upper metal layer is more c-di-second recording layer 'and the second recording layer is located in the first copper ^ 34. The wafer assembly of claim 22, wherein the two metal layers further comprise a second nickel layer and a gold layer, and the second nickel layer is on the second copper layer, and the gold layer is in the first layer On the second nickel layer. 35. The wafer package of claim 22, wherein the metal-containing layer is a layer. 36. The wafer structure of claim 22, wherein the metal-containing layer is a layer of a Chenhe alloy. 37. The wafer package of claim 22, wherein the titanium-containing metal layer is a titanium nitride compound layer. 64 1301647 38. As claimed in the patent application, the metal layer is a tin-alloy layer. 39. If the patent application area is tin, the tin metal layer is a tin layer. 4〇·If the scope of the patent application, the tin metal layer is a tin-silver alloy layer. The wafer assembly of claim 22, wherein the wafer assembly comprises 22, wherein the wafer assembly comprises 22 wafers, wherein the wafer structure is as described in claim 22 And wherein the tin-containing metal layer is a tin-silver-copper alloy layer. The wafer assembly of claim 22, wherein the second metal layer is above the first metal layer. 43. The wafer package of claim 22, wherein the first polymer layer is made of polyplylimide. 44. The wafer package of claim 22, wherein the first t-layer is made of benzocyclobutene (BCB). A wafer package comprising: a semiconductor wafer comprising: a germanium substrate; a first dielectric layer positioned above the germanium substrate; a transistor positioned below the first dielectric layer; a first circuit layer is disposed on the first dielectric layer; a second circuit layer is located above the first circuit layer, and the material of the first circuit layer comprises copper; Positioned between the first circuit layer and the second circuit layer; a protective layer on the second circuit layer, and the protective layer is an inorganic material layer, the inorganic material layer comprising a nitrogen-containing compound; a first metal layer is disposed on an upper surface of the protective layer and contacting the upper surface, and the first metal layer is in contact with an opening of the second circuit layer through a opening 651301647 located in the protective layer a first contact and a second opening in the protective layer contacting a second contact of the second circuit layer. The thickness of the first metal layer is greater than the thickness of the first circuit layer and the second circuit layer Thickness, and the thickness of the first metal layer on the upper surface The degree is greater than 5 micrometers, the transistor is located below the first metal layer, the first metal layer comprises a button metal layer and a first copper layer, wherein the button metal layer is located on the protective layer And the first copper layer is on the button metal layer; a hard board is located above the semiconductor wafer, and the hard board includes a plurality a second circuit layer, a plurality of insulating layers and a second metal layer, wherein the second metal layer comprises a second copper layer, a first nickel layer and a tin-containing metal layer, the first nickel layer Between the two copper layers and the tin-containing metal layer, the second metal layer is connected to the first contact and the second contact through the first metal layer; and a polymer layer is disposed on the hard plate and the protection Between the layers. The wafer structure of claim 45, wherein the material of the electric layer comprises a nitrogen compound. The machine material, wherein the wafer is not nitrided according to item 45, wherein the content is as described in item 45 of the patent application scope and the second contact is located at the lower side of the second metal layer. The first S1·the electronic component wheel-out signal of the wafer 所述 ί , , , , , , , , , , , , , , , , , , , , , 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子The metal output is a signal to an electronic component of the wafer assembly m half 66 1301647 conductor wafer as described in claim 45, and the signal is transmitted to the hard board after passing through the first metal layer. 53. The wafer package of claim 45, wherein the hard plate outputs a signal that is transmitted to the electronic component of the semiconductor wafer after passing through the first metal layer. 54. The wafer package of claim 45, wherein the first metal layer is in direct contact with the second metal layer. 55. The wafer package of claim 45, wherein the first metal layer further comprises a gold layer. The wafer assembly of claim 45, wherein the first metal layer further comprises a second nickel layer, and the second nickel layer is located in the first copper layer 57. The wafer assembly of claim 45, wherein the first metal layer further comprises a second nickel layer and a gold layer, and the second nickel layer is on the first copper layer, and the gold layer is in the second On the nickel layer. 58. The wafer structure of claim 45, wherein the metal layer of the button is a layer of germanium. 59. The wafer package of claim 45, wherein the metal-containing layer is a group of nitrogen compound layers. 60. The wafer package of claim 45, wherein the tin-containing metal layer is a tin-lead alloy layer. 61. The wafer package of claim 45, wherein the base metal layer is a tin layer. 62. The wafer package of claim 45, wherein the tin-containing metal layer is a tin-silver alloy layer. 63. The wafer package of claim 45, wherein the tin-containing metal layer is a tin-silver-copper alloy layer. 64. The wafer package of claim 45, wherein the second metal layer is above the first metal layer. 67 1301647 65. A wafer package comprising: a semiconductor wafer comprising: a substrate; a first dielectric layer positioned above the substrate; a transistor 'located in the first dielectric Below the layer, a first circuit layer is located on the first dielectric layer; a first circuit layer is located above the first circuit layer, and the material of the g # Μ second circuit layer comprises copper; a dielectric layer is disposed between the first circuit layer and the second circuit layer; a protective layer is disposed on the second circuit layer, and the protective layer is an inorganic material layer, and the inorganic material layer includes a a first polymer layer positioned on the protective layer and contacting the protective layer, wherein the first polymer layer has a thickness greater than 1 micrometer; and a first metal layer positioned on the first polymer layer And contacting the upper surface on an upper surface, and the first metal layer contacts a first contact and the transmission bit of the second circuit layer through a first opening in the first polymer layer a second opening in a polymer layer contacts a first layer of the circuit layer a thickness of the first metal layer is greater than a thickness of the first circuit layer and the second circuit layer, and a thickness of the first metal layer on the upper surface is greater than 5 micrometers, and the transistor is located at the Below the first metal layer, the first metal layer includes a button metal layer and a first copper layer, wherein the germanium-containing metal layer is on the first polymer layer, on the first contact layer, and Positioned on the second contact, and the first copper layer is on the germanium-containing metal layer; a hard plate is located above the semiconductor wafer, and the hard board includes a plurality of 681301647 two circuit layers, plural An insulating layer and a second metal layer, wherein the second metal sound comprises a second copper layer, a first nickel layer and a tin-containing metal layer, the first nickel layer being located in the second copper layer and the tin-containing layer Between the metal layers, the second metal layer is connected to the first contact and the second contact through the first metal layer; and a second polymer layer is disposed between the hard plate and the first polymer layer between. 66. The wafer package of claim 65, wherein the material of the second dielectric layer comprises a nitrogen compound. Wherein the first portion of the material is not included therein, wherein the first portion of the semiconductor layer is as described in claim 65. The material of the dielectric layer comprises an oxygen compound. 68. The wafer structure material layer of claim 65 further comprising an oxygenate. 69. The wafer constituting compound according to claim 65 is a ruthenium quinone compound. 70. The wafer assembly as described in the Scope of the Patent Application - the contact and the second contact are both below the second metal layer. The wafer structure described in item 65 of the conductor, the wafer structure described in item 65 of the semiconductor chip, wherein the layer of the burdock, the transmission i, the wheel-signal, the signal After passing through the ϊ-ϊ board output a message package, wherein the hard semiconductor wafer is electrically connected to the metal layer, then transferred to the metal layer and further packaged; The wafer assembly of claim 76, wherein the metal layer further comprises a second nickel layer, and the second nickel layer is in the first On a copper layer. The wafer assembly of claim 65, wherein the second gold further comprises a second nickel layer and a gold layer, and the second nickel layer is on the first copper layer, the gold layer is located at On the second nickel layer. The wafer structure of claim 65, wherein the group of metal layers is a layer. a wafer structure according to claim 65, wherein the metal layer is a nitrogen compound layer. The wafer structure described in claim 65, wherein the tin-containing metal layer is a tin-lead alloy layer. The wafer package of claim 65, wherein the tin-containing metal layer is a tin layer. The wafer package of claim 65, wherein the tin-containing metal layer is a tin-silver alloy layer. The wafer structure of claim 65, wherein the tin-containing metal layer is a tin-silver-copper alloy layer. The wafer assembly of claim 65, wherein the first metal layer is above the first metal layer. 85. The wafer assembly of claim 65, wherein the A polymer layer is made of polyamidamine, PJ). The wafer assembly of claim 65, wherein the material of the first compound layer is a ring-shaped ring of the base (^ ^1120〇}^1〇1)1^116,6.6). A wafer assembly comprising: a semiconductor wafer comprising: a germanium substrate; a first dielectric layer on the germanium substrate a transistor above the first circuit layer below the first dielectric layer, 1301647 a second circuit layer on the first dielectric layer, above the first circuit layer, and The material of the second circuit layer comprises copper; a second dielectric layer is located between the first circuit layer and the second circuit layer; a nitrogen-containing compound layer is located on the second circuit layer; a polymer layer positioned on the nitrogen-containing compound layer and contacting the nitrogen-containing compound layer, and the first polymer layer has a thickness greater than 1 a hard board, located above the semiconductor wafer, and the hard board includes a plurality of third circuit layers, a plurality of insulating layers and a pad, wherein the pad comprises a first copper layer and a nickel layer, and the pad a nickel layer contacting the first copper layer; a metal layer containing silver and tin between the second circuit layer and the pad, and the thickness of the metal layer containing silver and tin is greater than 5 microns, and the nickel a layer between the metal layer containing silver and tin and the first copper layer; a nickel-containing metal layer 'between the metal layer containing silver and tin and the second circuit layer; 'between the nickel-containing metal layer and the second circuit layer, and the thickness of the second copper layer is greater than the thickness of the nickel-containing metal layer; a titanium-containing metal layer, located in the second copper layer and the first Between the two circuit layers, and the titanium-containing metal layer contacts the first polymer layer and contacts the second circuit layer through an opening in the first polymer layer, and the pad penetrates the silver-containing and tin-containing layers a metal layer, the nickel-containing metal layer, the second copper layer and the titanium-containing metal layer are connected to the second circuit layer; a second polymer layer is disposed between the hard plate and the first polymer layer, and the second polymer layer contacts the hard plate and the first polymer layer. 88. The wafer structure of claim 2, wherein the material of the second dielectric layer comprises a nitrogen compound. 1301647 - The wafer structure of claim 87, wherein the material of the first dielectric layer comprises an oxygen compound. The wafer structure according to Item 87, wherein the nitridium-containing layer is a nitrogen compound layer. The wafer structure according to claim 87, wherein the first polymer layer is made of a material The wafer structure of claim 87, wherein the material of the layer of the first layer is a benzocyclobutene (BCB). 93. The wafer package of claim 87, wherein the material of the metal layer comprising silver and tin further comprises copper. 〃 94. The wafer structure of claim 87, wherein the nickel metal layer is a nickel layer.晶片 τ / 3 95. The wafer structure of claim 87, wherein the titanium-containing metal layer is a titanium layer. The wafer package of claim 87, wherein the titanium-containing metal layer is a titanium-tungsten alloy layer. 97. The wafer structure of claim 87, wherein the metal-containing layer is a layer of a nitrogen compound. 98. The wafer package of claim 87, wherein the crystal is below the pad. 〃 μ 99. A wafer package comprising: a semiconductor wafer comprising: a substrate; a first dielectric layer positioned above the germanium substrate; a transistor 'below the first dielectric layer; a first circuit layer is disposed on the first dielectric layer; a second circuit layer is located above the first circuit layer, and the material of the second circuit layer comprises copper; 72 1301647 a second dielectric a layer between the first circuit layer and the second circuit layer; a nitrogen-containing compound layer on the second circuit layer; and a first polymer layer on the nitrogen-containing compound layer Contacting the nitrogen-containing compound layer, and the first polymer layer has a thickness greater than 丨 micron; a hard plate is disposed above the semiconductor wafer, and the hard plate includes a plurality of third circuit layers, a plurality of insulating layers and a pad The pad comprises a first copper layer and a nickel layer, and the nickel layer contacts the first copper layer; a metal layer containing silver and germanium is located between the second circuit layer and the pad, And the thickness of the metal layer containing silver and tin is greater than 5 microns, and the nickel layer Between the metal layer containing silver and tin and the first copper layer; a nickel-containing metal layer between the metal layer containing silver and tin and the second circuit layer; a second copper layer, Between the nickel-containing metal layer and the second circuit layer, and the thickness of the second copper layer is greater than the thickness of the nickel-containing metal layer; a germanium-containing metal layer, located in the second copper layer and the second line Between the layers, and the group-containing metal layer contacts the first polymer layer and contacts the second circuit layer through an opening in the first polymer layer, and the pad transmits the metal containing silver and tin a layer, the nickel-containing metal layer, the second copper layer and the button-containing metal layer are connected to the second circuit layer; and a second polymer layer is disposed between the hard plate and the first polymer layer, And the second polymer layer contacts the hard plate and the first polymer layer. 100. The wafer θ structure according to claim 99, wherein the material of the second dielectric layer comprises a nitrogen compound. 101. The wafer structure of claim 99, wherein the material of the two dielectric layers of the bean comprises an oxygen compound. The wafer structure of claim 99, wherein the layer of the nitrogen compound comprising 73 1301647 is a gas dream compound layer. The wafer structure of claim 99, wherein the first polymer layer is made of polyimide (PI). 104. The wafer structure of claim 99, wherein the first polymer layer is made of benzocyclobutene (BCB). 105. The wafer package of claim 99, wherein the material of the metal layer comprising silver and tin further comprises copper. 106. The wafer structure of claim 99, wherein the nickel-containing metal layer in the bean is a nickel layer. ', " 107. The metal layer of the wafer structure of the wafer as described in claim 99 is a button layer. The wafer structure of claim 99, wherein the I-containing metal layer is a one-sided nitrogen alloy layer. VIII. The wafer structure of claim 99, wherein the transistor is located below the pad. ^ 74