200814211 九、發明說明： 【發明所屬之技術領域】 本發明是觸於-種晶;1構裝及晶片構錢程，且制是有關於一種 具有咼電性效能之晶片構裝及其所對應之晶片構裝製程。 【先前技術】 隨著資訊產品技術的突飛猛進，人類欲快速獲得千里以外的資訊，已 不疋-件聊的事’企魏爭餘得輕上的優勢，透過建置高效率的資 訊產品可以_此目的。隨著資訊產品_陳出新與各種線路設計的整 口最新的單晶片普遍地提供比以往更多的功能。由於半導體科技的曰新 月異’銅製㈣量產成功，再加上_電路的整合，大錄魏號傳輸可 以在同-單晶片内，使得訊號的傳輸路徑可以縮短且晶片的效能可以改善。 在晶片_完成之後’-般係利用打線導線或是凸塊，藉以使晶片與 基板電性連接。無，*論是打料線或是凸塊在垂直_麟輸方向上 的截面積均甚小，目此當織在進行傳鱗，會產生過大雜訊，嚴重時 甚至會導致運算錯誤。 【發明内容】 有鑒於此，本發明的目的就是在提供一種晶片構裝及晶片構裝製程， σ、連接半‘體晶片之線路與冑路連接構件之線路，藉以改善電性效能。 為達成本發目的，本發明提出_種晶片構裝，包括—半導體晶片 %路連接構件。半導體晶片具有—第—線路，電路連接構件具有一第 6 200814211 二線路，其中電路連接構件之第二線路係直接接觸地連接半導體晶片之第 一線路。 另外，本發明還提出一種晶片構裝，包括—替體晶片、一導電層及 -電路連接構件’其中半導體晶片具有—第—線路，電路連接構件具有— 第二線路，導電層係'連接第—線路及第二線路，且導電層之成分包括聚合 物及多數個金屬粒子，金屬粒子齡佈在聚合物巾，第—線職透過導電 層之金屬粒子電性連接於第二線路。 、，另外’本發明還提出一種晶片構裝製程，包括下列步驟··首先，提供 半V體阳片’其中半導體晶片具有—第_線路，並且還要提供—電路連 接構件八中包路連接構件具有一第二線路。接著，直接接觸地連接電路 I接構件之及半導體晶狀第一線路。 另外，本發明遊提出一種晶片構裝製程，包括下列步驟：首先，提供 -半導體晶片，其中半導體晶片具有一第'線路，並且還要提供一電路連 接構件’其中電路連接構件具有一第二線路。接著，直接接觸地連接電路 連接構件之第二線路及半導體晶片之第 一線路。 另外，本發明還提出-種晶片構賴程，包括下列步驟：首先，提供 :半導體晶片’射輸晶㈣，並爾提供—電路連 ^件’其恤物嫩㈠：_，，縣—魏層於電路 件之4-、_上，其巾導€狀絲⑽聚合物 子，金屬粒子分佈在聚合物中。接著，將第-輪入導謝，使= 線路透過導f層之金屬粒子電性連接於第二線路。 7 200814211 為讓本發明之上述和其他目的、特徵和優點能更明顯易懂，下文特舉 夕個較佳實施例，並配合所關式，作詳細說明如下。 【實施方式】 構裝亀之—是在於轉觸之線路__ 電 _連_叙魏，使料賴；之料心大面積地 電性連接於電路連接構件之線路，如此可以大幅度地改善半導體晶片與 路連接構件之間的電性關係。 或者，半導體晶片之線路可以透過含有聚合物及金屬粒子的導電層大 面積地連胁猶觸狀祕，如此柯从幅度喊善半導體晶 片與電路連接構件之間的電性關係。 爲簡化說明，在下述實施例中’各圖之相同標號係代表雷同的構件 相同標號所代表之構件在前面說明過_容將可能在後㈣容中省略。 一、晶片構裝之第一實施例 在晶片構裝之第-實施例中，半導體晶片具有—厚金屬線路，位在半 導體晶片絲層’轉體以之厚金麟路射以直接_地連接基板的 線路。以下配合圖示，舉出數種實施可能情形： 1·半導體晶片之厚金屬線路與基板的線路係作為半導體曰片内訊” 傳輸之用 9 之訊號 圖1繪示依照本發明第-實施例之晶片構*在組裝前半導體晶片及基 板的剖面示意圖，其中切過半導體晶片之厚金屬線路__分^雜 金屬線路的延伸路徑作垂直切過半導體晶片的剖面而得，切過義才 200814211 的σ ]面σ卩刀係沿著線路在基板上的延伸路徑作垂直切過基板的剖面而得。 半V體曰曰片1〇〇包括一半導體基底11〇、多數層薄膜介電層ΐ22、ΐ24、ΐ26、 多數層薄膜線路層132、134、136及一保護層14〇。 半$體基底110具有多數個電子元件112,電子元件η?係配設於半導 體基底no之-主動表面114絲層，其中半導體基底ιι〇比如是石夕基底， 透過摻雜五價或三價的離子，比如是觸離子或碗離子，藉以形成多個電子 兀件112於半導體基底11〇之表層，電子元件112比如是金屬氧化物半導 ，' 體或電晶體等。 利用化學氣向沉積的方式，可以形成多層之薄膜介電層122、124、既 在半導體基底110之主動表面114上，其中薄膜介電層122、⑵、既比 如是氧碎化合物、_化合物魏氧魏合物等，每__線路層、 134、136係分別配置於其中一薄膜介電層122、124、126上，其中薄膜線 路層132、134、136的材質比如包括鋁、銅或矽等。薄膜介電層ι22、、 126具有多數個導通孔12卜123、125，薄膜線路層132、134、136可以藉 ; 由薄膜介電層122、124、126之導通孔12卜123、125彼此電性連接，並 電性連接至電子元件112。 保護層140係配置於薄膜介電層122、124、126與薄膜線路層丨犯、1料、 136上，其中保護層140的厚度ζ比如係大於〇· 35微米，且保護層14〇的 結構比如係為一氮發化合物層、一氧硬化合物層、一鱗秒玻蹲居戈至丨 上述材質所構成的複合層。保護層140具有多數個開口 142,暴露出位在頂 層之薄膜線路層136。 9 200814211 厚金屬線路150係位於保護層140上，且經由保護請之開口 142 電性連接於細_ 136，射___厚親大㈣膜線路層 132、134、136的厚度。凸塊160係大致上對準保護層14〇之開口 142，並 電性連接__ 136。_上，_線_與凸_可以是 利用相同的製朗時完成，@此厚金騎路⑽與凸塊⑽可以具有相同 的金屬層結構線路150 _⑽的_結構在後文有詳細地 說明’在絲跳過。值得注意的是，厚麵線路⑽的厚度〗係大致上相 同於凸謂之厚度h，其中厚金屬線路15_度〗與凸塊⑽之厚度h 比如係大於1微米，在較佳的情況下，比如係大於5微米。 基板·的形式可以包括硬板或軟板，其中硬板—般是由多層線路層 及絕緣層交互叠合喊，比如是市面上常見的四層板、六層板或八層板等， 其中絕緣層的材質比如是聚合物或喊等。軟板比如係由—層線路層及一 層、、、巴緣層所構成，線路層係位在絕騎上，其巾絕緣層的材質比如是聚合 物般而0，由於軟板具有甚薄的厚度，因此具有較大的撓曲性。 如上所述，基板200可以是硬板或軟板的形式。基板200比如具有一 線路層210及-焊罩層220，位在基板2〇〇的頂部，焊罩層220係位在基板 200之線路層21〇上，用以保護線路層21〇，其中線路層21〇具有一線路212 及接墊214’焊罩層220之開口 222係暴露出線路層210之線路212及接 墊 214。 另外’就線路的形式而言，半導體晶片1〇〇之厚金屬線路15〇可以是 &著任何方向在半導體晶片1〇〇之頂部延伸，比如是類似直線延伸的形式、 200814211 曲線延㈣蝴物刪之__卿路徑，且基請之線 路212亦仙辦麵額她之了胃麵伸，比如是類似直線延 伸的形式、喻物樹跑输⑽物雜徑。在較 佳的情況下’半導體晶片100之厚金屬線路⑽與基板·之線路212之 間係呈現傭嶋’靖導細⑽絲板㈣在齡時，半導體 晶片之厚金屬線路150可以對準基板200之線路212。 在貝關中，半導體晶片⑽之厚金屬線路⑽與基板之線路 212比如是螺旋狀的電感元件，如圖u及圖ΐβ所示，其中㈣係為圖】 中基板200之線路212投影至平面·上的平面示意圖；圖ΐβ係為圖！ 中半^體曰曰片100之厚金屬線路15〇投影至平面麵上的平面示意圖。請 多圖及圖1B ’半導體晶片⑽之電感元件⑽的繞線路徑與基板施 之«元件212的繞線路徑之間係呈現鏡射的關係，基板測之電感元件 系=著路m〇〇延伸，比如是從路徑u⑻之X點延伸至路徑H〇〇之 γ點；料體晶片⑽之電感元件⑽係沿著路徑議延伸，比如是從路 徑1200之X點延伸至路徑12⑻之y點。 請參照圖2,其繪示圖i中半導體晶片與基板接合後之 晶片構裝的剖面 不思圖在提供半導體晶# 1〇〇與基板2〇〇之後，可g進行接合的步驟， 使付半$體晶片100之厚金屬線路15()可以直接接觸地連接基板觸之線 路212 ’且半導體晶片100之凸塊160可以直接接觸地連接基板200之接墊 214接著，可以填入一聚合物層17〇於半導體晶片1〇〇與基板之間， 承合物層170係包覆厚金屬線路15〇的周圍及凸塊16〇的周目。定義一平 200814211 面1000，係大致上平行於半導體基底110之主動表面114，其中厚金屬線 路150與基板線路212連接的區域投影至平面1〇〇〇上的延伸距離s比如是 大於500微米，或者比如是大於8〇〇微米，或者比如是大於12〇〇微米；厚 金屬線路150與基板線路212連接的區域投影至平面1〇〇〇上的面積比如係 大於30, 000平方微米，或者比如是大於go, 〇〇〇平方微米，或者比如是大 於150, 000平方微米。 在其中一實施例中，請參照圖1A及圖1B，當基板2〇〇之電感元件212 直接接觸地接合半導體晶片100之電感元件15〇時，基板200之電感元件 212的A、B、C、D、E、F、G區域係分別直接接觸地接合半導體晶片之 電感元件150的a、b、c、d、e、f、g區域。請參照圖2A，其繪示圖1A及 圖1B之二電感元件212、150接合後之連接區域投影至平面1〇〇〇上的平面 示意圖，其中二電感元件150、212連接的區域（圖2A中晝斜線的區域)投 影至平面1000上的延伸距離(路徑12〇〇從χ點延伸至y點的距離）比如是 大於500微米，或者比如是大於8〇〇微米，或者比如是大於12〇〇微米；二 電感元件150、212連接的區域（圖2A中畫斜線的區域)投影至平面丨〇⑼上 的面積比如係大於30, 000平方微米，或者比如是大於8〇, 〇〇〇平方微米， 或者比如是大於150, 〇〇〇平方微米。 請參照圖2，在電性傳輸上，半導體晶片1〇〇内之電子元件112的其中 -個（比如是電子元件112a)係適於輸出一電子訊號，此電子訊號經由薄膜 線路層132、134、136並穿過保護層14〇後，傳輸至厚金屬線路15〇及基 板200之線路212，接著再穿過保護層14〇，並經由薄膜線路層136、ι34、 12 200814211 7傳輸至半導體晶片之其他的電子元件112之至少其中一個（比如 私子元件112b)，此日寸’半導體晶片繼之厚金屬線路脱與基板細之 線路212可以作為半導體晶片1〇〇内之訊號傳輸之用。另外，此電子訊號 在仗電子το件112a傳輸至厚金屬線路15()及基板测之線路212後，還可 以傳輸至基板200内；此時，半導體晶片⑽之厚金屬線路⑽與基板2〇〇 之線路212亦可以作為半導體晶片1〇〇與基板2〇〇間之訊號傳輸之用。 在凸塊160的電性傳輸上，半導體晶片1〇〇可以透過凸塊16〇傳送電 ‘子峨至基板200，或是可以透過凸塊擺接收由基板2〇〇所傳來的電子訊 號。 如上所述，半導體晶片1〇〇之厚金屬線路與基板2〇〇之線路212 除了可以作為電子訊號的橫向傳輸之外，還可以作為半導體晶片1〇〇與基 板200間的縱向傳輸。由於半導體晶片1〇〇之厚金屬線路15〇係直接接觸 地連接基板200之線路212，因此半導體晶片1〇〇之厚金屬線路15〇可以大 面積地電性連接基板200之線路212，如此可以大幅地增加半導體晶片 【 與基板200間電性連接的效能，且可以減少雜訊的產生。 在上述電子訊號之電性傳輸上，半導體晶片1〇〇之厚金屬線路15〇與 基板200之線路212係作為半導體晶片1〇〇内之訊號傳輸之用，亦同時作 為半導體晶片100與基板200間之訊號傳輸之用。然而，本發明的應用並 不限於此，半導體晶片100之厚金屬線路150與基板200之線路212亦可 以僅作為半導體晶片100内之訊號傳輸之用，而不作為半導體晶片1〇〇與 基板200間之訊號傳輸之用’此時基板200之線路212係與基板200内之 13 200814211 其它線路呈現電性斷路的狀態。 在其他只施情形中，基板2〇〇亦可以適於輸出一電子訊號，傳輸至基 板200之線路212及厚金屬線路15〇,接著再穿過半導體晶片謂之保護層 140，並經由薄膜線路層136、134、132傳輸至半導體晶片1〇〇内之至少一 電子元件112(比如是電子元件112&及112b)。 在圖1及圖2中，厚金屬線路150係直接形成在保護層14〇上；然而， 厚金屬線路150亦可以是形成在位於保護層14〇上之聚合物層18〇上，如 ® 3所tf，其緣不依照本發明第一實施例之另一種晶片構裝的剖面示意圖。 請參照圖3，-聚合物層180係形成於保護層14〇上，聚合物層18〇具有多 個開口 182，大致上係對準保護層14〇之開口 142，厚金屬線路15〇係形成 於聚合物層18G上，並且經由聚合物層之開口 182及保護層14〇之開 口 142連接至薄膜線路層136。值得注意的是，突出於聚合物層⑽之開口 182外的凸塊160之厚度h比如是大致上相同於位在聚合物層18〇上之厚金 屬線路150的厚度j，且厚金屬線路15〇與凸塊16〇係具有相同的金屬層結 、 構，其中突出於聚合物層180之開口 182外的凸塊160之厚度h與位在聚 合物層180上之厚金屬線路15〇的厚度』·比如係大於j微米，在較佳的情 況下，比如係大於5微米。聚合物層18〇的厚度k比如係大於丨微米，且 承合物層180的材質比如是聚亞酿胺（p〇iyimide，pi)、苯基環丁烯 (benzocyclobutene ’ BCB)、聚亞芳香基醚(paryiene)、多孔性介電材質或 彈性體等。 在圖1至圖3中，厚金屬線路150係透過保護層14〇之小開口 142小 200814211 面積地連接頂層的薄膜線路層136;然而’厚金屬線路⑽亦可以是透過保 護層140之大開口 142大面積地連接了_薄膜線路層136，如圖*及圖5 所示，其繪示依照本發明第一實施例之其他形式晶片構裝的剖面示意圖， 其中頂層_麟簡136財—薄麟路m，賴層⑽之開口⑷係 大面積地暴露出薄膜線路137，使得厚金屬線路15〇可以大面積地連接保罐 層14〇之開口 142所暴露出的薄麟路137，上述之大面積地連接比如是如 下所述的情況。 請參照圖4及圖5，大面積連接之第一種情況：定義一平面麵，此 平面1〇〇〇係大致上平行於半導體基底110之主動表面114，厚金屬線路⑽ 與薄膜線路137連接的區域投影至此平面麵上的面積除㈣麟路⑶ 投影至此平面1_上的面積之比值比如係大於Q. 5，或者比如係大於8， 或者比如係大致上等於1。大面積連接的第二種情況：保護層14〇之開口 142暴露出薄膜線路137的面積比如係大於3〇 〇〇〇平方微米，或者比如係 大於80, 000平方微米，或者比如係大於15〇, 〇〇〇平方微米。大面積連接的 第二種情況.厚金屬線路150與薄膜線路層⑽連接的區域投影至此平面 1000上的延伸距離t比如係大於500微米，或者比如係大於8〇〇微米，或 者比如係大於1200微米。只要是符合上述任一情況，則可以稱作厚金屬線 路150係大面積地連接頂層之薄膜線路層136。 在一實施例中，當半導體晶片100之厚金屬線路15〇比如係為螺旋狀 的電感元件時，則與厚金屬線路150大面積連接的薄膜線路Μ?亦比如係 為螺旋狀的電感元件，如圖5A所示，其繪示圖4及圖5中厚金屬線路與薄 15 200814211 膜線路連接之區谢又衫至平面1000上的剖面示意圖，其中厚金屬線路與薄 膜線路均係為職狀之電感元件的樣式。作為電感元件之薄膜線路137係 ^著路徑1200延伸，比如是從路徑12〇〇之p點延伸至路徑12〇〇之q點。 清參照® 5A，二電感元件150、137連接的區域投影至平面1〇〇〇上的 面積（圖5A中畫斜線的區域)除以薄膜線路137投影至此平面上的面積⑽ 5A中虛線所包圍的區域)之比值比如係大於〇·5，或者比如係大於u，或 者比如係大致上等於卜另外，保護層14()之開口 142暴露出薄膜線路⑶ ; 的面積（圖5Α中畫斜線的區域）比如係大於3〇, _平方微米，或者比如係 大於8〇, 〇〇〇平方微米，或者比如係大於15〇, _平方微米。另外，二電感 π件150、137連接的區域（圖5Α中晝斜線的區域)投影至平面1〇〇〇上的延 伸距離（圖5Α巾路徑1200從ν點延伸至w點的距離）比如係大於5〇〇微米， 或者比如係大於8〇〇微米，或者比如係大於i2Q〇微米。 請參照圖4及圖5，在電性傳輸上，半導體晶片1〇〇内之電子元件112 的其中個（比如是電子元件112a)係適於輪出一電子訊號，此電子訊號經 v 由薄膜線路層132、134後，可以傳輸至薄膜線路137、厚金屬線路15〇及 基板200之線路212，接著再經由薄膜線路層134、132可以傳輸至半導體 晶片100内之其他的電子元件112之至少其中一個（比如是電子元件 112b);此時，薄膜線路丨37、厚金屬線路15〇與基板2〇〇之線路212可以 作為半導體晶片100内之訊號傳輸之用。另外，此電子訊號在傳輸至薄膜 線路137、厚金屬線路150及基板200之線路212後，還可以傳輸至基板 200内；此時，薄膜線路137、厚金屬線路15〇與基板2〇〇之線路212亦可 200814211 以作為半導體晶請與基板_之訊號傳輪之用。另外，基板綱亦 適於輸出一電子訊號’傳輪至基板測之線路212及轉體晶片議之厚 金屬線路⑽及薄膜線路137，接著再經由薄膜線路層134、您傳輸至半 導體晶片1()◦内之至少—電子元件112(比如是電子元件及卿。 另外’就凸塊160的電性傳輸而言，半導體晶片100可以透過凸塊⑽ 傳送電子訊號至基板200，或是可以透過凸塊⑽接收由基板所傳來的 電子訊號。 ’ 如上所述，半導體晶片1〇〇之薄膜線路137、厚金屬線路⑽與基板 200之線路212除了可以作為電子訊號的橫向傳輸之外，還可以作為半導體 晶片100與基板200間的縱向傳輸。由於厚金屬線路15〇係大面積地連接 薄膜線路137及基板2〇〇之線路212，故至少可以增加電子訊號之一部份傳 輸路控的截面積，因此可以改善電子訊號之傳輸品質。 圖4與圖5的不同點是在於半導體晶片1〇〇是否有配置聚合物層18〇 在保護層140上。請參照圖4，半導體晶片1〇〇在形成保護層14〇之後，接 、 著係同時形成厚金屬線路150及凸塊160於薄膜線路層136上，其中凸塊 160的厚度h比如是大致上相同於厚金屬線路15〇的厚度〗，且凸塊16〇的 金屬層結構係大致上相同於厚金屬線路15〇的金屬層結構，其中凸塊16〇 之厚度h與厚金屬線路15〇之厚度j比如係大於1微米，在較佳的情況下， 比如係大於5微米。 然而’請參照圖5，在形成保護層14〇之後，還形成圖案化之一聚合物 層180於保護層14〇上，聚合物層ι8〇的厚度k比如係大於1微米，且聚 17 200814211 合物層180的材質比如是聚亞醯胺（poiyimide，PI)、苯基環丁浠 (benzocyclobutene，BCB)、聚亞芳香基醚(parylen幻、多孔性介電材質或 彈性體等。聚合物層180具有一開口 182，暴露出頂層之薄膜線路層136， 其中包括暴露出薄膜線路137。接著，可以同時形成厚金屬線路15〇及凸塊 160於薄膜線路層136上，其中突出於聚合物層18〇之開口 182外的凸塊 160之厚度h比如是大致上相同於突出於聚合物層18〇之開口 182外的厚金 屬線路150的厚度j，且凸塊16〇的金屬層結構係大致上相同於厚金屬線路 150的金屬層結構，射突出於聚合物層18〇之開〇 182外的凸塊刷之厚 度h比如係大於1微米，在較佳的情況下，比如係大於5微米，·突出於聚 合物層180之開口 182夕卜的厚金屬線路15〇之厚度】比如係大於（微米， 在較佳的情況下，比如係大於5微米。 請參照圖4及圖5,在製作完成半導體晶片⑽之厚金屬線路15〇及凸 塊160之後’可以進行接合的步驟，使得半導體晶片議之厚金屬線路⑽ 可以直接接觸地連接基板2GG之線路212，且半導體晶片⑽之凸塊⑽可 以直接接觸地連接基板綱之接墊214。接著，可以填入—聚合物層於 半導體晶請與基板雇之間，聚合物層m係包覆厚金屬線路⑽的 周圍及凸塊160的周圍。 ' 片與基板間 2·半V體曰曰片之厚金屬、線路與基板的線路係作為半導 之訊號傳輸之用 請參照圖6至圖9,其緣示依照本發明第一實施例之另_類型曰片 的剖面示意圖’其中圖6環之半導體晶㈣係分別雷同彻至則 18 200814211 之半導體晶片1G0，且圖6至圖9之基板咖係雷同於圖2至圖5之基板 200，在此便不再贅述；惟不同點係在於半導體晶片ι〇〇之厚金屬線路15〇 與基板200的線路212僅作為半導體晶片iq〇與基板2QQ間之訊號傳輸之 用，而不作為料體晶片綱内之訊號傳輪之用，如下所述。 «月參圖6及圖7 ’在電性傳輸上，半導體晶片1⑼内之電子元件112 的其中一個（比如是電子元件112a)係適於輪出一電子訊號，此電子訊號經 由薄膜線路層132、134、136並穿過保護層14〇後，傳輸至半導體晶片1〇〇 之厚金屬線路150及基板200之線路212，接著再傳輸至基板2〇〇内；此時， 半導體晶片1GG之厚金屬線路150與基板200之線路212係可以作為半導 體晶片100與基板200間之訊號傳輸之用。 在其他實施情形中’基板200亦適於輪出一電子訊號，傳輸至基板2〇〇 之線路212及半導體晶片100之厚金屬線路15〇，接著再穿過半導體晶片 1〇〇之保護層14〇,並經由薄膜線路層136、134、132傳輸至半導體晶片⑽ 内之至少一電子元件112(比如是電子元件U2a)。 請參照圖8及圖9，在電性傳輸上，半導體晶片⑽内之電子元件ιΐ2 輪自—電子舰，輯子訊號經 由薄膜線路層132、134後，傳輸至薄膜線路137、厚金屬線路15〇及基板 2〇〇之線路212，接著再傳輸至基板200内；此時，半導體晶片⑽之厚金 屬線路15〇與基板200樣路212係可以作為半導體晶片⑽絲板· 間之訊號傳輸之用。 在其他實施情形中’基板200亦適於輪出—電子訊號，傳輪至基板· 200814211 之線路212及半導體晶片⑽之厚金屬線路15〇及薄膜線路⑶，接著再經 蓴膜線路層134、132傳輸至半導體晶片⑽内之至少—電子元件⑽（比 如是電子元件112a)。 …明參照圖6至圖9,就凸塊16〇的電性傳輸而言，轉體晶片謂可以 透過凸塊160傳送電子魏g^板·，或是可以透過凸塊⑽接收由基板 2〇〇所傳來的電子訊號。 如上所述，轉體晶片100之厚金屬線路15〇與基板綱之線路批 除了可以作為電子訊號的橫向傳輸之外，還可以作為半導體；1〇〇與基 間的縱向傳輸。由於半導體晶片⑽之厚金屬線路⑽係直接接觸 地連接基板細之線路212，因此半導體晶請之厚金屬線路⑽可以大 面積地紐連絲板200之線路212，如此可以大幅地增加半導體晶片1〇〇 與基板200間電性連接的效能，且可以減少雜訊的產生。 3.半導體晶片之厚金屬線路與基板私線路係作為電源匯流排或接地匯 流排之用 請參照圖10至圖13，其緣示_本發明第一實施例之另一類型晶片構 裝的剖面示意圖，其中圖1G至圖13之半導體晶片⑽齡難同於圖2 至圖5之半導體晶片⑽，且圖1()至圖13之基板測係雷同於圖2至圖& 之基板200，在此便不再贅述；惟*同點係在於半導體晶片⑽之厚金屬線 路150與基板200的線路212係作為電源匯流排或接地匯流排之用，如下 所述。 請參照圖10至圖13，當半導體晶片100之厚金屬線路150與基板200 20 200814211 的線路212係作為電源匯流排時，半導體晶片⑽之厚金屬線路脱與基 板200的線路212比如雜生連接至半導體晶片ι〇㈣之電源匯流排咖， 比如係由細魏層134提供之，並域·連接至基板細n的電源匯 机排由於半導體晶片1〇〇之厚金屬線路⑽係大面積直接接觸地連接基 板200之線路212，且電性連接至半導體晶片1〇〇内之電源匯流排撕，如 此可以減少半導體晶片議之電源匯流排135因爲受到訊號干擾而產生電 塵、欠化的程度’並且半導體晶片⑽可以提供較為穩定之電源電壓。 或者在其他的貝施情況中，半導體晶片⑽之厚金屬線路15〇與基 板2〇0的線路212係電性連接於半_日片⑽之電源匯流排 135,但是卻 舆基板200内的線路之間呈現電性斷路。 多、圖10至圖13’畜半導體晶片1〇〇之厚金屬線路15〇與基板· 的線路212係作為接地匯流排時，半導體晶片⑽之厚金屬線路⑽與基 板2〇〇的線路212 _、紐連接至半導_⑽欧接舰流排撕， 比如係由134提供之，纽細_至基板· _接地匯 ;半‘體00片100之厚金屬線路⑽係大面積直接接觸地連接基 、、桌路212且电性連接至半_晶片刚内之接地匯流排⑶如 此可以減少半導體晶片⑽之接地匯流排135因爲受到訊號干擾而產生電 趣_度’並且料_⑽可喷供_教_壓。或者， +導體晶請之厚金屬線路⑽與基板咖的線路犯係電性連接於半 導體晶請之接地匯流細，但是卻與基板2⑼内的線路之間呈現電性 斷路。 21 200814211 4.半導體晶>{之厚金麟職作為基㈣之峨傳輸之用、或是作為 基板之電源匯流排或接地匯流排之用 請參照圖14及圖15,其繪示依照本發明第一實施例之另一類型晶片構 裝的剖面示意圖，其中圖14及圖15之半導體晶片⑽係分別雷同於圖2 及圖3之半導體晶片100，且圖14及圖15之基板2〇〇係雷同於圖2及圖3 之基板200 ’在此便不再贅述；惟不同點係在於半導體晶片1〇〇之厚金屬線 路150係與半導體晶片100内之薄膜線路層132、134、136之間呈現電性 斷路的狀態，且半導體晶片100之厚金屬線路15〇與基板之線路212 係作為基板200内之訊號傳輸之用、或是作為基板2〇〇之電源匯流排或接 地匯流排之用，如下所述。 請參照圖14及圖15，當半導體晶片100之厚金屬線路15〇與基板2〇〇 之線路212作為基板200内之訊號傳輸之用時，一電子訊號適於經由基板 200傳輸至基板2〇〇之線路212與半導體晶片1〇〇之厚金屬線路go，經由 基板200之線路212與半導體晶片100之厚金屬線路15〇的傳輸後，再傳 輸至基板200之其他線路，其中此電子訊號並未經由基板2〇〇之線路212 與半導體晶片100之厚金屬線路150直接傳輸至半導體晶片1〇〇内。如上 所述，半導體晶片100之厚金屬線路150與基板200之線路212可以僅作 為基板200内之電子訊號傳輸之用，而不作為半導體晶片1〇〇内之訊號傳 輪之用或是作為半導體晶片100與基板200間之訊號傳輸之用。由於半導 體晶片100之厚金屬線路150係直接接觸地連接基板200之線路212，因此 半導體晶片100之厚金屬線路150可以大面積地電性連接基板2〇〇之線路 22 200814211 212，如此可以增加此電子訊號的電性傳輸品質。 请參照圖14及圖15 ’當半導體晶片1〇〇之厚金屬線路ι5〇與基板 之線路212作為基板200之電源匯流排時，半導體晶片ι〇〇之厚金屬線路 150與基板200之線路212係適於電性連接基板2〇〇内之電源匯流排，其中 半導體晶片100之厚金屬線路150係與半導體晶片1〇〇内之電源匯流排之 間呈現電性斷路。由於半導體晶片100之厚金屬線路15〇係直接接觸地連 接基板200之線路212，且電性連接至基板200内之電源匯流排，如此可以 減少基板200之電源匯流排因爲受到訊號干擾而產生電壓變化的程度，並 且基板200可以提供較為穩定之電源電壓。 請參照圖14及圖15,當半導體晶片100之厚金屬線路15〇與基板2〇〇 之線路212作為基板200之接地匯流排時，半導體晶片1〇〇之厚金屬線路 150與基板200之線路212係適於電性連接基板2〇〇内之接地匯流排，其中 半導體晶片100之厚金屬線路15〇係與半導體晶片ι〇〇内之接地匯流排之 間呈現電性斷路。由於半導體晶片100之厚金屬線路15〇係直接接觸地連 接基板200之線路212，且電性連接至基板2〇〇内之接地匯流排 ，如此可以 減少基板200之接地匯流排因爲受到訊號干擾而產生電壓變化的程度，並 且基板200可以提供較為穩定之接地電壓。 5·半導體晶片之厚金屬線路與基板之線路的金屬層結構 明參妝圖16，其繪示在本發明第一實施例中半導體晶片之厚金屬線路 之其中一種金屬層堆積結構的剖面示意圖。前述之半導體晶片1〇〇之厚金 屬線路150比如包括一底層金屬層1511及一頂層金屬層1516,底層金屬層 23 200814211 1511比如係直接形成在保護層140上(如圖1、圖2、圖6、圖ι〇及圖μ 所示）、聚合物層180上(如圖3、圖7、圖u及圖15所示）或頂層之薄膜 線路137上(如圖4、圖5、圖8、圖9、圖12及圖13所示），頂層金屬層 1516係位在底層金屬層1511上’其中底層金屬層1511之材質比如係為欽 嫣合金、鈦氮化合物、组或组氮化合物等，頂層金屬層1516的材質比如係 為金，頂層金屬層1516的厚度1：匕如係大於i微米，在較佳的情況下， 比如係大於5微米。此外，半導體晶片100之凸塊16〇亦可以具有與厚金 f 屬線路150相同之如圖16所示的金屬層結構。 請參照圖17，其緣示在本發明第一實施例中半導體晶片之厚金屬線路 之其中一種金屬層堆積結構的剖面示意圖。前述之半導體晶片1〇〇之厚金 屬線路150比如包括一底層金屬層1521及一頂層金屬層1526，頂層金屬層 1526係位在底層金屬層1521上，其中底層金屬層1521比如係由一黏著/ 阻障層1522、-銅層1523、-錄層1524及-金層1525所構成，黏著/阻 障層1522比如係直接形成在保護層14〇上(如圖卜圖2、圖6、圖1〇及圖 (14所示）、聚合物層180上(如圖3、圖7、圖u及圖15所示）或頂層之薄 膜線路137上(如圖4、圖5、圖8、圖9、圖12及圖13所示），銅層1523 係开>成在黏著/阻障層1522上，鎳層1524係形成在銅層1523上，金層1525 係形成在鎳層腿上，黏著/轉層1522之材質比如係為鈥、鈦鶴合金、 鈦氮化合物、钽或鈕氮化合物等，或者黏著/阻障層1522亦可以是藉由依 序沉積鉻層及鉻銅合金層而成，其中鉻銅合金層係位在鉻層上。頂層金屬 層1526係形成在底層金屬層1521之金層1525上，且頂層金屬層1526的 24 200814211 材貝比如係為錫錯合金、錫、錫銀合金或錫銀銅合金等之焊料，頂層金屬 層1526的厚度j2比如係大於1微#，在較佳的情況下，比如係大於5微 米。此外，半導體晶片1〇〇之凸塊16〇亦可以具有與厚金屬線路⑽相同 之如圖17所示的金屬層結構。 請參關18，齡示林發明第-實補巾基板之線路之其中一種金 屬層堆積結構的剖面示意圖。前述之基板2〇〇之線路212比如包括一底層 金屬層2111及一頂層金屬層2116,頂層金屬層2116係位在底層金屬層2ηι / 上，其中底層金屬層2111比如係由一銅層2112及一鎳層2113所構成，銅 層2112比如係位在基板2〇〇之絕緣層上，鎳層2113係位在銅層2112上。 頂層金屬層2116係位在底層金屬層2111之鎳層2113上，且頂層金屬層2116 的材質比如係為金。此外，基板2〇〇之接墊214亦可以具有與基板2〇〇之 線路212相同之如圖18所示的金屬層結構。 明參照圖19，其纷示在本發明第一實施例中基板之線路之其中一種金 屬層堆積結構的剖面示意圖。前述之基板200之線路212比如包括一底層 : 金屬層2121及一頂層金屬層2126，頂層金屬層2126係位在底層金屬層2121 上，其中底層金屬層2121比如係由一銅層2122、一鎳層2123及一金層2124 所構成，銅層2122比如係位在基板200之絕緣層上，鎳層2123係位在銅 層2122上，金層2124係位在鎳層2123上。頂層金屬層2126係位在底層 金屬層2121之金層2124上，且頂層金屬層2126的材質比如係為錫鉛合金、 錫、錫銀合金或錫銀銅合金之焊料，其中頂層金屬層2126比如可以利用電 鍍的方式形成在底層金屬層2121之金層2124上；或者，頂層金屬層2126 25 200814211 亦可以是由貧狀焊料經由迴焊步驟固化而成，亦即可以先利用網板印刷的 方式形成貧狀焊料(未繪示)於基板测之底層金屬層2121之金層2124上， 之後半導體晶# 1G0之厚金屬線路15〇可以與此膏轉料連接，接著經由 迴焊的步驟可以形成_狀的焊料2126於底層金屬層2121之金層2124 上，如此透過焊料2126可以連接半導體晶片100之厚金屬線路15〇與基板 200之底層金屬層2121之金層2124。此外，基板200之接墊214亦可以具 有與基板200之線路212相同之如圖19所示的金屬層結構。 清參照圖20，其繪示在本發明第一實施例中基板之線路之其中一種金 屬層堆積結構的剖面示意圖。前述之基板2〇〇之線路212比如包括一底層 金屬層2131及-頂層金屬層·，頂層金屬層2136係位在底層金屬層· 上，其中底層金屬層2131比如係包括銅，且位在基板2〇〇之絕緣層上。頂 層金屬層2136的材質比如係為錫鉛合金、錫、錫銀合金或錫銀銅合金之焊 料’其中頂層金屬層2136比如可以利用電鍍的方式形成在底層金屬層213i 上，或者，頂層金屬層2136亦可以是由膏狀焊料經由迴焊步驟固化而成， ^ 亦即可以先利用網板印刷的方式形成膏狀焊料(未繪示)於基板2〇〇之底層 金屬層2131上，之後半導體晶片1〇〇之厚金屬線路15〇可以與此膏狀焊料 連接，接著經由迴焊的步驟可以形成固體狀的焊料2136於底層金屬層2131 上，如此透過焊料2136可以連接半導體晶片100之厚金屬線路15〇與基板 200之底層金屬層2131。此外，基板200之接墊214亦可以具有與基板200 之線路212相同之如圖20所示的金屬層結構。 在本發明中，半導體晶片100之厚金屬線路15〇與基板2〇〇之線路212 26 200814211 的連接方狀社可骑為__，第_種絲金金純接合的方式， 亦即半導體晶片廳之厚金屬線路15G之頂層金屬層的材質係為金，雜 測之線路212之頂層金屬層的材質亦係為金，當半導體晶片議與基板 200在接合時，半導體晶片100之厚金屬線路15〇的頂層金屬層可以透過金 -金共晶接合的方式連接基板200之線路212的頂層金屬層，例如半導體晶 片100之厚金屬線路150係具有如圖16所示之金屬層結構，基板2〇〇之線 路212係具有如圖18所示之金屬層結構，此時半導體晶片雇之厚金屬線 路150之頂層金屬層1516的材質與基板之線路212之頂層金屬層_ 的材質均係為金，當半導體晶片⑽之厚金屬線路⑽與基板之線路 212接合時，半導體晶片100之厚金屬線路15〇之頂層金屬層刪係利用 金-金共金接合的方式接合基板200之線路212之頂層金屬層2116。 第二種係為焊接接合的方式，亦即半導體晶片之厚金屬線路⑽ 之頂層金屬層的材質係為焊料，當半導體晶片⑽與基板腳在接合時， 半導體晶片10G之厚金屬線路⑽的頂層金屬層可以透過焊接接合的方式 連接基板200之線路212。例如，半導體晶片1〇〇之厚金屬線路15〇係具有 如圖17所示之金屬層結構，此時半導體晶片期之厚金屬線路15〇之頂層 金屬層1526的材質係為焊料，當半導體晶片應之厚金屬線路15〇與基板 200之線路212接合時，半導體晶片1〇〇之厚金屬線路15〇之頂層金屬層 1526係利用焊接接合的方式接合基板2〇〇之線路2i2。 或者，亦可以是基板200之線路212之頂層金屬層的材質係為焊料， 當半導體晶片1GQ與基板2GG在接合時，半導體晶片⑽之厚金屬線路15〇 27 200814211 可以透過焊接接合的方式連接基板之線路212之頂層金屬層。例如， 基板200之線路212係具有如圖19或圖2〇所示之金屬層結構，此時基板 2〇〇之線路212之頂層金屬層2126或2136的材質係為禪料，當半導體晶片 1〇〇之厚金屬線路15〇與基板测之線路212接合時，半導體晶片⑽之厚 金屬線路150係利用焊接接合的方式接合基板·之線路212之頂層金屬 層2126或2136 ’若是半導體晶片⑽之厚金屬線路15〇係如圖16所示， 其頂層金屬層1516係為甚厚的金層，則在較佳的情況下，基板⑽之線路 212之頂層金屬層2126或2136比如係為厚度甚薄的錫層。 或者，亦可以是半導體晶片謂之厚金屬線路⑽之頂層金屬層的材 貝與基板200之線路212之頂層金屬層的材質均係為焊料，當半導體晶片 K、基板200在接合時，半導體晶片1〇〇之厚金屬線路15〇之頂層金屬層 可以透過焊接接合的方式連接基板測之線路212之頂層金屬層。例如， 半導體晶片100之厚金屬線路15〇係具有如圖17所示之金屬層結構，基板 200之線路212係具有如圖19或圖20所示之金屬層結構，此時半導體晶片 1〇〇之厚金屬線路150之頂層金屬層1526的材質與基板之線路批之 頂層金屬層2126或2136的材質均係為焊料，當半導體晶片之厚金屬 線路150與基板200之線路212接合時，半導體晶片100之厚金屬線路15〇 之頂層金屬層1526係利用焊接接合的方式接合基板2〇〇之線路212之頂層 金屬層2126或2136。 二、晶片構裝之第二實施例 半導體晶片100之厚金屬線路150除了上述可以用於與基板2〇〇之線 28 200814211 路212直接接觸地連接，然而半導體晶片1〇〇之厚金屬線路⑽亦可以與 另一半導體晶片300之厚金屬線路350直接接觸地連接，如圖21至圖47 所示，其巾半雜晶請之轉及材f在第__實齡盡的敘述， 在此便不再贅述。以下配合圖示，舉出數種實施可能情形： 1·二半導體晶片之相互連接的二厚金屬線路係作為其中—半導體晶片 内之訊號傳輸之用 請先參關21及® 22，其帽21 _依照本剌第二實施例之晶片 構裝在組裝前二半導體晶片的剖面示意圖，其中切過二半導體晶片之厚金 屬線路的剖面部分係分別沿著二厚金屬線路的延伸路徑作垂直切過對應之 半導體晶片的剖面而得；圖22繪示圖21中二半導體晶片接合後之晶片構 裝的剖面示意圖。 請參照® 21，半導體晶片300包括一半_基底、多數層薄膜介 電層322、324、326、多數層薄膜線路層332、334、336及一保護層340。 半導體基底310具有多數個電子元件312，電子元件312係配設於半導體基 底310之一主動表面314的表層，其中半導體基底310比如是矽基底，透 過摻雜五價或三價的離子，比如是硼離子或磷離子，藉以形成多個電子元 件312於半導體基底31〇之表層，電子元件312比如是金屬氧化物半導體 或電晶體等。 利用化學氣向沉積的方式，可以形成多層之薄膜介電層322、324、326 在半導體基底310之主動表面314上，其中薄膜介電層322、324、326比 如是氧矽化合物、氮矽化合物或氮氧矽化合物等，每一薄膜線路層332、 29 200814211 334、336係分別配置於其中一薄膜介電層322、324、326上，其中薄膜線 路層332、334、336的材質比如包括紹、銅或矽等。薄膜介電層322、324、 326具有多數個導通孔32卜323、325，薄膜線路層332、334、336可以藉 由薄膜介電層322、324、326之導通孔321、323、325彼此電性連接，並 電性連接至電子元件312。 保護層340係配置於薄膜介電層322、324、326與薄膜線路層332、334、 336上，其中保護層340的厚度z比如係大於〇· 35微米，且保護層340的 結構比如係為一氮矽化合物層、一氧矽化合物層、一磷矽玻璃層或至少一 上述材質所構成的複合層。保護層34〇具有多數個開口 342，暴露出位在頂 層之薄膜線路層336。 厚金屬線路350係位於保護層340上，且經由保護層34〇之開口料2 電性連接於薄膜線路層336，其中厚金屬線路咖的厚度係大於薄膜線路層 332、334、336的厚度。接墊係大致上對準保護層340之開口 342，並 電f生連接於_線路層336。在製程上，厚金屬線路與接塾調可以是 利用相同的製綱時完成，因此厚金屬線路與接墊删可以具有相同 的金屬層π構’厚金屬線路與接墊編的金屬層結構在後文有詳細地 說明，在此先跳過。值得注意的是，厚金屬線路咖的厚们係大致上相 R於接墊36G之厚度Η，其中厚金屬線路35()的厚度塊編之厚度η 比如係大於1微米，在較佳的情況下，比如係大於5微米。 ^ , 1〇〇 . 3〇〇 ^ 15〇 ^ 35〇 了疋/口著任何方向分別在半導體晶片1()()、咖之頂部延伸，比如是類似 200814211 直線延伸的形式、 徑。在健崎灯，、二物料敲具林_之凹折料的延伸路 間係呈現鏡射的關係，贿=片細、細之厚金屬線路劃50之 100之^^ 传導體晶在接合時，半導體晶片 路150可以對準半導體晶片300之厚金屬線路350。 .照圖22 ’在提供二半導體晶請、咖之後，可以進行接合的步 驟，使得半導體晶請之厚金屬線路⑽可以直接接觸地連接半導體晶 片之厚金屬線路35〇’且半導體晶片⑽之凸塊⑽可以直接接觸地連 接半導體晶_之接墊秦接著，可以填入一聚合物層m於二半導體 晶片⑽、之間，聚合物層_包覆厚金屬線謂、的周圍， 並且還包覆凸塊⑽及接塾36G的。定義—平面麵，係大致上平行 於半導體基底110之主絲面114，其中二厚金屬線路⑽咖連接的區 _影至平© _上的延伸_ s比如是大於_鄕，或者比如是大於 800微米，或者比如是大於12〇〇微米；二厚金屬線路15〇、連接的區域 投影至平面1000上的面積比如係大於3〇,咖平方微米，或者比如是大於 80, 000平方微米，或者比如是大於15〇, 〇〇〇平方微米。 本實施例中，半導體晶片100、300之厚金屬線路150、350間的連接 關係係雷同於第一實施例中半導體晶片100之厚金屬線路15〇與基板2〇〇 之線路212間的連接關係，相關更詳盡的說明，可以參考在第一實施例中 所舉出的半導體晶片100之厚金屬線路150與基板200之線路212係為電 感元件的實施例，若是參考此部伤的說明’將會對本實施例中半導體晶片 100、300之厚金屬線路150、350的連接關係有更清楚的瞭解。 31 200814211 請參照圖22，在電性傳輸上，半導體晶片1〇〇内之電子元件112的其 中-個（比如疋電子το件112a)係適於輪出一電子訊號，此電子訊號經由薄 膜線路層132、134、136並穿過保護層14〇後，傳輸至厚金屬 線路 150、350, 接著再穿過保護層140，並經由薄膜線路層136、134、132傳輸至半導體晶 片100狀其他的電子元件112之至少其中一個（比如是電子元件㈣）； 此時，半導體晶片100之厚金屬線路15G與半導體晶片之厚金屬線路 350可以作為半導體晶片1〇〇内之訊號傳輪之用。另外，此電子訊號在從電 子元件112a傳輸至厚金屬線路15〇、後，還可以傳輸至半導體晶片3〇〇 内’比如疋牙過保護層340並經由薄膜線路層336、334、微傳輸至電子 兀件312a，此時’半導體晶片1〇〇之厚金屬線路15〇與半導體晶片綱之 厚金屬線路350亦可以作為二半導體晶片⑽、_之訊號傳n 另外-月參知、圖22,半導體晶片3〇〇内之電子元件312的其中一個（比 如疋電子兀件312a)亦適於輸出一電子訊號，此電子訊號經由薄膜線路層 332、334、咖並穿過保護請後，傳輸至厚金屬線請、⑽，接著 再穿過半導體晶片⑽之保護層⑽，並經由薄膜線路層136、134、麵 輸至半導體晶片⑽内之至少一電子元件112(比如是電子元件論及 112b) 斤述半導體阳片100之厚金屬線路15〇與半導體晶片剔之厚 金屬線路350除了可以作為電子訊號的橫向傳輸之外，還可以作為二半導 亩體I0,間的縱向傳輪。由於半導體晶請之厚金屬線路_ 直接接觸地連接半導體晶片_之厚金屬線路35〇，因此半導體晶片細之 32 200814211 厚金屬線路150可以大面積地電性連接半導體晶片3〇〇之厚金屬線路35〇， 如此可以大幅地增加二半導體晶；^ _、震間電性連接的效能，且可以減 少雜訊的產生。 此外，請參照圖22,透過半導體晶片1〇〇之凸塊16〇與半導體晶片_ 之接墊360，半導體晶片1〇〇可以傳送電子訊號至半導體晶片珊，或是可 以接收由半導體晶片300所傳來的電子訊號。 在圖21及圖22中，厚金屬線路15〇、35請分別直接形成在保護層. 340上；然而，厚金屬線路15〇、亦可以是分別形成在位於保護層⑽、 340上之聚合物層上，·或者，亦可以是厚金屬線路35〇形成在位於保護層 340上之聚合物層上，而厚金屬線路15〇係直接形成在保護層14〇上；或者， 亦可以是厚金麟路150形成在位於保護層14()上之聚合物紅，而厚金 屬線路係直接形成在保護層34〇上，如圖23所示，其緣示依照本發明 第-實施例之另-種晶片構袭的剖面示意圖。在此僅繪示出上述其中一種 之厚金屬線路配置於聚合物層上的實施例，其他未繪示之厚金屬線路配置 於聚合物層上的結構’均可依照圖8之厚金屬線職置於聚合物層上的結 構以此類推。 請參照圖23，-聚合物層⑽係形成於保護層14〇上，聚合物層⑽ 具有多個開口 182，大致上係對準保護層⑽之開口 142，厚金屬線路15〇 係形成於聚合物層180上，並且經由聚合物層⑽之開口 182及保護層⑽ 之開口 142連接至薄膜線路層136。厚金屬線路35〇係直接接觸地形成在保 遵層340上，亚且經由保護層34〇之開口 342連接至薄膜線路層咖。值得 33 200814211 注意的是，突出於聚合物層180之開口 i82外的凸塊160之厚度h比如是 大致上相同於位在聚合物層180上之厚金屬線路150的厚度j,且厚金屬線 路150與凸塊160係具有相同的金屬層結構，其中突出於聚合物層18〇之 開口 182外的凸塊160之厚度h與位在聚合物層180上之厚金屬線路150 的厚度j比如係大於1微米，在較佳的情況下，比如係大於5微米。聚合 物層180的厚度k比如係大於1微米，且聚合物層180的材質比如是聚亞 醢胺(polyimide，PI)、苯基環丁烯(benzoCyCi〇butene，BCB)、聚芳香基 醚(parylene)、多孔性介電材質或彈性體等。 在圖21至圖23中，厚金屬線路150、35〇係透過保護層ι4〇、34〇之 小開口 142、342小面積地連接頂層的薄膜線路層136、336 ;然而，厚金屬 線路150、350亦可以是透過保護層14〇、34〇之大開口 m2、342大面積地 連接頂層的薄膜線路層136、336，包括下列可能實施情形。第—種實施情 形·厚金屬線路150係小面積地連接頂層的薄膜線路層136，厚金屬線路 350係大面積地連接頂層的薄膜線路層咖；第二種實施情形：厚金屬線路 150係大面積地連接頂層的薄膜線路層136，厚金屬線路35〇係小面積地連 接頂層的薄麟路層咖，如圖24及圖25所示；第三種實施情形·厚金屬 線路150、350均係分別大面積地連接頂層的薄膜線路層136、娜，如圖 26及圖27所示。在此僅繪示出第二種實施情形與第三種實施情形，而未繪 示之第-種實施情形可以依照圖24至圖27之厚金屬線路大痛地連接頂 層的薄膜線路層之結構以此類推。 請參照圖24至圖27，在半導體晶片謂中，頂層的薄膜線路層136具 34 200814211 有-薄膜線路137,保護層140之開口 142係大面積地暴露出薄膜線路137, 使得厚金屬線路150可以大面積地連接保護層140之開口 142所暴露出的 薄膜線路137。定義-平面1〇〇〇，此平面麵係大致上平行於半導體基底 110之主動表面114，厚金屬線路15〇與薄膜線路137連接的區域投影至此 平面1000上的面積除以薄膜線路137鄕至此平面1〇〇〇上的面積之比值 比如係大於0· 5，或者比如係大於〇· 8，或者比如係大致上等於卜保護層 140之開口 142暴露出薄膜、線路137的面積比如係大於3〇,麵平方微米， 或者比如係大於80, 000平方微米，或者比如係大於15〇，咖平方微米。厚 金屬線路150與薄膜線路層136連接的區域投影至此平面1〇〇〇上的延伸距 離t比如係大於500微米，或者比如係大於8〇〇微米，或者比如係大於· 微米。 在本實施例中，圖24至圖27所示之半導體晶片謂之厚金屬線路15〇 與薄膜線路137間的連接關係猶同於第—實施例中圖4至圖5所示之半 導體晶片100之厚金屬線路15〇與薄膜線路137間的連接關係，相關更詳 盡的祝明’可以參考在第一實施例中所舉出的半導體晶片1〇〇之厚金屬線 路150與薄膜線路137係為電感元件的實施例，若是參考此部份的說明， 將會對本貝知例中半導體晶片⑽之厚金屬線路⑽與薄膜線路⑶間的 連接關係有更清楚的瞭解。 另外’除了上述厚金屬線路15Q可以大面積地連接頂層之薄膜線路層 136外，厚金屬線路35〇亦可以大面積地連接頂層之薄膜線路層犯6，如圖 26及圖27所示。頂層的薄膜線路層336具有一薄膜線路337，保護層34() 35 200814211 之開口 342係大面積地暴露出薄膜線路337，使得厚金屬線路35〇可以大面 積地連接保護層340之開口 342所暴露出的薄膜線路337。定義一平面 _，此平面1050係大致上平行於半導體基底310之主動表面314，厚金 屬線路350與薄膜線路337連接的區域投影至此平面1〇5〇上的面積除以薄 膜線路337投影至此平面·上的面積之比值比如係大於〇· 5，或者比如 係大於0· 8，或者比如係大致上等於卜保護層34〇之開口 342暴露出薄膜 線路337的面積比如係大於3〇,咖平方微米，或者比如係大於8〇，咖平 方微米，或者比如係大於150,000平方微米。厚金屬線路與薄膜線路 層336連接的區域投影至此平面麵上的延伸距離τ比如係大於圓微 米，或者比如係大於_微米，或者比如係大於12〇〇微米。 本實施例中圖26及圖27所示之半導體晶片3〇〇之厚金屬線路35〇與 薄膜線路337 _連接關係係雷同於第一實施例中圖4至圖5所示之半導 體晶片100之厚金屬線路150與薄膜線路137間的連接關係，相關更詳盡 的說明，可以參考在第-實施例中所舉出的半導體晶片⑽之厚金屬線路 與薄膜線路137係為電感元件的實施例，若是參考此部份的說明，將會 對本實施例中半導體晶片綱之厚金屬線路與薄膜線路挪間的雜 關係有更清楚的瞭解。 請參照圖24及圖25，在電性傳輸上，半導體晶片1〇〇内之電子元件 112的其中一個（比如是電子元件_係、適於輸出—電子訊號，此電子訊 號經由薄膜線路層132、134，傳輸至薄膜線路13?及厚金屬線路15〇、35〇， 接著再經由薄膜線路層m、132傳輪至半導體晶片⑽内之其他的電子元 36 200814211 件112之至少其中一個（比如是電子元件U2b);此時，半導體晶片1〇〇之 厚金屬線路150與半導體晶片300之厚金屬線路350可以作為半導體晶片 1〇〇内之訊號傳輸之用。另外，此電子訊號在從電子元件112a傳輸至薄膜 線路137及厚金屬線路150、350後，還可以傳輸至半導體晶片内，比 如是穿過保護層340並經由薄膜線路層336、334、332傳輸至電子元件 312a ;此時，半導體晶片100之厚金屬線路15〇與半導體晶片3〇〇之厚金 屬線路350亦可以作為二半導體晶片1〇〇、3〇〇間之訊號傳輸之用。 另外，清參照圖24及圖25，半導體晶片3〇〇内之電子元件312的其中 -個（比如是電子元件312a)輯於輸出―電子訊號，此電子城係經由薄 膜線路層332、334、336，並穿過保護層34〇傳輸至厚金屬線路35〇、15〇 及薄膜線路137，接著再經由薄膜線路層134、132傳輸至半導體晶片1〇〇 内之至少一電子元件112(比如是電子元件112a、U2b)。 圖24與圖25的不同點是在於半導體晶片1〇〇是否有配置聚合物層18〇 在保護層140上，其中隨及圖25之半導體晶片⑽之轉係分別雷同 於第-實施例中圖4及圖5之半導體晶片⑽之結構，在此便不再贅述。 請參照圖26及圖27，在電性傳輸上，半導體晶片1〇〇内之電子元件 112的其巾-錄如是電子元件咖係適於輸出—電子訊號 ，此電子訊 〜由薄膜線路層132、134，傳輸至薄膜線路⑶、厚金屬線路⑽、a% 蓴、線路337，接著再經由薄膜線路層134、132傳輸至半導體晶片綱 、，二的電子元件112之至少其中一個（比如是電子元件112b);此時， 半^體曰曰片100之厚金屬線路15〇與半導體晶片3〇〇之厚金屬線路娜可 37 200814211 以作為半導體晶片100内之訊號傳輸之用。另外，此電子訊號在從電子元 件112a傳輸至薄膜線路137、厚金屬線路15〇、35〇及薄膜線路337後，還 可以傳輪至半導體晶片300内，比如是經由薄膜線路廣334、332傳輪至電 子元件312a ;此時，半導體晶片1〇〇之厚金屬線路150與半導體晶片3〇〇 之厚金屬線路350亦可以作為二半導體晶片ι〇〇、3〇〇間之訊號傳輸之用。 另外，請參照圖26及圖27，半導體晶片300内之電子元件312的其中 一個（比如是電子元件312a)亦適於輸出一電子訊號，此電子訊號係經由薄 膜線路層332、334傳輸至薄膜線路337、厚金屬線路350、150及薄膜線路 137 ,接著再經由薄膜線路層134、132傳輸至半導體晶片1〇〇内之至少一 電子元件112(比如是電子元件H2a、H2b)。 圖26與圖27的不同點是在於半導體晶片1〇〇、3〇〇是否有配置聚合物 層180、380在保護層140、340上，其中圖26及圖27之半導體晶片1〇〇 之結構係分別雷同於第一實施例中圖4及圖5之半導體晶片1〇〇之結構， 在此便不再贅述。 請參照圖26，半導體晶片300在形成保護層34〇之後，接著係同時形 成厚金屬線路350及接墊360於薄膜線路層336上，其中接墊36〇的厚度H 比如是大致上相同於厚金屬線路350的厚度j，且接墊36〇的金屬層結構係 大致上相同於厚金屬線路350的金屬層結構，其中接墊3⑼之厚度{{與厚 金屬線路350之厚度J比如係大於1微米，在較佳的情況下，比如係大於5 微米。 然而，請參照圖27 ,半導體晶片300在形成保護層34〇之後，還形成 38 200814211 圖案化之一聚合物層380於保護層340上，聚合物層380的厚度κ比如係 大於1微米，且聚合物層380的材質比如是聚亞醯胺(poiyimide，pi)、苯 基環丁烯(benzocyclobutene，BCB)、聚亞芳香基醚(paryiene) '多孔性介 電材質或彈性體等。聚合物層380具有一開口 382，暴露出頂層之薄膜線路 層336，其中包括暴露出薄膜線路337。接著，可以同時形成厚金屬線路35〇 及接墊360於薄膜線路層336上，其中突出於聚合物層38〇之開口 3犯外 的接墊360之厚度Η比如是大致上相同於突出於聚合物層38〇之開口 3犯 外的厚金屬線路350的厚度J，且接墊360的金屬層結構係大致上相同於厚 金屬線路350的金屬層結構，其中突出於聚合物層38〇之開口 3犯外的接 墊360之厚度Η比如係大於1微米，在較佳的情況下，比如係大於5微米； 突出於聚合物層之開π 382外的厚金屬線路·之厚度；比如係大於【 微米’在較佳的情況下，比如係大於5微米。 2·二半導體晶片之相互連接的二厚金屬線路係作為二半導體晶片間之 訊號傳輸之用。 凊參照圖28至圖33，其緣示依照本發明第二實施例之另一類型晶片 構裝的剖面示意圖，其中圖28至圖33之半導體晶片⑽係分別雷同於圖 22至圖27之半導體晶片100,且圖沈至圖犯之半導體晶片咖係分別雷 同於圖22至圖27之半導體晶片·，在此便不再贅述；惟不同點係在於半 _>u〇〇' 15G、35()懈科输j 應、綱 間之訊號傳輸之用，而不作為半導體晶片⑽内之訊麟輪之用，如下所 述。 39 200814211 请參照圖28及圖29，在電性傳輸上，半導體晶片1〇〇内之電子 元件112的其中一個（比如是電子元件U2a)係適於輸出一電子訊號， 此電子訊號經由薄膜線路層132 ' 134、136並穿過保護層14〇後，傳 輸至半導體晶片100、300之厚金屬線路150、350 ,接著穿過半導體 晶片300之保護層340，並且經由薄膜線路層336、334、332傳輸至 半導體晶片300内之電子元件312的其中一個（比如是電子元件 312a)。或者，半導體晶片300内之電子元件312的其中一個（比如是 電子元件312a)亦可以適於輸出一電子訊號，此電子訊號經由薄膜線 路層332、334、336並穿過保護層340後，傳輸至半導體晶片300、 100之厚金屬線路350、150,接著穿過半導體晶片1〇〇之保護層14〇， 並且經由薄膜線路層136、134、132傳輸至半導體晶片1〇〇内之電子 元件112的其中一個（比如是電子元件n2a)。此時，半導體晶片1〇〇、 300之厚金屬線路150、350係作為半導體晶片1〇〇、3〇〇間之訊號傳輸之 用。 凊參照圖30及圖31，在電性傳輸上，半導體晶片内之電子 兀件112的其中一個（比如是電子元件112a)係適於輸出一電子訊號， 此電子訊號經由薄膜線路層132、134傳輸至薄膜線路137及半導體晶 片100、300之厚金屬線路150、35〇，接著穿過半導體晶片3〇〇之保 護層340,並且經由薄膜線路層336、334、332傳輸至半導體晶片3〇〇 内之電子元件312的其中一個（比如是電子元件312a)。或者，半導體 晶片300内之電子元件312的其中一個（比如是電子元件312a)亦可以 200814211 適於輸出一電子訊號，此電子訊號經由薄膜線路層332、334、336並 穿過保護層340後，傳輸至半導體晶片300、1〇〇之厚金屬線路35〇、 150及薄膜線路137，接著經由薄膜線路層134、132傳輸至半導體晶 片100内之電子元件112的其中一個（比如是電子元件U2a)。此時， 半導體晶片100、300之厚金屬線路150、350係作為半導體晶片1〇〇、 300間之訊號傳輸之用。 睛參照圖32及圖33，在電性傳輸上，半導體晶片内之電子 元件112的其中一個（比如是電子元件112a)係適於輸出一電子訊號， 此電子訊5虎經由薄膜線路層132、134傳輸至薄膜線路I”、半導體晶 片100、300之厚金屬線路150、350及薄膜線路337，接著經由薄膜 線路層334、332傳輸至半導體晶片300内之電子元件312的其中一個 (比如疋電子元件312a)。或者，半導體晶片3〇〇内之電子元件gig的 其中-個（比如是電子元件312a)亦可以適讀出—電子訊號，此電子 訊號經由薄膜線路層332、334傳輸至薄膜線路336、半導體晶片3〇〇、 1〇〇之厚金屬線路350、150及薄膜線路137,接著經由薄膜線路層134、 132傳輸至半導體晶片應内之電子元件112的其中-個（比如是電子 几件112a)。此時，半導體晶片1〇〇、3〇〇之厚金屬線路15〇、35〇係 作為半導體晶片100、300間之訊號傳輸之用。 如上所述，半導體晶片1〇〇、300之厚金屬線路15〇、35〇除了可 以作為電子訊號的橫向傳輸之外，還可以作為半導體晶片1〇〇、綱間 的縱向傳輸。由於半導體晶片1GG之厚金屬線路⑽係直接接觸地連 200814211 接半導體晶片3GG之厚金屬線路35G，因此半導體晶片咖之厚金屬 線路150可以大面積地電性連接半導體晶片3〇〇之厚金屬線路35〇， 如此可以大幅地增加半導體晶片1〇〇、3〇〇間電性連接的效能，且可以 減少雜訊的產生。 此外，請參照圖28至圖33，透過半導體晶片1〇〇之凸塊16〇與 半導體晶片300之接墊360，半導體晶片1〇〇可以傳送電子訊號至半 導體晶片300’或是可以接收由半導體晶片3〇〇所傳來的電子訊號。 3.—半V體⑼之相互連接的二厚金屬線路係作為電雜流排或 接地匯流排之用 請參照圖34至圖39，其繪示依照本發明第二實施例之另一類型 晶片構裝的剖面示意圖，其中圖34至圖39之半導體晶片⑽係分別 田同於圖22至圖27之半導體晶片1〇〇，且圖34至圖39之半導體晶 片300係雷同於圖22至圖27之半導體晶片細，在此便不再贊述； 准不同點係在於半導體晶片1〇〇、_之厚金屬線路⑽湖係作為 " 電源匯流排或接地匯流排之用，如下所述。 請參照圖34至圖39，當半導體晶片⑽、綱之厚金屬線路15〇、 咖係作為電源匯流排時，半導體晶片1〇〇、之厚金屬線路15〇、 350係電性連接至半導體晶片⑽内之電源匯流排I%，比如係由薄膜 線路層134提供之，並且還電性連接至半導體晶片綱内之電源匯流 5比如係由薄膜線路層334提供之。由於半導體晶片1〇〇之厚 金屬線路150係大面積直接接觸地連接半導體晶片綱之厚金屬線路 42 200814211 350 ’且電性連接至半導體晶片1GG、3GG内之電源匯流排135、335， 如此可以減J半導體晶片⑽、綱之電源匯流排娜、娜因爲受到 訊號干擾而產生電壓變化的程度，並对導體晶片 100、300可以提供 較為穩定之電源電壓。 明參關34至圖39,當半導體晶片1〇〇、3〇〇之厚金屬線路15〇、 係作為接地匯机排時，半導體晶片則、綱之厚金屬線路⑽、 350係電性連接至半導體晶片1⑽内之接地匯流排 135 ’比如係由薄膜 線路層134提供之，並且還電性連接至半導體晶片·内之接地匯流 排335，比如係由薄膜線路層334提供之。祕半導體晶片⑽之厚 金屬線路150係大面積直接接觸地連接半導體晶片3⑽之厚金屬線路 且電性連接至半導體晶片丨⑼、3⑽内之接地匯流排135、咖， 如此可以減4半導體晶片丨⑽、咖之接地匯流排135、娜因爲受到 訊號干擾而產生電壓變化的程度，並且半導體晶片⑽、咖可以提供 較為穩定之接地電壓。 4.二半導體晶片之相互連接的二厚金屬線路係作為其中一半導體 晶片内之訊號傳輸之用 明參圖40至圖43，其繪示依照本發明第二實施例之另一類型 晶片構裝的剖面示意圖’其中圖4〇與圖42之半導體晶片議係雷同 於圖22之半導體晶片1〇。’圖41與圖43之半導體晶片⑽係雷同於 圖23之半導體晶片議，且圖4〇舆圖4ι之半導體晶片綱係雷同於 圖22之半導體晶片3GG’圖42與圖43之半導體晶片_係雷同於圖 43 200814211 26之半導體晶片3〇〇，在此便不再贅述；惟不同點係在於半導體晶片 1〇〇之厚金屬線路150係與半導體晶片100内之薄膜線路層132、134、 136之間呈現電性斷路的狀態，且半導體晶片1〇〇、3〇〇之厚金屬線路 150、350係作為半導體晶片3〇〇内之訊號傳輸之用，如下所述。 請參照圖40至圖43,當半導體晶片1〇〇、300之厚金屬線路15〇、 350係作為半導體晶片3〇〇内之訊號傳輸之用時，半導體晶片3⑽内 之電子元件312的其中一個（比如是電子元件312a)係適於輸出一電子 訊號，此電子訊號經由薄膜線路層332、334、336並穿過保護層34〇 後，傳輸至半導體晶片300、100之厚金屬線路350、150，接著再穿 過保護層340，並經由薄膜線路層336、334、332傳輸至半導體晶片 3〇〇内之其他的電子元件312之至少其中一個（比如是電子元件 312b);其中此電子訊號並不經由半導體晶片3〇〇、1〇〇之厚金屬線路 35〇、150直接地傳輸至半導體晶片1〇〇内。此時，半導體晶片1〇〇之 厚金屬線路150與半導體晶片300之厚金屬線路350可以作為半導體 晶片300内之訊號傳輸之用，而不作為半導體晶片100内之訊號傳輸 之用或是半導體晶片100、300間之訊號傳輸之用。由於半導體晶片 i〇〇之厚金屬線路150係直接接觸地連接半導體晶片300之厚金屬線 路350，因此半導體晶片100之厚金屬線路150可以大面積地電性連 接半導體晶片300之厚金屬線路350 ’如此可以增加此電子訊號的電 性傳輪品質。 5·二半導體晶片之相互連接的二厚金屬線路係作為其中一半導體 44 200814211 晶片之電源g麵或接地匯流排之用 °月'知圖44至圖47，其㈣依照本發明第-實施例之另一類型 晶片構裝的剖面示意圖，其中圖44與圖46之半導體晶請係雷同 於圖22之半導體晶片咖’圖奶與圖47之半導體晶片⑽係雷同於 圖23之半導體晶請，且圖4()與圖41之半導體晶片_係雷同於 ㈣至圖37之半導體晶請，圖42與圖43之半導體晶片細係 雷同於圖38與圖39之半導體晶片3〇〇，在此便不再贊述；惟不同點 係在於半導體晶片議之厚金屬線路⑽係與半導體晶片⑽内之薄 膜線路層132、134、136之間呈現概斷路驗態，且轉體晶片刚、 300之厚金屬線路15〇、咖係作為半導體晶片_之電源匯流排或接 地匯流排之用’如下所述。 請參關44至圖47，當半導體晶片100之厚金屬線路15〇作為 半導體晶片300之電源匯流排時，半導體晶片i⑼、綱之厚金屬線路 150、350 _於電性連接半導體晶片3〇〇内之電源匯流排335，電源 匯流排335比如是由半導體晶片300之薄膜線路層334提供之，其中 半導體晶片100、300之厚金屬線路15〇、350係與半導體晶片1〇〇内 之電源匯流排之間呈現電性斷路。由於半導體晶片1〇〇之厚金屬線路 150係直接接觸地連接半導體晶片300之厚金屬線路350，且電性連接 至半導體晶片300内之電源匯流排335 ’如此可以減少半導體晶片3〇〇 之電源匯流排335因爲受到訊號干擾而產生電屢變化的程度，並且半 導體晶片300可以提供較為穩定之電源電壓。 45 200814211 口月“、、圖44至圖47，當半導體晶片1〇〇之厚金屬線路15〇作為 半導體晶片300之接地匯流排時，半導體晶片1〇〇、3〇〇之厚金屬線路 150、350係適於電性連接半導體晶片細内之接地匯流排，接地 匯流排335 t匕如是由半導體晶片3〇〇之薄膜線路層334提供之，其中 半導體晶片1G0、3GG之厚金屬線路15〇、係與半導體晶片1〇〇内 之接地匯流排之間呈現電性斷路。由於半導體晶片剛之厚金屬線路 150係直接接觸地連接半導體晶片3〇〇之厚金屬線路35〇，且電性連接 至半導體晶片300内之接地匯流排335,如此可以減少半導體晶片3〇〇 之接地匯流排335因爲受到訊號干擾而產生電壓變化的程度，並且半 導體晶片300可以提供較為穩定之接地電壓。 6·二半導體晶片之相互連接的二厚金屬線路之金屬層結構 在本實施例中，關於半導體晶片1〇〇之厚金屬線路15〇係比如具 有在第一實施例中如圖16或圖17所述之金屬層結構，在此便不再贅 述。 請參照圖48,其繪示在本發明第二實施例中半導體晶片3〇〇之厚 金屬線路350之其中一種金屬層堆積結構的剖面示意圖。半導體晶片 300之厚金屬線路350比如包括一底層金屬層3511及一頂層金屬層 3516,底層金屬層3511比如係直接形成在保護層340上（如圖21至圖 25、圖28至圖31、圖34至圖37、圖40、圖41、圖44及圖45所示） 或頂層之薄膜線路337上（如圖26、圖27、圖32、圖33、圖38、圖 39、圖42、圖43、圖46及圖47所示），頂層金屬層3516係位在底層 46 200814211 金屬層3511上，其中底層金屬層3511之材質比如係為敛鶴合金、欽 氮化合物、组或组氮化合物等，頂層金屬層3516的材質比如係為金， 頂層金屬層3516的厚度J1比如係大於！微米，在較佳的情況下，比 如係大於5微米。此外，半導體晶片300之接塾36〇亦可以具有與厚 金屬線路350相同之如圖48所示的金屬層結構。 請參關49,麟示在本發㈣二實施例中半導體晶片之厚 金屬線路350之其中-種金屬層堆積結構的剖面示意圖。半導體晶片 300之厚金屬線路比如包括一底層金屬層及一頂層金屬層 3526，頂層金屬層3526係位在底層金屬層3521上，其中底層金屬層 3521比如係由一黏著/阻障層3522、一銅層祁23、一鎳層邪24及一 金層3525所構成，黏著/阻障層3522比如係直接形成在保護層340上 (如圖21至圖25、圖28至圖31、圖34至圖37、圖40、圖41、圖44 及圖45所示）或頂層之薄膜線路337上（如圖26、圖27、圖犯、圖、 圖38、圖39、圖42、圖43、圖46及圖47所示），銅層㈣係形成 在黏著/阻障層3522上，鎳層3524係形成在銅層3523上，金層3525 係形成在制3524上，黏著/轉層3522之材f比如係為鈦、敛鶴合 金鈦氮化合物、组或组氮化合物等，或者黏著/阻障層3522亦可以 疋藉由依序沉積鉻層及鉻銅合金層而成，其中鉻銅合金層係位在鉻層 上。頂層金屬層3526係形成在底層金屬層3521之金層3525上，且頂 層金屬層3526的材質比如係為錫錯合金、錫、錫銀合金或錫銀鋼合金 等之焊料’頂層金屬層3526的厚度J2比如係大於i微米，在較佳的 47 200814211 情況下’比如係大於5微米。此外’半導體晶片之接墊36〇亦可 以具有與厚金屬，線路350相同之如圖j7所示的金屬層結構。 在本發明中，半導體晶片100、_之厚金屬線路150、350的迷 接方式大致上可以分為兩種機制’第一種係為金金共晶接合的方式， 亦即半導體晶片刚、咖之厚金屬線路、咖之頂層金屬層的材 •質係均為金，當半導體晶片100、300在接合時，半導體晶片100之厚 金屬線路15G _層金屬層可以透過金_金共晶接合的方式連接半導 體晶片300之厚金屬線路35〇的頂層金屬層，例如半導體晶片⑽之 料屬線路⑽係具有如圖16所示之金屬層結構，半導體晶片3〇〇之 厚金屬線路350係具有如圖48所示之金屬層結構，此時半導體晶片 ⑽之厚金屬線路15〇之頂層金屬層1516與半導體晶片編之厚金屬 線路350之項層金屬層3516的材質係均為金，當半導體晶片⑽之厚 金屬線路150與半導體晶片3⑼之厚金屬線路咖接合時半導體晶 片1〇〇之厚金屬線路150之頂層金屬層1516係利用金金共金接合的 方式接合半導體晶片3〇〇之厚金屬線路35〇之頂層金屬層咖。 第二種係為焊接接合的方式，亦即半導體晶片⑽之厚金屬線路 150之=層金屬層的材質係為焊料，#半導體晶片⑽、勘在接合時， “ 片之厚金屬線路的頂層金屬層可以透過焊接接合的 方姑接半導體晶片300之厚金屬線路。例如半導體晶片⑽ 之厚金屬線路150係具有如圖17所示之金屬層結構，此時半導體晶片 100之厚金屬線路⑽之頂層金屬層驗的材質係為桿料，當半導體 48 200814211 曰^⑽之厚金屬線路150與半導體晶片_之厚金屬線路咖接合 時’半導體晶請之厚金麟路15G之頂層金屬層1526係利用谭接 接合的方式接合半導體晶;ί 之厚金屬線路_。若是半導體曰片 之厚金屬線路350係如圖48所示，其頂層金屬層3516 _曰厚 的金層，則在較佳的情況下，半導體晶片⑽之厚金屬線路⑽之頂 層金屬層比如係為厚度甚薄的錫層。 或者亦可以疋半導體晶片3〇〇之厚金屬線路35〇之頂層金屬層 的材質係為焊料，當半導體晶請、_在接合時半導體晶片⑽ 之厚金屬線路⑽可以透過焊接接合的方錢接半導體晶片_之厚 金屬線路350之頂層金屬層。例如，半導體晶片之厚金屬線路删 係具有如圖49所示之金屬層結構，此時半導體晶片300之厚金屬線路 3,之項層金屬層3526的材質係為焊料當半導體晶片⑽、細之 厚=屬線路150、350接合時，半導體晶片1〇〇之厚金屬線路⑽係利 、日接接口的方式接合半導體晶片3〇〇之厚金屬線路之頂層金屬 層_。若是半導體晶片⑽之厚金屬線路150係如圖16所示’其 曰金屬層1516係為甚厚的金層，則在較佳的情況下，半導體晶片 30k厚金屬線路咖之頂層金屬層比如係為厚度甚薄的錫層。 或者亦可以疋半導體晶片1〇〇、3〇〇之厚金屬線路⑽、之 曰、’屬層的材質均係為焊料，當半導體晶片⑽、在接合時，半 導體晶片1GD之厚金屬線路150之頂層金屬層可以透過焊接接合的方 /連接半導體aa# _之厚金屬線路之職金屬層。例如，半導 49 200814211 體晶片⑽之厚金屬線路150係具有如圖17所示之金屬層結構，半導 體晶片剔之厚金屬線路咖係具有如圖49所示 半導體晶請之厚金屬線謂金屬層1526=^時 寫之厚金屬線路咖之頂層金屬層3526刪均係為谭： 體晶片100、300之厚金屬線路⑽、35〇接合時，半導體晶片1 田⑽之 厚金屬線路150之頂層金屬層1526係利用浮接接合的方式=合|= b曰片300之厚金屬線路35〇之頂層金屬層3526。 三、晶片構裝之第三實施例 在上述的實施财，半龍晶片⑽之厚金屬線路⑽係直接接 觸地連接基板2GG之線路212，如第—實施例所述，或是直接接觸地 連接另-半導體晶片_之厚金屬線路，如第二實施例所述。然 而’本發明之應用並不限於此，半導體晶片1〇〇之厚金屬線路⑽亦 可以透過含有聚合物452及多數個金屬粒子454之導電層伽電性連 接一電路連接構件400之線路412，如圖50至圖54所示，其中半導 體晶片1GG之結構及材質在第—實施例巾均有詳盡的敘述，在此便不 再贅述，而電路連接構件400比如是任何形式之半導體晶片或是美 板。在本實施例中，電路連接構件4〇〇比如是玻璃基板，一般而言， 玻璃基板400之線路層410比如係由透明的銦錫氧化物所形成，在本 實施例中，線路層410比如包括線路412及接墊414。以下配合圖示 舉出數種實施可能情形： 1·半V體曰曰片之尽金屬線路與玻璃基板的線路係作為半導體晶片 50 200814211 内之訊號傳輸之用 清先參照® 50及® 51，其中圖5()纟會示依照本發明第三實施例之 晶片構裝在組裝前之半導體晶片與《基板的剖㈣意圖，其中切過 半導體晶片之厚金;|線_剖面部分係分別沿著厚金屬 線路的延伸路 徑作垂直切過半導體晶片的剖面而得；圖51繪示圖5()中半導體晶片 接與玻璃基板合後之晶片構裝的剖面示意圖。 請先參照圖50，在半導體晶片100與玻璃基板400接合之前，比 如疋異方性導電膠（anisotropic conductive paste，ACP)或是異方性 導電膜（anisotropic conductive film，ACF)之導電層 450 可以先形 成於玻璃基板400上，其中包括形成在玻璃基板4〇〇之線路412上與 玻璃基板400之接墊414上。導電層450之成分包括聚合物452及多 數個金屬粒子454，金屬粒子454係分佈在聚合物452中。 就線路的形式而言，玻璃基板4〇〇之線路412可以是沿著任何方 向在玻璃基板400之頂部延伸，比如是類似直線延伸的形式、曲線延 伸的形式或是具有不連續之凹折部分的延伸路徑。在較佳的情況下， 半導體晶片100之厚金屬線路15〇與玻璃基板400之線路412之間係 呈現鏡射的關係，使得半導體晶片1〇〇與玻璃基板400在接合時，半 導體晶片100之厚金屬線路150可以對準玻璃基板400之線路412。 在一實施例中，半導體晶片1〇〇之厚金屬線路150與玻璃基板4〇〇 之線路412比如是螺旋狀的電感元件，如圖50A及圖50B所示，其中 圖50A係為圖50中玻璃基板400之線路412投影至平面1〇5〇上的平 51 200814211 面示意圖；圖50B係為圖50中半導體晶片loo之厚金屬線路15〇投影 至平面1000上的平面示意圖。請參照圖50A及圖50B,半導體晶片1〇〇 之％感元件150的繞線路彳竖與玻璃基板400之線路412的繞線路徑之 間係呈現鏡射的關係，玻璃基板400之電感元件412係沿著路徑11〇〇 延伸，比如是從路徑1100之X點延伸至路徑11〇〇之γ點；半導體晶 片100之電感元件150係沿著路徑1200延伸，比如是從路徑12〇〇之 X點延伸至路徑1200之y點。 請參照圖51，在提供半導體晶片1〇〇與玻璃基板4〇〇之後，可以 進行接合的步驟’使得半導體晶片100之厚金屬線路15〇可以壓入位 於玻璃基板400上之導電層450中，使得半導體晶片100之厚金屬線 路150可以透過導電層450之金屬粒子454電性連接於玻璃基板400 之線路412，且半導體晶片1〇〇之凸塊160可以透過導電層450之金 屬粒子454電性連接於玻璃基板400之接墊414。此時，導電層450 之聚合物452可以包覆半導體晶片1〇〇之厚金屬線路15〇與凸塊16〇 的周圍。定義一平面1000，係大致上平行於半導體基底11〇之主動表 面114，其中半導體晶片1〇〇之厚金屬線路與玻璃基板4〇〇之線 路412投影至此平面1〇〇〇上之重疊區域的延伸距離L比如係大於5〇〇 微米，或者比如疋大於800微米，或者比如是大於12〇〇微米；半導體 晶片100之厚金屬線路150與玻璃基板4〇〇之線路412投影至此平面 1000上之重疊區域的面積比如係大於3〇, 〇〇〇平方微米，或者比如是 大於80, 000平方微米，或者比如是大於15〇, 〇〇〇平方微米。 52 200814211 在其中-實施例中，請參照圖50A及圖5〇B，當玻璃基板棚之 電感兀件412透過導電層450接合半導體晶片1〇〇之電感元件15〇時， 玻璃基板400之電感元件412的八、6、（：、〇、£小6區域係分別透 過導電層450接合半導體晶片⑽之電感元件15〇的a、b、c、d、e、 f、g區域。睛參照圖51A，其繪示圖5〇A及圖5〇β之二電感元件412、 150接合後之連接區域投影至平面麵上的平面示意圖，其中二電感 兀件150、412投影至此平面1〇〇〇上之重疊區域（圖5U中晝斜線的區 域）的延伸距離（路徑1200從X點延伸至y點的距離）比如係大於5〇〇 微米，或者比如是大於800微米，或者比如是大於12〇〇微米；二電感 元件150、412投影至此平面1〇〇〇上之重疊區域（圖51A中晝斜線的區 域）的面積比如係大於30, 000平方微米，或者比如是大於go, 〇〇〇平方 微米，或者比如是大於150, 〇〇〇平方微米。 請參照圖51，在電性傳輸上，半導體晶片1〇〇内之電子元件ι12 的其中一個（比如是電子元件112a)係適於輸出一電子訊號，此電子訊 號經由薄膜線路層132、134、136並穿過保護層140後，傳輸至厚金 屬線路150及玻璃基板400之線路412，接著再穿過保護層140，並經 由薄膜線路層136、134、132傳輸至半導體晶片100内之其他的電子 元件112之至少其中一個（比如是電子元件U2b);此時，半導體晶片 100之厚金屬線路150與玻璃基板400之線路412可以作為半導體晶 片100内之訊號傳輸之用。另外，此電子訊號在從電子元件112a傳輪 至厚金屬線路150及玻璃基板400之線路412後，還可以傳輸至玻墙 53 200814211 基板400内；此時，半導體晶片loo之厚金屬線路15〇與玻璃基板4〇〇 之線路412亦可以作為半導體晶片1〇〇與玻璃基板4〇〇間之訊號傳輸 之用。 在凸塊160的電性傳輸上’半導體晶片1〇〇可以透過凸塊1⑼傳 送電子訊號至玻璃基板400，或是可以透過凸塊160接收由玻璃基板 400所傳來的電子訊號。 如上所述，半導體晶片1〇〇之厚金屬線路150與玻璃基板4〇0之 線路412除了可以作為電子訊號的橫向傳輸之外，還可以作為半導體 曰曰片100與玻璃基板400間的縱向傳輸。由於半導體晶片之厚金 屬線路150係透過導電層450大面積地連接玻璃基板400之線路412, 因此可以大幅地增加半導體晶片1〇〇與玻璃基板4〇〇間電性連接的效 能，且可以減少雜訊的產生。 在上述電子訊號之電性傳輸上，半導體晶片1〇〇之厚金屬線路15〇 與玻璃基板400之線路412係作為半導體晶片1〇〇内之訊號傳輸之 用’亦同時作為半導體晶片1〇〇與玻璃基板4〇〇間之訊號傳輸之用。 然而，本發明的應用並不限於此，半導體晶片1⑽之厚金屬線路15〇 與玻璃基板400之線路412亦可以僅作為半導體晶片1〇〇内之訊號傳 輸之用，而不作為半導體晶片1〇〇與玻璃基板4〇〇間之訊號傳輸之用， 此時玻璃基板400之線路412係與玻璃基板4〇〇内之其它線路呈現電 性斷路的狀態。 在其他實施情形中，玻璃基板400亦可以適於輸出一電子訊號， 54 200814211 傳輸至玻璃基板400之線路412及厚金屬線路150，接著再穿過半導 體晶片100之保護層14〇，並經由薄膜線路層136、134、132傳輸至 半導體晶片1〇〇内之至少一電子元件112(比如是電子元件112a及 112b) 〇 在圖50及圖51中，厚金屬線路150係直接形成在保護層140上； 然而’厚金屬線路150亦可以是形成在位於保護層14〇上之聚合物層 180上’如圖52所示，其繪示依照本發明第三實施例之另一種晶片構 裝的剖面示意圖，其中聚合物層180之配置位置及材質在第一實施例 中均有詳盡的敘述，在此便不再贅述。 在圖50至圖52中，厚金屬線路150係透過保護層140之小開口 142小面積地連接頂層的薄膜線路層136;然而，厚金屬線路15()亦可 以是透過保護層14〇之大開口 142大面積地連接頂層的薄膜線路層 136，如圖53及圖54所示，其繪示依照本發明第三實施例之其他形式 曰曰片構裝的剖面示意圖。在本實施例中，圖53及圖54所示之半導體 曰曰片100之厚金屬線路15〇與薄膜線路137間的連接關係係雷同於第 實施例中圖4至圖5所示之半導體晶片1〇〇之厚金屬線路15〇與薄 膜線路137間的連接關係’相關更詳盡的說明，可以參考在第一實施 例中所舉出的半導體晶片⑽之厚金屬線路15()與賴線路137係為 電感元件的實關’若是參考此部份的說明，將會對本實施例中半導 體曰曰片100之厚金屬、線路15〇舆薄膜線路137間的連接關係有更清楚 的瞭解。 55 200814211 明參照圖53及圖54，在電性傳輸上，半導體晶片loo内之電子 元件112的其中一個（比如是電子元件112a)係適於輸出一電子訊號， 此電子訊號經由薄膜線路層132、134後，可以傳輸至薄膜線路137、 厚金屬線路150及玻璃基板400之線路412 ,接著再經由薄膜線路層 134、132可以傳輸至半導體晶片1〇〇内之其他的電子元件Μ?之至少 其中一個（比如是電子元件H2b);此時，薄膜線路137、厚金屬線路 150與玻璃基板4〇〇之線路412可以作為半導體晶片1〇〇内之訊號傳 輸之用。另外，此電子訊號在傳輸至薄膜線路137、厚金屬線路15〇 及玻璃基板400之線路412後，還可以傳輸至玻璃基板内；此時， 薄膜線路137、厚金屬線路150與玻璃基板400之線路412亦可以作 為半導體晶片100與玻璃基板400間之訊號傳輸之用。另外，玻璃基 板400亦適於輸出一電子訊號，傳輸至玻璃基板4〇〇之線路412及半 導體晶片100之厚金屬線路15〇及薄膜線路137，接著再經由薄膜線 路層134、132傳輸至半導體晶片1〇〇内之至少一電子元件112(比如 是電子元件112a及112b)。 另外，就凸塊160的電性傳輸而言，半導體晶片1〇〇可以透過凸 塊160傳送電子訊號至玻璃基板4〇〇，或是可以透過凸塊16〇接收由 玻璃基板400所傳來的電子訊號。 如上所述，半導體晶片1〇〇之薄膜線路137、厚金屬線路150與 玻璃基板400之線路412除了可以作為電子訊號的橫向傳輸之外，還 可以作為半導體晶片1〇〇與基板200間的縱向傳輸。由於厚金屬線路 56 200814211 150係大面積地連接薄膜線路137及玻璃基板棚之線路似，故至少 可以增加電子訊號之—部份傳輸雜喊面積，因此可以改善電子訊 號之傳輸品質。 2·半導體晶片之厚金屬線路與玻璃基板的線路係作為半導體晶片 與玻璃基板間之訊號傳輪之用。 4參照圖55至圖58，其繪示依照本發明第三實施例之另一類型 晶片構裳的剖面示意圖，其中圖55至圖58之半導體晶片刚係分別 雷同於第-實施例中圖2至圖5之半導體晶片剛，且圖55至圖⑽ 之玻璃基板棚係雷同於圖5Q至圖54之玻璃基板侧，在此便不再 贅述；惟不同點係在於半導體晶片1〇〇之厚金屬線路15〇與玻璃基板 400的線路412僅作為半導體晶片1〇〇與玻璃基板侧間之訊號傳輸 之用，而不作為半導體晶片議内之訊號傳輸之用，如下所述。 請參照圖55及Η 56，在電性傳輸上，半導體晶片1〇〇内之電子 元件112的其中-個（比如是電子元件112a)係適於輸出—電子訊號， 此電子訊號經由薄膜線路層132、134、136並穿過保護層14〇後，傳 輸至半導體晶片1〇〇之厚金屬線路150及玻璃基板4〇〇之線路4丨2， 接著再傳輸至玻璃基板400内；此時，半導體晶片1〇〇之厚金屬線路 150與玻璃基板400之線路412係可以作為半導體晶片1〇〇與玻璃基 板400間之訊號傳輸之用。 在其他實施情形中，玻璃基板400亦適於輸出一電子訊號，200814211 IX. Description of the invention: [Technical field of the invention] The present invention is a touch-type seed crystal; a structure and a wafer structure, and the system is related to a wafer structure having a germanium electrical property and corresponding thereto Wafer assembly process. [Prior Art] With the rapid advancement of information product technology, human beings want to quickly obtain information thousands of miles away, and it’s not awkward - the business of arbitrarily competing for the advantages of the company, through the construction of high-efficiency information products. . With the information products, Chen Xinxin and the latest serial single-chip design of various circuit designs generally provide more functions than ever before. Thanks to the success of the semiconductor technology's new monthly 'Bronze' (fourth) mass production, coupled with the integration of the _ circuit, the large recording Wei number transmission can be in the same-single chip, so that the transmission path of the signal can be shortened and the performance of the chip can be improved. After the wafer_ is completed, the wire or the bump is used to electrically connect the wafer to the substrate. No, it is said that the cross-sectional area of the feeding line or the bump in the vertical _ lining direction is very small. Therefore, when weaving the scales, excessive noise will be generated, and in serious cases, the operation error will be caused. SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a wafer fabrication and wafer fabrication process, σ, connecting a line of a half-body wafer and a circuit connecting member, thereby improving electrical performance. To achieve the object of the present invention, the present invention provides a wafer package comprising a semiconductor wafer splicing member. The semiconductor wafer has a first line, and the circuit connecting member has a sixth line 200814211, wherein the second line of the circuit connecting member is in direct contact with the first line of the semiconductor wafer. In addition, the present invention also provides a wafer package comprising: a replacement wafer, a conductive layer and a circuit connecting member, wherein the semiconductor wafer has a first line, the circuit connecting member has a second line, and the conductive layer is a connection - a line and a second line, and the composition of the conductive layer comprises a polymer and a plurality of metal particles, the metal particles are clothed on the polymer towel, and the metal particles of the first line through the conductive layer are electrically connected to the second line. In addition, the present invention also proposes a wafer fabrication process including the following steps: First, a half V body positive film is provided, wherein the semiconductor wafer has a -th line, and a circuit connection member is also provided in the eight-way connection. The member has a second line. Next, the circuit I is connected in direct contact with the semiconductor crystal first line. In addition, the present invention provides a wafer fabrication process including the following steps: First, a semiconductor wafer is provided, wherein the semiconductor wafer has a 'th line' and a circuit connection member is further provided, wherein the circuit connection member has a second line . Next, the second line of the circuit connecting member and the first line of the semiconductor wafer are directly contacted. In addition, the present invention also proposes a wafer structure process, including the following steps: Firstly, providing: a semiconductor wafer 'injecting crystals (4), and providing a circuit-connecting piece's shirt (1): _,, county-wei Layered on the 4-, _ of the circuit member, the towel guides the filament (10) polymer, and the metal particles are distributed in the polymer. Next, the first wheel is guided, so that the metal line passing through the conductive layer is electrically connected to the second line. The above and other objects, features, and advantages of the present invention will become more apparent and understood. [Embodiment] The structure is based on the circuit of the contact __Electronic_Connected_Sui Wei, which makes the material of the material large-area electrically connected to the circuit connecting member, so that it can be greatly improved An electrical relationship between the semiconductor wafer and the road connecting member. Alternatively, the wiring of the semiconductor wafer can be connected to the conductive layer containing the polymer and the metal particles in a large area, so that the electrical relationship between the semiconductor wafer and the circuit connecting member is oscillated. In the following embodiments, the same reference numerals are used to refer to the same components. I. First Embodiment of Wafer Fabrication In the first embodiment of the wafer assembly, the semiconductor wafer has a thick metal line, and the semiconductor wafer filament layer is rotated by a thick Jinlin road to directly connect with the ground. The wiring of the substrate. In the following, there are several possible implementation scenarios: 1) The thick metal line of the semiconductor wafer and the circuit of the substrate are used as the semiconductor chip internal signal. The signal for transmission 9 is shown in FIG. 1 according to the first embodiment of the present invention. The wafer structure* is a schematic cross-sectional view of the semiconductor wafer and the substrate before assembly, wherein the thick metal line of the semiconductor wafer is cut through the extension path of the semiconductor wafer, and is cut through the cross section of the semiconductor wafer. The σ 面 卩 卩 系 系 沿着 沿着 沿着 沿着 沿着 沿着 沿着 沿着 沿着 沿着 沿着 沿着 半 半 半 半 半 半 半 半 半 半 半 半 半 半 半 半 半 半 半 半 半 半 半 半 半 半 半 半 半Ϊ́24, ΐ26, a plurality of thin film circuit layers 132, 134, 136 and a protective layer 14A. The semi-body substrate 110 has a plurality of electronic components 112, and the electronic components η? are disposed on the semiconductor substrate no-active surface 114 a wire layer, wherein the semiconductor substrate ιι is, for example, a stone substrate, is doped with a pentavalent or trivalent ion, such as a contact ion or a bowl ion, thereby forming a plurality of electronic components 112 on the semiconductor substrate 11 The layer, the electronic component 112 is, for example, a metal oxide semiconductor, a body or a transistor, etc. A plurality of thin film dielectric layers 122, 124 can be formed by chemical gas deposition, both on the active surface 114 of the semiconductor substrate 110. The thin film dielectric layer 122, (2), such as an oxygen compound, a compound Wei oxygen derivative, and the like, each of the circuit layers, 134, and 136 are disposed on one of the thin film dielectric layers 122, 124, and 126, respectively. The material of the film circuit layer 132, 134, 136 includes, for example, aluminum, copper or tantalum, etc. The thin film dielectric layers ι 22, 126 have a plurality of via holes 12, 123, 125, and the film circuit layers 132, 134, 136 can be The vias 12 and 123 of the thin film dielectric layers 122, 124, and 126 are electrically connected to each other and electrically connected to the electronic component 112. The protective layer 140 is disposed on the thin film dielectric layers 122, 124, and 126. The thickness of the protective layer 140 is, for example, greater than 〇·35 μm, and the structure of the protective layer 14〇 is, for example, a nitrogen compound layer, an oxygen hard compound layer, and a layer. Scaly-second glass 蹲 蹲 丨 丨 丨 丨 丨The composite layer 140 has a plurality of openings 142 exposing the thin film wiring layer 136 located on the top layer. 9 200814211 The thick metal wiring 150 is located on the protective layer 140, and is electrically connected to the thin through the opening 142 of the protection. _ 136, the thickness of the film layer 132, 134, 136. The bump 160 is substantially aligned with the opening 142 of the protective layer 14〇, and is electrically connected to __ 136. _, _ Line _ and convex _ can be completed using the same system, @this thick gold riding (10) and the bump (10) can have the same metal layer structure line _ _ (10) _ structure will be explained in detail later in the silk jump Over. It is worth noting that the thickness of the thick-faced line (10) is substantially the same as the thickness h of the convex, wherein the thick metal line 15_degree and the thickness (h) of the bump (10) are, for example, greater than 1 micron, in the preferred case. For example, the system is larger than 5 microns. The form of the substrate may include a hard board or a soft board, wherein the hard board is generally overlapped by a plurality of circuit layers and insulating layers, such as a common four-layer board, a six-layer board or an eight-layer board, etc. The material of the insulating layer is, for example, a polymer or a shout. The soft board is composed of, for example, a layer of a circuit layer and a layer of a layer of a barrier layer, and the layer of the circuit layer is located on the extreme riding. The material of the insulating layer of the towel is, for example, a polymer, and 0, because the soft board has a thin thickness. Thickness and therefore greater flexibility. As described above, the substrate 200 may be in the form of a hard or soft board. The substrate 200 has, for example, a circuit layer 210 and a solder mask layer 220 on the top of the substrate 2, and the solder mask layer 220 is on the circuit layer 21 of the substrate 200 for protecting the circuit layer 21, wherein the circuit The layer 21 has a line 212 and a pad 214'. The opening 222 of the solder mask layer 220 exposes the line 212 of the circuit layer 210 and the pads 214. In addition, in terms of the form of the line, the thick metal line 15 of the semiconductor wafer may be & extend in the direction of the top of the semiconductor wafer 1 in any direction, such as a form similar to a straight line extension, 200814211 curve extension (four) butterfly The object is deleted __Qing path, and the line 212 of the base is also the denomination of her stomach extension, such as the form of a straight line extension, the metaphysical tree ran away (10) material path. In the preferred case, the thick metal line (10) of the semiconductor wafer 100 and the circuit 212 of the substrate are presented as a 嶋 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖Line 212 of 200. In Beiguan, the thick metal line (10) of the semiconductor wafer (10) and the circuit line 212 of the substrate are, for example, spiral inductor elements, as shown in FIG. 9 and FIG. ,, wherein (4) is the line 212 of the substrate 200 projected onto the plane. The schematic diagram on the top; Figure ΐ is the diagram! A plan view of a thick metal line 15 of the middle half of the body piece 100 projected onto a plane. Please refer to Figure 1B for the relationship between the winding path of the inductive component (10) of the semiconductor wafer (10) and the winding path of the substrate «the component 212. The inductive component of the substrate is measured. The extension, for example, extends from the X point of the path u(8) to the γ point of the path H〇〇; the inductive component (10) of the body wafer (10) extends along the path, for example, from the X point of the path 1200 to the point y of the path 12 (8). . Referring to FIG. 2, a cross-sectional view of the wafer structure after bonding the semiconductor wafer and the substrate in FIG. i is performed, and after the semiconductor crystal 1 〇〇 and the substrate 2 are provided, the step of bonding can be performed. The thick metal line 15 () of the half-body wafer 100 can be directly connected to the substrate contact line 212' and the bumps 160 of the semiconductor wafer 100 can be directly contacted to the pads 214 of the substrate 200. Then, a polymer can be filled. The layer 17 is sandwiched between the semiconductor wafer 1 and the substrate, and the conformal layer 170 covers the periphery of the thick metal line 15〇 and the periphery of the bump 16〇. Defining a flat 200814211 face 1000, substantially parallel to the active surface 114 of the semiconductor substrate 110, wherein the region of the thick metal line 150 connected to the substrate line 212 is projected onto the plane 1 延伸, for example, greater than 500 microns, or For example, it is greater than 8 〇〇 micrometers, or, for example, greater than 12 〇〇 micrometers; the area of the thick metal line 150 connected to the substrate line 212 projected onto the plane 1 比如 is, for example, greater than 30,000 square micrometers, or for example Greater than go, 〇〇〇 square micron, or, for example, greater than 150,000 square microns. In one embodiment, referring to FIG. 1A and FIG. 1B, when the inductive component 212 of the substrate 2 is directly in contact with the inductive component 15 of the semiconductor wafer 100, the A, B, and C of the inductive component 212 of the substrate 200. The D, E, F, and G regions are in direct contact with the a, b, c, d, e, f, and g regions of the inductive component 150 of the semiconductor wafer. Please refer to FIG. 2A , which is a schematic plan view showing the connection area of the two inductive elements 212 , 150 of FIG. 1A and FIG. 1B joined to the plane 1 ,, where the two inductive elements 150 , 212 are connected ( FIG. 2A The area of the midline slash) projected onto the plane 1000 (the distance of the path 12〇〇 extending from the defect to the y point) is, for example, greater than 500 microns, or such as greater than 8 microns, or greater than 12 inches, for example. 〇 microns; the area where the two inductive elements 150, 212 are connected (the area marked with a diagonal line in FIG. 2A) is projected onto the plane 丨〇 (9), for example, more than 30,000 square microns, or, for example, greater than 8 〇, 〇〇〇 square Micron, or for example greater than 150, 〇〇〇 square micron. Referring to FIG. 2, in the electrical transmission, one of the electronic components 112 in the semiconductor chip 1 (such as the electronic component 112a) is adapted to output an electronic signal via the thin film circuit layers 132, 134. After passing through the protective layer 14 , the film is transferred to the thick metal line 15 〇 and the line 212 of the substrate 200 , and then through the protective layer 14 〇 and transferred to the semiconductor wafer via the thin film wiring layer 136 , ι 34 , 12 200814211 7 . At least one of the other electronic components 112 (such as the private component 112b), the semiconductor wafer followed by the thick metal wiring and the thin substrate 212 can be used for signal transmission in the semiconductor wafer. In addition, the electronic signal can be transmitted to the substrate 200 after being transferred to the thick metal line 15 () and the substrate measurement line 212. At this time, the thick metal line (10) and the substrate 2 of the semiconductor wafer (10) The circuit 212 can also be used for signal transmission between the semiconductor wafer 1 and the substrate 2. On the electrical transmission of the bumps 160, the semiconductor wafers 1 can transmit electrons to the substrate 200 through the bumps 16 or can receive the electronic signals transmitted from the substrate 2 through the bumps. As described above, the thick metal line of the semiconductor wafer and the line 212 of the substrate 2 can be used as a lateral transmission between the semiconductor wafer 1 and the substrate 200 in addition to the lateral transmission of the electronic signal. Since the thick metal line 15 of the semiconductor wafer is directly connected to the line 212 of the substrate 200, the thick metal line 15 of the semiconductor wafer can be electrically connected to the line 212 of the substrate 200 over a large area. The efficiency of electrically connecting the semiconductor wafer to the substrate 200 is greatly increased, and the generation of noise can be reduced. In the electrical transmission of the electronic signal, the thick metal line 15 of the semiconductor wafer and the line 212 of the substrate 200 are used for signal transmission in the semiconductor wafer 1 and also serve as the semiconductor wafer 100 and the substrate 200. The signal transmission between the two. However, the application of the present invention is not limited thereto, and the thick metal line 150 of the semiconductor wafer 100 and the line 212 of the substrate 200 may also be used only for signal transmission in the semiconductor wafer 100, and not between the semiconductor wafer 1 and the substrate 200. For the signal transmission, the line 212 of the substrate 200 and the other lines in the substrate 200 are electrically disconnected. In other applications, the substrate 2 can also be adapted to output an electronic signal, which is transmitted to the line 212 of the substrate 200 and the thick metal line 15 , and then passes through the semiconductor wafer as the protective layer 140 and through the thin film line. Layers 136, 134, 132 are transferred to at least one electronic component 112 (such as electronic components 112 & and 112b) within semiconductor wafer 1 . In FIGS. 1 and 2, the thick metal line 150 is formed directly on the protective layer 14A; however, the thick metal line 150 may also be formed on the polymer layer 18〇 on the protective layer 14〇, such as ® 3 Tf is a schematic cross-sectional view of another wafer assembly according to the first embodiment of the present invention. Referring to FIG. 3, a polymer layer 180 is formed on the protective layer 14A. The polymer layer 18 has a plurality of openings 182, substantially aligned with the opening 142 of the protective layer 14〇, and the thick metal line 15 is formed. The polymer layer 18G is connected to the thin film wiring layer 136 via the opening 182 of the polymer layer and the opening 142 of the protective layer 14''. It is noted that the thickness h of the bump 160 protruding beyond the opening 182 of the polymer layer (10) is, for example, substantially the same as the thickness j of the thick metal line 150 on the polymer layer 18, and the thick metal line 15 The crucible and the bump 16 have the same metal layer structure, wherein the thickness h of the bump 160 protruding beyond the opening 182 of the polymer layer 180 and the thickness of the thick metal line 15〇 on the polymer layer 180 For example, it is greater than j microns, and in preferred cases, such as greater than 5 microns. The thickness k of the polymer layer 18〇 is, for example, greater than 丨μm, and the material of the conformal layer 180 is, for example, polypyramine (pi), benzocyclobutene 'BCB, polyarylene. Ether (paryiene), porous dielectric material or elastomer. In FIG. 1 to FIG. 3, the thick metal line 150 is connected to the top film layer 136 through the small opening 142 of the protective layer 14 2008. The thick metal line (10) may also be a large opening through the protective layer 140. 142 is connected to the thin film circuit layer 136 over a large area, as shown in FIG. 4 and FIG. 5, which is a cross-sectional view showing the wafer structure of other forms according to the first embodiment of the present invention, wherein the top layer is 136 The opening (4) of the lining m, the lamella layer (10) exposes the thin film line 137 over a large area, so that the thick metal line 15 〇 can connect the thin lining 137 exposed by the opening 142 of the sump layer 14 大 in a large area, the above A large area connection is as follows. Referring to FIG. 4 and FIG. 5, the first case of large-area connection: defining a plane, which is substantially parallel to the active surface 114 of the semiconductor substrate 110, and the thick metal line (10) is connected to the thin film line 137. The area projected onto this plane is divided by (4) Lin Road (3). The ratio of the area projected onto this plane 1_ is greater than Q. 5, or for example, is greater than 8, or such as being substantially equal to 1. The second case of large area connection: the opening 142 of the protective layer 14 turns out that the area of the thin film line 137 is, for example, greater than 3 square microns, or, for example, greater than 80,000 square microns, or such as greater than 15 inches. , 〇〇〇 square micron. The second case of large area connection. The extent to which the thick metal line 150 is connected to the thin film wiring layer (10) is projected onto the plane 1000 such that it is greater than 500 microns, or such as greater than 8 microns, or such as greater than 1200 microns. As long as it satisfies any of the above, it can be said that the thick metal line 150 is connected to the top film layer 136 over a large area. In an embodiment, when the thick metal line 15 of the semiconductor wafer 100 is, for example, a spiral inductor element, the thin film line connected to the thick metal line 150 is also a spiral inductor element. As shown in FIG. 5A, a cross-sectional view of the thick metal line and the thin film of the 200814211 film line connecting the Xie to the plane 1000 is shown in FIG. 4 and FIG. 5, wherein the thick metal line and the film line are both in the position. The style of the inductive component. The thin film line 137 as an inductive element extends along the path 1200, for example, from point p of the path 12〇〇 to the q point of the path 12〇〇. Clear reference ® 5A, the area where the two inductive elements 150, 137 are connected is projected onto the plane 1〇〇〇 (the area marked with a diagonal line in FIG. 5A) divided by the area projected by the film line 137 onto the plane (10) surrounded by the dotted line in 5A The ratio of the area is, for example, greater than 〇·5, or if the system is greater than u, or is, for example, substantially equal to 卜, the opening 142 of the protective layer 14() exposes the area of the film line (3); The region) is, for example, greater than 3 〇, _ square micron, or such as greater than 8 〇, 〇〇〇 square micron, or such as greater than 15 〇, _ square micron. In addition, the region where the two inductors π-members 150 and 137 are connected (the region of the oblique line in FIG. 5A) is projected onto the plane 1〇〇〇 (the distance from the ν point to the point w in FIG. 5). Greater than 5 microns, or such as greater than 8 microns, or such as greater than i2Q. Referring to FIG. 4 and FIG. 5, in the electrical transmission, one of the electronic components 112 in the semiconductor chip 1 (for example, the electronic component 112a) is adapted to rotate an electronic signal, and the electronic signal passes through the film. After the circuit layers 132, 134, they can be transferred to the thin film line 137, the thick metal line 15 and the line 212 of the substrate 200, and then can be transferred to at least the other electronic components 112 in the semiconductor wafer 100 via the thin film wiring layers 134, 132. One of them (for example, the electronic component 112b); at this time, the thin film line 37, the thick metal line 15A, and the substrate 212 of the substrate 2 can be used for signal transmission in the semiconductor wafer 100. In addition, after transmitting the electronic signal to the line 212 of the thin film line 137, the thick metal line 150 and the substrate 200, the electronic signal can also be transmitted to the substrate 200; at this time, the thin film line 137, the thick metal line 15 and the substrate 2 are The line 212 can also be used as a signal transmission wheel for the semiconductor crystal and the substrate_200814211. In addition, the substrate is also suitable for outputting an electronic signal 'passing to the substrate measuring line 212 and the thick metal line (10) and the thin film line 137 of the rotating wafer, and then transferring to the semiconductor wafer 1 via the thin film wiring layer 134. At least the electronic component 112 (such as an electronic component and a singularity. In addition, in terms of electrical transmission of the bump 160, the semiconductor wafer 100 can transmit an electronic signal to the substrate 200 through the bump (10), or can pass through the convex The block (10) receives the electronic signal transmitted from the substrate. As described above, the thin film line 137 of the semiconductor wafer, the thick metal line (10) and the line 212 of the substrate 200 can be used as a lateral transmission of the electronic signal. As a longitudinal transmission between the semiconductor wafer 100 and the substrate 200. Since the thick metal line 15 is connected to the thin film line 137 and the line 212 of the substrate 2 in a large area, at least one part of the transmission path of the electronic signal can be increased. The area, therefore, can improve the transmission quality of the electronic signal. The difference between FIG. 4 and FIG. 5 is whether the semiconductor wafer 1 is provided with a polymer layer 18 On the layer 140. Referring to FIG. 4, after the protective layer 14 is formed, the semiconductor wafer 1 is simultaneously formed to form a thick metal line 150 and a bump 160 on the thin film wiring layer 136, wherein the thickness of the bump 160 is h. For example, it is substantially the same as the thickness of the thick metal line 15〇, and the metal layer structure of the bump 16〇 is substantially the same as the metal layer structure of the thick metal line 15〇, wherein the thickness of the bump 16〇 and the thick metal The thickness j of the line 15 is, for example, greater than 1 micrometer, and preferably, for example, greater than 5 micrometers. However, referring to FIG. 5, after the protective layer 14 is formed, a patterned polymer layer 180 is also formed. On the protective layer 14〇, the thickness k of the polymer layer ι8〇 is, for example, greater than 1 μm, and the material of the poly layer 17 200814211 layer 180 is, for example, poiyimide (PI), benzocyclobutene (benzocyclobutene). , BCB), polyarylene ether (parylen phantom, porous dielectric material or elastomer, etc. The polymer layer 180 has an opening 182 exposing the top film layer 136 of the top layer, including exposing the film line 137. Can be simultaneously shaped The thick metal line 15 turns and the bumps 160 are on the thin film circuit layer 136, wherein the thickness h of the bumps 160 protruding beyond the opening 182 of the polymer layer 18 is, for example, substantially the same as the opening protruding from the polymer layer 18? The thickness j of the thick metal line 150 outside the 182, and the metal layer structure of the bump 16〇 is substantially the same as the metal layer structure of the thick metal line 150, and the bump protruding beyond the opening 182 of the polymer layer 18〇 The thickness h of the brush is, for example, greater than 1 micrometer, and in the preferred case, such as greater than 5 micrometers, the thickness of the thick metal wiring 15 突出 protruding from the opening 182 of the polymer layer 180 is, for example, greater than (micrometers, In preferred cases, such as greater than 5 microns. Referring to FIG. 4 and FIG. 5, after the fabrication of the thick metal lines 15 and bumps 160 of the semiconductor wafer (10), the steps of bonding can be performed, so that the thick metal lines (10) of the semiconductor wafer can be directly connected to the circuit of the substrate 2GG. 212, and the bumps (10) of the semiconductor wafer (10) can be directly connected to the pads 214 of the substrate. Next, a polymer layer may be filled between the semiconductor crystal and the substrate, and the polymer layer m is wrapped around the thick metal wiring (10) and around the bump 160. Please refer to FIG. 6 to FIG. 9 for the transmission of thick metal, line and substrate between the chip and the substrate. The reason for the transmission of the thick metal, the line and the substrate is as described in the first embodiment of the present invention. A cross-sectional view of another type of cymbal sheet, wherein the semiconductor crystal (four) of the ring of FIG. 6 is identical to the semiconductor wafer 1G0 of 18 200814211, and the substrate of the substrate of FIG. 6 to FIG. 9 is identical to the substrate 200 of FIG. 2 to FIG. Therefore, the difference is that the thick metal line 15 of the semiconductor wafer and the line 212 of the substrate 200 are only used for signal transmission between the semiconductor wafer iq and the substrate 2QQ, and not as a material. The signal transmission in the wafer class is as follows. «May 6 and FIG. 7' In electrical transmission, one of the electronic components 112 (such as the electronic component 112a) in the semiconductor wafer 1 (9) is adapted to rotate an electronic signal via the thin film wiring layer 132. After passing through the protective layer 14 , 134 and 136 are transferred to the thick metal line 150 of the semiconductor wafer 1 and the line 212 of the substrate 200, and then transferred to the substrate 2 ;; at this time, the thickness of the semiconductor wafer 1GG The metal line 150 and the line 212 of the substrate 200 can be used for signal transmission between the semiconductor wafer 100 and the substrate 200. In other implementations, the substrate 200 is also adapted to rotate an electronic signal, to the substrate 212 and to the thick metal line 15 of the semiconductor wafer 100, and then to the protective layer 14 of the semiconductor wafer 1 And transmitted to the at least one electronic component 112 (such as electronic component U2a) in the semiconductor wafer (10) via the thin film wiring layers 136, 134, 132. Referring to FIG. 8 and FIG. 9, in the electrical transmission, the electronic component ιΐ2 in the semiconductor wafer (10) is driven by the electronic ship, and the component signal is transmitted to the thin film line 137 and the thick metal line 15 through the thin film circuit layers 132 and 134. The circuit 212 of the substrate and the substrate 2 is then transferred to the substrate 200. At this time, the thick metal line 15 of the semiconductor wafer (10) and the substrate 200 of the substrate 200 can be used as the signal transmission between the semiconductor wafer (10) and the board. use. In other implementations, the 'substrate 200 is also suitable for the wheel-out electronic signal, the line 212 of the substrate to the substrate · 200814211 and the thick metal line 15〇 and the thin film line (3) of the semiconductor wafer (10), and then through the enamel circuit layer 134, 132 is transmitted to at least an electronic component (10) (such as electronic component 112a) within the semiconductor wafer (10). Referring to FIG. 6 to FIG. 9, in terms of electrical transmission of the bump 16〇, the rotating wafer can be transported through the bump 160, or can be received by the substrate through the bump (10). The electronic signal from the 。. As described above, the thick metal lines 15 〇 and the substrate of the transfer wafer 100 can be used as a semiconductor, and can be used as a semiconductor for longitudinal transmission between the substrate and the substrate. Since the thick metal line (10) of the semiconductor wafer (10) is directly in contact with the thin circuit line 212 of the substrate, the thick metal line (10) of the semiconductor crystal can be a large area of the line 212 of the new wire board 200, so that the semiconductor wafer 1 can be greatly increased. The electrical connection between the crucible and the substrate 200 is effective, and the generation of noise can be reduced. 3. Referring to FIG. 10 to FIG. 13 , a thick metal line and a substrate private line of a semiconductor chip are used as a power bus or a ground bus. FIG. 13 is a cross-sectional view showing another type of wafer structure according to the first embodiment of the present invention. The semiconductor wafer (10) of FIG. 1G to FIG. 13 is similar to the semiconductor wafer (10) of FIGS. 2 to 5, and the substrate of FIG. 1() to FIG. 13 is identical to the substrate 200 of FIG. 2 to FIG. Therefore, the same point is that the thick metal line 150 of the semiconductor wafer (10) and the line 212 of the substrate 200 are used as a power bus or a ground bus, as described below. Referring to FIG. 10 to FIG. 13, when the thick metal line 150 of the semiconductor wafer 100 and the line 212 of the substrate 200 20 200814211 are used as power supply busbars, the thick metal line of the semiconductor wafer (10) is disconnected from the line 212 of the substrate 200, such as a miscellaneous connection. The power bus to the semiconductor wafer (4), for example, is provided by the fine layer 134, and the field is connected to the substrate n. The thick metal line (10) of the semiconductor wafer is directly large. Contacting the grounding line 212 of the substrate 200 and electrically connecting to the power busbar of the semiconductor wafer 1 to reduce the degree of electric dust and under-conduction of the power busbar 135 of the semiconductor wafer due to signal interference. 'And the semiconductor wafer (10) can provide a relatively stable supply voltage. Or in other cases, the thick metal line 15 of the semiconductor wafer (10) and the line 212 of the substrate 2〇 are electrically connected to the power bus 135 of the half-day chip (10), but the line in the substrate 200 There is an electrical disconnection between them. In the case of the thick metal line 15〇 of the semiconductor wafer of FIG. 10 to FIG. 13 and the line 212 of the substrate, the thick metal line (10) of the semiconductor wafer (10) and the line 212 of the substrate 2 _ , New Zealand connected to the semi-conducting _ (10) European pick-up row tearing, such as provided by 134, the new _ to the substrate · _ ground sink; half 'body 00 piece 100 thick metal line (10) is a large area direct contact ground connection The base, the circuit 212 and the electrical connection to the ground bus (3) in the half-wafer just reduce the ground bus 135 of the semiconductor wafer (10) due to signal interference and generate electrical interest and the material_(10) can be sprayed _ teach _ pressure. Alternatively, the thick metal line (10) of the +-conductor crystal is electrically connected to the circuit of the substrate, and is electrically connected to the ground of the semiconductor crystal, but is electrically disconnected from the line in the substrate 2 (9). 21 200814211 4. Referring to FIG. 14 and FIG. 15 , a semiconductor crystal is used as a base (four) for transmission, or as a substrate power bus or ground bus, and is illustrated in accordance with the first embodiment of the present invention. A cross-sectional view of another type of wafer structure, wherein the semiconductor wafers (10) of FIGS. 14 and 15 are identical to the semiconductor wafers 100 of FIGS. 2 and 3, respectively, and the substrate 2 of FIGS. 14 and 15 is identical to The substrate 200' of FIGS. 2 and 3 will not be described herein; the only difference is that the thick metal lines 150 of the semiconductor wafer are electrically connected to the thin film wiring layers 132, 134, and 136 in the semiconductor wafer 100. The state of the open circuit, and the thick metal line 15 of the semiconductor wafer 100 and the line 212 of the substrate are used for signal transmission in the substrate 200 or as a power bus or ground bus of the substrate 2, as follows Said. Referring to FIG. 14 and FIG. 15, when the thick metal line 15 of the semiconductor wafer 100 and the line 212 of the substrate 2 are used for signal transmission in the substrate 200, an electronic signal is suitable for transmission to the substrate 2 via the substrate 200. The thick metal line go of the circuit 212 and the semiconductor wafer 1 is transmitted through the line 212 of the substrate 200 and the thick metal line 15 of the semiconductor wafer 100, and then transferred to other lines of the substrate 200, wherein the electronic signal is The thick metal lines 150 of the semiconductor wafer 100 are not directly transferred into the semiconductor wafer 1 without the wiring 212 from the substrate 2. As described above, the thick metal line 150 of the semiconductor wafer 100 and the line 212 of the substrate 200 can be used only for electronic signal transmission in the substrate 200, not as a signal transmission wheel in the semiconductor wafer 1 or as a semiconductor wafer. The signal transmission between the 100 and the substrate 200 is used. Since the thick metal line 150 of the semiconductor wafer 100 is directly in contact with the line 212 of the substrate 200, the thick metal line 150 of the semiconductor wafer 100 can electrically connect the substrate 22 to the line 22 200814211 212 over a large area, which can increase this. The electrical transmission quality of electronic signals. Referring to FIG. 14 and FIG. 15 'When the thick metal line 1 of the semiconductor wafer 1 and the line 212 of the substrate are used as the power bus of the substrate 200, the thick metal line 150 of the semiconductor wafer and the line 212 of the substrate 200 The utility model is suitable for electrically connecting the power busbars in the substrate 2, wherein the thick metal wires 150 of the semiconductor wafer 100 and the power busbars in the semiconductor wafer 1 are electrically disconnected. Since the thick metal line 15 of the semiconductor wafer 100 is directly connected to the line 212 of the substrate 200 and electrically connected to the power bus bar in the substrate 200, the power supply bus of the substrate 200 can be reduced to generate voltage due to signal interference. The extent of the change, and the substrate 200 can provide a relatively stable supply voltage. Referring to FIG. 14 and FIG. 15, when the thick metal line 15 of the semiconductor wafer 100 and the line 212 of the substrate 2 are used as the ground bus of the substrate 200, the thick metal line 150 and the substrate 200 of the semiconductor wafer 1 are connected. The 212 series is adapted to electrically connect the ground busbars in the substrate 2, wherein the thick metal lines 15 of the semiconductor wafer 100 and the ground busbars in the semiconductor wafers are electrically disconnected. Since the thick metal line 15 of the semiconductor wafer 100 is directly connected to the line 212 of the substrate 200 and electrically connected to the ground bus bar in the substrate 2, the ground bus bar of the substrate 200 can be reduced because of signal interference. The degree of voltage change is generated, and the substrate 200 can provide a relatively stable ground voltage. 5. Metal layer structure of a thick metal line of a semiconductor wafer and a line of a substrate. Fig. 16 is a cross-sectional view showing a metal layer stacking structure of a thick metal line of a semiconductor wafer in the first embodiment of the present invention. The thick metal line 150 of the semiconductor wafer 1 includes an underlying metal layer 1511 and a top metal layer 1516, and the underlying metal layer 23 200814211 1511 is directly formed on the protective layer 140, for example (FIG. 1, FIG. 2, FIG. 6. Figure ι〇 and Figure μ), on the polymer layer 180 (as shown in Figures 3, 7, U and Figure 15) or on the top film line 137 (Figure 4, Figure 5, Figure 8) 9, FIG. 12 and FIG. 13), the top metal layer 1516 is located on the underlying metal layer 1511. The material of the underlying metal layer 1511 is, for example, a bismuth alloy, a titanium nitride compound, a group or a group of nitrogen compounds, and the like. The material of the top metal layer 1516 is, for example, gold, and the thickness of the top metal layer 1516 is, for example, greater than i micrometers, preferably, for example, greater than 5 micrometers. Further, the bump 16 of the semiconductor wafer 100 may have the same metal layer structure as shown in Fig. 16 as the thick gold f-line 150. Referring to Fig. 17, there is shown a cross-sectional view showing a metal layer stacking structure of a thick metal line of a semiconductor wafer in the first embodiment of the present invention. The thick metal line 150 of the foregoing semiconductor wafer includes, for example, an underlying metal layer 1521 and a top metal layer 1526, and the top metal layer 1526 is tied to the underlying metal layer 1521, wherein the underlying metal layer 1521 is bonded by, for example, The barrier layer 1522, the copper layer 1523, the recording layer 1524, and the gold layer 1525 are formed, and the adhesion/barrier layer 1522 is directly formed on the protective layer 14 (for example, FIG. 2, FIG. 6, FIG. 1). 〇 and Figure (14), on the polymer layer 180 (as shown in Figures 3, 7, U and 15) or on the top film line 137 (Figure 4, Figure 5, Figure 8, Figure 9) 12 and 13), the copper layer 1523 is opened on the adhesion/barrier layer 1522, the nickel layer 1524 is formed on the copper layer 1523, and the gold layer 1525 is formed on the nickel layer leg. The material of the layer 1522 is, for example, tantalum, titanium alloy, titanium nitride compound, niobium or nitrogen compound, or the adhesion/barrier layer 1522 may be formed by sequentially depositing a chromium layer and a chromium-copper alloy layer. The chrome-copper alloy layer is on the chrome layer, and the top metal layer 1526 is formed on the gold layer 1525 of the underlying metal layer 1521, and the top metal layer 15 26, 200814211 The material is, for example, a solder of tin alloy, tin, tin-silver alloy or tin-silver-copper alloy. The thickness j2 of the top metal layer 1526 is, for example, greater than 1 micro#. In the preferred case, for example, In addition, the bump 16 of the semiconductor wafer may also have the same metal layer structure as shown in FIG. 17 as the thick metal line (10). Please refer to 18, the age of the invention invented the first-solid towel A schematic cross-sectional view of one of the metal layer stacking structures of the substrate. The circuit 212 of the substrate 2 includes, for example, an underlying metal layer 2111 and a top metal layer 2116, and the top metal layer 2116 is positioned on the underlying metal layer 2ηι / The underlying metal layer 2111 is composed, for example, of a copper layer 2112 and a nickel layer 2113. The copper layer 2112 is, for example, on the insulating layer of the substrate 2, and the nickel layer 2113 is positioned on the copper layer 2112. The layer 2116 is located on the nickel layer 2113 of the underlying metal layer 2111, and the material of the top metal layer 2116 is, for example, gold. In addition, the pads 214 of the substrate 2 may also have the same wiring 212 as the substrate 2 Metal as shown in Figure 18. Referring to Figure 19, there is shown a schematic cross-sectional view of one of the metal layer stacking structures of the substrate in the first embodiment of the present invention. The circuit 212 of the substrate 200 includes, for example, a bottom layer: a metal layer 2121 and a top layer. The metal layer 2126, the top metal layer 2126 is located on the underlying metal layer 2121, wherein the underlying metal layer 2121 is composed of, for example, a copper layer 2122, a nickel layer 2123, and a gold layer 2124, such as a copper substrate 2122. On the insulating layer of 200, the nickel layer 2123 is tied to the copper layer 2122, and the gold layer 2124 is positioned on the nickel layer 2123. The top metal layer 2126 is located on the gold layer 2124 of the underlying metal layer 2121, and the material of the top metal layer 2126 is, for example, tin-lead alloy, tin, tin-silver alloy or tin-silver-copper alloy solder, wherein the top metal layer 2126 is The gold layer 2124 of the underlying metal layer 2121 may be formed by electroplating; or the top metal layer 2126 25 200814211 may be cured by a lean solder through a reflow step, that is, the screen printing method may be used first. Forming a poor solder (not shown) on the gold layer 2124 of the underlying metal layer 2121 of the substrate, after which the thick metal line 15 of the semiconductor crystal #1G0 can be connected to the paste transfer, and then can be formed through the step of reflow soldering. The _-shaped solder 2126 is on the gold layer 2124 of the underlying metal layer 2121, such that the thick metal lines 15 of the semiconductor wafer 100 and the gold layer 2124 of the underlying metal layer 2121 of the substrate 200 can be connected through the solder 2126. In addition, the pads 214 of the substrate 200 may have the same metal layer structure as shown in FIG. 19 as the lines 212 of the substrate 200. Referring to Fig. 20, there is shown a cross-sectional view showing one of the metal layer stacking structures of the wiring of the substrate in the first embodiment of the present invention. The substrate 212 of the substrate 2 includes, for example, an underlying metal layer 2131 and a top metal layer. The top metal layer 2136 is on the underlying metal layer. The underlying metal layer 2131 includes copper and is disposed on the substrate. 2〇〇 on the insulation layer. The material of the top metal layer 2136 is, for example, a solder of tin-lead alloy, tin, tin-silver alloy or tin-silver-copper alloy. The top metal layer 2136 may be formed on the underlying metal layer 213i by electroplating, for example, or a top metal layer. 2136 may also be formed by paste soldering through a reflow step, ^, that is, a paste solder (not shown) may be formed on the underlying metal layer 2131 of the substrate 2 by screen printing, and then the semiconductor The thick metal line 15 of the wafer can be connected to the cream solder, and then a solid solder 2136 can be formed on the underlying metal layer 2131 via the reflow step, so that the thick metal of the semiconductor wafer 100 can be connected through the solder 2136. The line 15 is connected to the underlying metal layer 2131 of the substrate 200. In addition, the pads 214 of the substrate 200 may have the same metal layer structure as shown in FIG. 20 as the lines 212 of the substrate 200. In the present invention, the connection between the thick metal line 15 of the semiconductor wafer 100 and the line 212 26 200814211 of the substrate 2 can be __, the first method of the gold-gold bonding, that is, the semiconductor wafer The material of the top metal layer of the thick metal line 15G of the hall is gold, and the material of the top metal layer of the miscellaneous line 212 is also gold. When the semiconductor wafer is bonded to the substrate 200, the thick metal line of the semiconductor wafer 100 The 15 顶层 top metal layer can be connected to the top metal layer of the line 212 of the substrate 200 by gold-gold eutectic bonding. For example, the thick metal line 150 of the semiconductor wafer 100 has a metal layer structure as shown in FIG. The wiring line 212 has a metal layer structure as shown in FIG. 18. At this time, the material of the top metal layer 1516 of the thick metal line 150 of the semiconductor wafer and the top metal layer of the line 212 of the substrate are both gold. When the thick metal line (10) of the semiconductor wafer (10) is bonded to the line 212 of the substrate, the top metal layer of the thick metal line 15 of the semiconductor wafer 100 is bonded by means of gold-gold co-gold bonding. The top metal layer 2116 of the line 212 of the board 200. The second type is solder bonding, that is, the material of the top metal layer of the thick metal line (10) of the semiconductor wafer is solder. When the semiconductor wafer (10) is bonded to the substrate, the top layer of the thick metal line (10) of the semiconductor wafer 10G is used. The metal layer can be connected to the line 212 of the substrate 200 by solder bonding. For example, the thick metal line 15 of the semiconductor wafer has a metal layer structure as shown in FIG. 17, and the material of the top metal layer 1526 of the thick metal line 15 of the semiconductor wafer is solder, when the semiconductor wafer is used. When the thick metal line 15 is bonded to the line 212 of the substrate 200, the top metal layer 1526 of the thick metal line 15 of the semiconductor wafer 1 is bonded to the line 2i2 of the substrate 2 by solder bonding. Alternatively, the material of the top metal layer of the line 212 of the substrate 200 may be solder. When the semiconductor wafer 1GQ and the substrate 2GG are bonded, the thick metal line 15 〇 27 200814211 of the semiconductor wafer (10) may be connected by solder bonding. The top metal layer of line 212. For example, the line 212 of the substrate 200 has a metal layer structure as shown in FIG. 19 or FIG. 2B. At this time, the material of the top metal layer 2126 or 2136 of the line 212 of the substrate 2 is a zen material, when the semiconductor wafer 1 When the thick metal line 15〇 is bonded to the substrate-measured line 212, the thick metal line 150 of the semiconductor wafer (10) is bonded to the top metal layer 2126 or 2136 of the substrate 212 by solder bonding. The thick metal line 15 is as shown in FIG. 16, and the top metal layer 1516 is a thick gold layer. In the preferred case, the top metal layer 2126 or 2136 of the line 212 of the substrate (10) is, for example, thick. Thin tin layer. Alternatively, the material of the top metal layer of the thick metal line (10) of the semiconductor wafer and the top metal layer of the line 212 of the substrate 200 may be solder, and when the semiconductor wafer K and the substrate 200 are bonded, the semiconductor wafer The top metal layer of the 1 厚 thick metal line 15 可以 can be connected to the top metal layer of the substrate 212 by solder bonding. For example, the thick metal line 15 of the semiconductor wafer 100 has a metal layer structure as shown in FIG. 17, and the line 212 of the substrate 200 has a metal layer structure as shown in FIG. 19 or FIG. The material of the top metal layer 1526 of the thick metal line 150 and the material of the top metal layer 2126 or 2136 of the circuit board of the substrate are solder. When the thick metal line 150 of the semiconductor wafer is bonded to the line 212 of the substrate 200, the semiconductor wafer The top metal layer 1526 of the thick metal line 15 of 100 bonds the top metal layer 2126 or 2136 of the line 212 of the substrate 2 by solder bonding. Second, the second embodiment of the wafer structure of the thick metal line 150 of the semiconductor wafer 100 in addition to the above can be used to connect with the substrate 2 〇〇 line 28 200814211 way 212 in direct contact, but the semiconductor wafer 1 〇〇 thick metal line (10) It can also be connected in direct contact with the thick metal line 350 of another semiconductor wafer 300, as shown in FIG. 21 to FIG. 47, the half-grain of the towel and the material f are described in the first __ I won't go into details. In the following, there are several possible implementation scenarios: 1. Two interconnected two-thick metal lines of semiconductor wafers are used as the signal transmission in the semiconductor wafer. Please refer to 21 and 22, respectively. The wafer according to the second embodiment of the present invention is a schematic cross-sectional view of the first semiconductor wafer before assembly, wherein the cross-sectional portions of the thick metal lines cut through the two semiconductor wafers are respectively cut perpendicularly along the extending path of the two thick metal lines. Corresponding to the cross section of the semiconductor wafer; FIG. 22 is a schematic cross-sectional view showing the wafer structure after the bonding of the two semiconductor wafers in FIG. Referring to FIG. 21, the semiconductor wafer 300 includes a half-substrate, a plurality of thin film dielectric layers 322, 324, 326, a plurality of thin film wiring layers 332, 334, 336, and a protective layer 340. The semiconductor substrate 310 has a plurality of electronic components 312 disposed on a surface layer of one of the active surfaces 314 of the semiconductor substrate 310, wherein the semiconductor substrate 310 is, for example, a germanium substrate, which is doped with pentavalent or trivalent ions, such as Boron ions or phosphorus ions are formed to form a plurality of electronic components 312 on the surface layer of the semiconductor substrate 31. The electronic components 312 are, for example, metal oxide semiconductors or transistors. A plurality of thin film dielectric layers 322, 324, 326 may be formed on the active surface 314 of the semiconductor substrate 310 by means of chemical gas deposition, wherein the thin film dielectric layers 322, 324, 326 are, for example, oxonium compounds and nitrogen bismuth compounds. Or a oxynitride compound or the like, each of the thin film circuit layers 332, 29, 200814211 334, 336 is disposed on one of the thin film dielectric layers 322, 324, 326, wherein the material of the thin film circuit layers 332, 334, 336 includes , copper or enamel. The thin film dielectric layers 322, 324, 326 have a plurality of via holes 32, 323, 325, and the thin film wiring layers 332, 334, 336 can be electrically connected to each other by the via holes 321 , 323 , 325 of the thin film dielectric layers 322 , 324 , 326 . The connection is made and electrically connected to the electronic component 312. The protective layer 340 is disposed on the thin film dielectric layers 322, 324, 326 and the thin film wiring layers 332, 334, 336, wherein the thickness z of the protective layer 340 is, for example, greater than 〇·35 micrometers, and the structure of the protective layer 340 is a composite layer composed of a nitrogen arsenide compound layer, an oxonium compound layer, a phosphonium glass layer or at least one of the above materials. The protective layer 34 has a plurality of openings 342 exposing the thin film wiring layer 336 located in the top layer. The thick metal line 350 is disposed on the protective layer 340, and is electrically connected to the thin film wiring layer 336 via the opening material 2 of the protective layer 34, wherein the thickness of the thick metal wiring is greater than the thickness of the thin film wiring layers 332, 334, and 336. The pads are substantially aligned with the openings 342 of the protective layer 340 and are electrically coupled to the _ wiring layer 336. In the process, the thick metal line and the connection can be completed by using the same system, so the thick metal line and the pad can have the same metal layer π structure 'thick metal line and pad metal layer structure in As explained in detail later, skip here first. It is worth noting that the thickness of the thick metal line coffee is substantially the upper phase R of the thickness of the pad 36G, wherein the thickness λ of the thickness of the thick metal line 35() is, for example, greater than 1 micrometer, in the preferred case. Below, for example, is greater than 5 microns. ^ , 1〇〇 . 3〇〇 ^ 15〇 ^ 35〇 The 疋/mouth is extended in any direction on the top of the semiconductor wafer 1()(), the top of the coffee, such as the form and diameter of the straight line extending like 200814211. In the Jianqi lamp, the extension path of the two materials knocking forest _ the concave and the twisted material shows a mirror relationship, bribe = thin, thin thick metal line drawing 50 of the ^ ^ conduction body crystal at the time of bonding The semiconductor wafer path 150 can be aligned with the thick metal line 350 of the semiconductor wafer 300. . Referring to FIG. 22', after the two semiconductor crystals are provided, the bonding step can be performed so that the thick metal lines (10) of the semiconductor crystal can directly connect the thick metal lines 35' of the semiconductor wafer and the bumps of the semiconductor wafer (10). (10) The semiconductor crystal can be directly contacted. Then, a polymer layer m can be filled in between the two semiconductor wafers (10), the polymer layer _ cladding thick metal lines, and also coated Bump (10) and junction 36G. Definition—the planar surface is substantially parallel to the main surface 114 of the semiconductor substrate 110, wherein the extension _ s of the two thick metal lines (10) to the flat _ _ is, for example, greater than _鄕, or is greater than 800 microns, or for example greater than 12 〇〇 microns; two thick metal lines 15 〇, the area of the joined area projected onto the plane 1000 is, for example, greater than 3 〇, 平方 square microns, or, for example, greater than 80,000 square microns, or For example, it is greater than 15 〇, 〇〇〇 square micron. In this embodiment, the connection relationship between the thick metal lines 150 and 350 of the semiconductor wafers 100 and 300 is the same as the connection between the thick metal lines 15 of the semiconductor wafer 100 and the line 212 of the substrate 2 in the first embodiment. For a more detailed description, reference may be made to the embodiment in which the thick metal line 150 of the semiconductor wafer 100 and the line 212 of the substrate 200 are the inductive elements in the first embodiment. A clearer understanding of the connection relationship of the thick metal lines 150, 350 of the semiconductor wafers 100, 300 in this embodiment. 31 200814211 Referring to FIG. 22, in the electrical transmission, one of the electronic components 112 in the semiconductor wafer 1 (such as the germanium electrons 112a) is adapted to rotate an electronic signal through the thin film circuit. The layers 132, 134, 136 pass through the protective layer 14 and are transferred to the thick metal lines 150, 350, then through the protective layer 140, and through the thin film wiring layers 136, 134, 132 to the semiconductor wafer 100. At least one of the electronic components 112 (such as the electronic component (4)); at this time, the thick metal line 15G of the semiconductor wafer 100 and the thick metal line 350 of the semiconductor wafer can be used as the signal transmission wheel in the semiconductor wafer 1 . In addition, the electronic signal can be transmitted to the semiconductor wafer 3 after being transferred from the electronic component 112a to the thick metal line 15A, such as the tooth-over protection layer 340 and via the thin film circuit layers 336, 334, to the micro-transmission to The electronic component 312a, at this time, the thick metal line 15 of the semiconductor wafer 1 and the thick metal line 350 of the semiconductor wafer can also be used as the signal of the two semiconductor wafers (10), and the signal is transmitted. One of the electronic components 312 in the semiconductor chip 3 (such as the electronic component 312a) is also adapted to output an electronic signal, and the electronic signal is transmitted through the thin film circuit layers 332, 334, and then transmitted to the The thick metal wire, (10), then passes through the protective layer (10) of the semiconductor wafer (10), and is transferred to the at least one electronic component 112 (such as the electronic component and 112b) in the semiconductor wafer (10) via the thin film wiring layers 136, 134. The thick metal line 15 of the semiconductor positive film 100 and the thick metal line 350 of the semiconductor wafer can be used as the lateral transmission of the electronic signal, and can also be used as the two semi-conducting body I0. To pass round. Since the thick metal line of the semiconductor crystal is directly connected to the thick metal line 35 of the semiconductor wafer, the semiconductor wafer is thin. The 3214214211 thick metal line 150 can electrically connect the thick metal line of the semiconductor wafer to a large area. 35〇, this can greatly increase the efficiency of the two semiconductor crystals; ^ _, the electrical connection between the earthquakes, and can reduce the generation of noise. In addition, referring to FIG. 22, the semiconductor wafer 1 can transmit an electronic signal to the semiconductor wafer through the bump 16 of the semiconductor wafer 1 and the pad 360 of the semiconductor wafer, or can be received by the semiconductor wafer 300. The electronic signal passed. In Fig. 21 and Fig. 22, the thick metal lines 15〇 and 35 are formed directly on the protective layer. 340; however, the thick metal lines 15〇 may also be formed on the polymer layers on the protective layers (10), 340, respectively, or may be thick metal lines 35〇 formed on the protective layer 340. On the object layer, the thick metal line 15 is formed directly on the protective layer 14〇; or, the thick gold line 150 may be formed on the polymer red on the protective layer 14 (), and the thick metal line is directly Formed on the protective layer 34, as shown in Fig. 23, the edge shows a schematic cross-sectional view of another wafer according to the first embodiment of the present invention. Only the embodiment in which the thick metal line of one of the above-mentioned thick metal lines is disposed on the polymer layer is shown here. The structure of other thick metal lines not shown on the polymer layer can be in accordance with the thick metal line of FIG. The structure placed on the polymer layer is similar. Referring to FIG. 23, a polymer layer (10) is formed on the protective layer 14A. The polymer layer (10) has a plurality of openings 182 substantially aligned with the openings 142 of the protective layer (10), and the thick metal lines 15 are formed in the polymerization. The layer 180 is attached to the thin film wiring layer 136 via the opening 182 of the polymer layer (10) and the opening 142 of the protective layer (10). A thick metal line 35 is formed in direct contact with the protective layer 340, and is connected to the thin film wiring layer via the opening 342 of the protective layer 34. It is worth 33 200814211 to note that the thickness h of the bump 160 protruding beyond the opening i82 of the polymer layer 180 is, for example, substantially the same as the thickness j of the thick metal line 150 on the polymer layer 180, and the thick metal line 150 has the same metal layer structure as the bump 160, wherein the thickness h of the bump 160 protruding beyond the opening 182 of the polymer layer 18 and the thickness j of the thick metal line 150 located on the polymer layer 180 are, for example, More than 1 micron, in preferred cases, such as greater than 5 microns. The thickness k of the polymer layer 180 is, for example, greater than 1 micrometer, and the material of the polymer layer 180 is, for example, polyimide (PI), benzocyclobutene (BCB), polyaryl ether ( Parylene), porous dielectric material or elastomer. In FIGS. 21 to 23, the thick metal lines 150, 35 are connected to the thin film wiring layers 136, 336 of the top layer through the small openings 142, 342 of the protective layers ι4, 34; however, the thick metal lines 150, The 350 may also be a thin film connection layer 136, 336 that is connected to the top layer through the large openings m2, 342 of the protective layers 14, 34, including the following possible implementations. The first embodiment is a thick metal line 150 which is connected to the top layer of the thin film circuit layer 136 in a small area, and the thick metal line 350 is connected to the top layer of the thin film circuit layer in a large area; the second implementation case: the thick metal line 150 is large The thin film circuit layer 136 is connected to the top layer, and the thick metal line 35 is connected to the thin layer of the top layer of the thin layer, as shown in FIG. 24 and FIG. 25; the third embodiment, the thick metal lines 150 and 350 are both The thin film circuit layers 136 and 娜 of the top layer are connected to each other over a large area, as shown in FIGS. 26 and 27. Only the second embodiment and the third embodiment are shown here, and the first embodiment, not shown, can connect the structure of the thin film circuit layer of the top layer with great pain in accordance with the thick metal lines of FIG. 24 to FIG. And so on. Referring to FIG. 24 to FIG. 27, in the semiconductor wafer, the top film line layer 136 has 34 200814211-film line 137, and the opening 142 of the protective layer 140 exposes the thin film line 137 over a large area, so that the thick metal line 150 The film line 137 exposed by the opening 142 of the protective layer 140 can be connected over a large area. Definition - plane 1 〇〇〇, the plane plane is substantially parallel to the active surface 114 of the semiconductor substrate 110, the area of the area where the thick metal line 15 〇 is connected to the film line 137 is projected onto the plane 1000 divided by the film line 137 鄕The ratio of the area on the plane 1 比如 is, for example, greater than 0.5, or such as greater than 〇·8, or, for example, the opening 142 of the protective layer 140 is substantially equal to the exposed film, and the area of the line 137 is greater than 3 〇, the square of the square micrometer, or such as more than 80,000 square micrometers, or such as more than 15 inches, the square of the square. The area of the region where the thick metal line 150 is connected to the thin film wiring layer 136 is projected onto the plane 1 to an extent such as greater than 500 microns, or such as greater than 8 microns, or such as greater than a micron. In the present embodiment, the semiconductor wafer shown in FIGS. 24 to 27 has a connection relationship between the thick metal line 15A and the thin film line 137, which is the same as the semiconductor wafer 100 shown in FIGS. 4 to 5 in the first embodiment. The connection relationship between the thick metal line 15A and the thin film line 137 is more detailed. It can be referred to the thick metal line 150 and the thin film line 137 of the semiconductor wafer 1 exemplified in the first embodiment. The embodiment of the inductive component, if reference is made to the description of this section, will have a clearer understanding of the connection relationship between the thick metal line (10) of the semiconductor wafer (10) and the thin film line (3). Further, in addition to the above-mentioned thick metal line 15Q, which can connect the top film layer 136 over a large area, the thick metal line 35 can also be connected to the top film layer 6 in a large area, as shown in Figs. 26 and 27. The top film line layer 336 has a film line 337, and the opening 342 of the protective layer 34() 35 200814211 exposes the film line 337 over a large area, so that the thick metal line 35 can be connected to the opening 342 of the protective layer 340 over a large area. The exposed film line 337. A plane _ is defined which is substantially parallel to the active surface 314 of the semiconductor substrate 310. The area of the area where the thick metal line 350 is connected to the film line 337 is projected onto the plane 1〇5〇 divided by the film line 337 projected onto the plane. The ratio of the area above is, for example, greater than 〇·5, or such as greater than 0·8, or such as an opening 342 that is substantially equal to the protective layer 34〇 exposing the area of the thin film line 337, such as more than 3 〇, 咖平方Micron, or for example, greater than 8 turns, coffee square microns, or such as greater than 150,000 square microns. The area where the thick metal line is connected to the thin film line layer 336 is projected onto the plane by an extension distance τ, for example, greater than a circular micrometer, or such as greater than _micron, or such as greater than 12 Å. In this embodiment, the thick metal line 35A and the thin film line 337_ of the semiconductor wafer 3 shown in FIG. 26 and FIG. 27 are identical to the semiconductor wafer 100 shown in FIGS. 4 to 5 in the first embodiment. For a more detailed description of the connection between the thick metal line 150 and the thin film line 137, reference may be made to the embodiment in which the thick metal line and the thin film line 137 of the semiconductor wafer (10) exemplified in the first embodiment are inductive elements. If the description of this part is referred to, a clear understanding of the miscellaneous relationship between the thick metal line of the semiconductor wafer and the film line in this embodiment will be provided. Referring to FIG. 24 and FIG. 25, in the electrical transmission, one of the electronic components 112 in the semiconductor wafer 1 (for example, an electronic component is adapted to output an electronic signal, and the electronic signal passes through the thin film wiring layer 132. And 134, transmitted to the thin film line 13 and the thick metal lines 15〇, 35〇, and then transferred to at least one of the other electronic components 36 200814211 112 in the semiconductor wafer (10) via the thin film wiring layers m, 132 (such as It is an electronic component U2b); at this time, the thick metal line 150 of the semiconductor wafer 1 and the thick metal line 350 of the semiconductor wafer 300 can be used for signal transmission in the semiconductor wafer 1. In addition, the electronic signal is in the electronic device. After being transmitted to the thin film line 137 and the thick metal lines 150, 350, the element 112a may also be transferred into the semiconductor wafer, for example, through the protective layer 340 and transmitted to the electronic component 312a via the thin film wiring layers 336, 334, 332; The thick metal line 15 of the semiconductor wafer 100 and the thick metal line 350 of the semiconductor wafer 3 can also be used as the signal transmission between the two semiconductor wafers 1 and 3 In addition, referring to FIG. 24 and FIG. 25, one of the electronic components 312 in the semiconductor wafer 3 (for example, the electronic component 312a) is integrated with the output electronic signal via the thin film circuit layers 332, 334, And passed through the protective layer 34〇 to the thick metal lines 35〇, 15〇 and the thin film line 137, and then transferred to the at least one electronic component 112 in the semiconductor wafer 1 via the thin film wiring layers 134, 132 (for example, The electronic components 112a, U2b). The difference between FIG. 24 and FIG. 25 is whether the semiconductor wafer 1 is provided with a polymer layer 18 on the protective layer 140, wherein the semiconductor wafers (10) of FIG. 25 are respectively identical. The structure of the semiconductor wafer (10) of FIGS. 4 and 5 in the first embodiment will not be described herein. Referring to FIG. 26 and FIG. 27, in the electrical transmission, the electronic component 112 in the semiconductor wafer 1 is The towel-recording electronic component is suitable for outputting an electronic signal, which is transmitted from the film circuit layer 132, 134 to the film line (3), the thick metal line (10), the a% 莼, the line 337, and then through the film. Line layer 134, 132 pass At least one of the electronic components 112 (for example, the electronic component 112b) is transferred to the semiconductor wafer, and the thick metal line 15 of the semiconductor wafer 100 and the thick metal wiring of the semiconductor wafer 3 Nako 37 200814211 is used for signal transmission in the semiconductor wafer 100. In addition, the electronic signal can be transmitted after being transmitted from the electronic component 112a to the thin film line 137, the thick metal lines 15〇, 35〇, and the film line 337. Up to the semiconductor wafer 300, for example, through the thin film lines 334, 332 to the electronic component 312a; at this time, the thick metal line 150 of the semiconductor wafer 1 and the thick metal line 350 of the semiconductor wafer 3 can also be used as two The semiconductor chip is used for signal transmission between 〇〇 and 〇〇. In addition, referring to FIG. 26 and FIG. 27, one of the electronic components 312 in the semiconductor wafer 300 (such as the electronic component 312a) is also adapted to output an electronic signal transmitted to the film via the thin film wiring layers 332, 334. Lines 337, thick metal lines 350, 150, and thin film lines 137 are then transferred via thin film line layers 134, 132 to at least one electronic component 112 (such as electronic components H2a, H2b) within semiconductor wafer 1 . 26 is different from FIG. 27 in that the semiconductor wafers 1 and 3 are provided with the polymer layers 180 and 380 on the protective layers 140 and 340, and the structures of the semiconductor wafers of FIGS. 26 and 27 are used. The structures of the semiconductor wafers 1 and 5 of the first embodiment are similar to those of the first embodiment, and will not be described again. Referring to FIG. 26, after the protective layer 34 is formed on the semiconductor wafer 300, a thick metal line 350 and a pad 360 are simultaneously formed on the thin film circuit layer 336, wherein the thickness H of the pad 36 is substantially the same as the thickness. The thickness j of the metal line 350, and the metal layer structure of the pad 36A is substantially the same as the metal layer structure of the thick metal line 350, wherein the thickness of the pad 3 (9) {{and the thickness J of the thick metal line 350 is greater than 1 Micron, in preferred cases, such as greater than 5 microns. However, referring to FIG. 27, after forming the protective layer 34, the semiconductor wafer 300 further forms 38 200814211 to pattern one of the polymer layers 380 on the protective layer 340. The thickness κ of the polymer layer 380 is, for example, greater than 1 micron. The material of the polymer layer 380 is, for example, poiyimide (pi), benzocyclobutene (BCB), polyarylene ether (poryiene), a porous dielectric material, or an elastomer. The polymer layer 380 has an opening 382 exposing the top film layer 336 of the top layer, including exposing the film line 337. Then, a thick metal line 35 and a pad 360 can be simultaneously formed on the film circuit layer 336, wherein the thickness of the pad 360 protruding from the opening 3 of the polymer layer 38 is, for example, substantially the same as the protrusion. The thickness of the thick metal line 350 outside the opening 3 of the layer 38 is the thickness J of the thick metal line 350, and the metal layer structure of the pad 360 is substantially the same as the metal layer structure of the thick metal line 350, wherein the opening of the polymer layer 38 is protruded. 3 The thickness of the outer pad 360 is, for example, greater than 1 micrometer, preferably, for example, greater than 5 micrometers; the thickness of the thick metal wire protruding beyond the opening π 382 of the polymer layer; [Micron' is preferably greater than 5 microns, for example. 2. The two thick metal lines interconnected by the two semiconductor wafers serve as signal transmission between the two semiconductor wafers. Referring to Figures 28 to 33, there is shown a cross-sectional view of another type of wafer assembly in accordance with a second embodiment of the present invention, wherein the semiconductor wafers (10) of Figures 28 through 33 are identical to the semiconductors of Figures 22 through 27, respectively. The wafer 100, and the semiconductor wafers of the drawings are similar to those of the semiconductor wafers of FIG. 22 to FIG. 27, and will not be described here; the difference is that the half is _>u〇〇' 15G, 35 () The use of the signal transmission between the syllabus and the syllabus is not used as the symphony wheel in the semiconductor wafer (10), as described below. 39 200814211 Referring to FIG. 28 and FIG. 29, in electrical transmission, one of the electronic components 112 in the semiconductor chip 1 (for example, the electronic component U2a) is adapted to output an electronic signal, and the electronic signal is transmitted through the thin film circuit. Layers 132' 134, 136 pass through protective layer 14 and are transferred to thick metal lines 150, 350 of semiconductor wafers 100, 300, then through protective layer 340 of semiconductor wafer 300, and via thin film wiring layers 336, 334, 332 is transferred to one of the electronic components 312 (such as electronic component 312a) within semiconductor wafer 300. Alternatively, one of the electronic components 312 in the semiconductor wafer 300 (such as the electronic component 312a) may also be adapted to output an electronic signal that is transmitted through the thin film wiring layers 332, 334, 336 and through the protective layer 340. The thick metal lines 350, 150 to the semiconductor wafers 300, 100, then pass through the protective layer 14A of the semiconductor wafer 1 and are transferred to the electronic components 112 within the semiconductor wafer 1 via the thin film wiring layers 136, 134, 132. One of them (for example, electronic component n2a). At this time, the thick metal lines 150 and 350 of the semiconductor wafers 1 and 300 serve as signal transmission between the semiconductor wafers 1 and 3. Referring to FIGS. 30 and 31, in electrical transmission, one of the electronic components 112 (such as the electronic component 112a) in the semiconductor wafer is adapted to output an electronic signal via the thin film wiring layers 132, 134. The thick metal lines 150, 35A transferred to the thin film line 137 and the semiconductor wafers 100, 300 are then passed through the protective layer 340 of the semiconductor wafer 3 and transferred to the semiconductor wafer 3 via the thin film wiring layers 336, 334, 332. One of the electronic components 312 (such as the electronic component 312a). Alternatively, one of the electronic components 312 in the semiconductor wafer 300 (such as the electronic component 312a) can also be adapted to output an electronic signal through the thin film wiring layers 332, 334, 336 and through the protective layer 340. The thick metal lines 35A, 150 and the thin film lines 137 are transferred to the semiconductor wafer 300, and then transferred to one of the electronic components 112 (such as the electronic component U2a) in the semiconductor wafer 100 via the thin film wiring layers 134, 132. . At this time, the thick metal lines 150 and 350 of the semiconductor wafers 100 and 300 serve as signal transmission between the semiconductor wafers 1 and 300. Referring to FIG. 32 and FIG. 33, in electrical transmission, one of the electronic components 112 in the semiconductor wafer (for example, the electronic component 112a) is adapted to output an electronic signal, and the electronic device 5 passes through the thin film circuit layer 132. 134 is transferred to the thin film line I", the thick metal lines 150, 350 of the semiconductor wafers 100, 300, and the thin film line 337, and then transferred to one of the electronic components 312 in the semiconductor wafer 300 via the thin film wiring layers 334, 332 (such as germanium electrons) Element 312a). Alternatively, one of the electronic components gig in the semiconductor chip 3 (such as the electronic component 312a) may also be read out - an electronic signal transmitted to the film line via the thin film wiring layers 332, 334. 336. The semiconductor wafers 3, 1 厚 thick metal lines 350, 150 and the thin film lines 137 are then transferred via the thin film wiring layers 134, 132 to one of the electronic components 112 within the semiconductor wafer (eg, electronic At this time, the thick metal lines 15 〇 and 35 半导体 of the semiconductor wafer 1 〇〇, 3 〇 are used for signal transmission between the semiconductor wafers 100 and 300. The thick metal lines 15〇 and 35〇 of the semiconductor wafers 1 and 300 can be used as the lateral transmission of the electronic signals, and can also be used as the longitudinal transmission of the semiconductor wafers. The thick metal lines of the semiconductor wafers 1GG. (10) The thick metal line 35G of the semiconductor wafer 3GG is directly contacted with the ground connection of the semiconductor chip 3GG. Therefore, the thick metal line 150 of the semiconductor chip can be electrically connected to the thick metal line 35 of the semiconductor wafer by a large area, which can greatly increase The efficiency of electrical connection between the semiconductor wafers 1 and 3, and the generation of noise can be reduced. Further, please refer to FIG. 28 to FIG. 33, through the bumps 16 of the semiconductor wafer 1 and the semiconductor wafer 300 The pad 360, the semiconductor wafer 1 can transmit an electronic signal to the semiconductor wafer 300' or can receive an electronic signal transmitted from the semiconductor wafer 3. - FIG. 34 to FIG. 39, which illustrate another type of wafer assembly in accordance with a second embodiment of the present invention, for use as an electrical shunt or ground busbar for a half-V body (9) interconnecting two thick metal lines. The semiconductor wafer (10) of FIGS. 34 to 39 is the same as the semiconductor wafer 1 of FIG. 22 to FIG. 27, and the semiconductor wafer 300 of FIGS. 34 to 39 is the same as that of FIGS. 22 to 27. The semiconductor wafer is fine and will not be mentioned here; the quasi-different point is that the semiconductor wafer 1 〇〇 thick metal line (10) is used as a " power bus or ground bus, as described below. Referring to FIG. 34 to FIG. 39, when the semiconductor wafer (10), the thick metal line 15〇, and the coffee system are used as the power bus, the semiconductor wafer 1 and the thick metal lines 15 and 350 are electrically connected to the semiconductor wafer. The power supply bus I% within (10), such as provided by the thin film circuit layer 134, and also electrically connected to the power supply bus 5 within the semiconductor wafer, such as provided by the thin film wiring layer 334. Since the thick metal line 150 of the semiconductor wafer is directly connected to the thick metal line 42 200814211 350 ' of the semiconductor wafer, and electrically connected to the power bus 135, 335 in the semiconductor wafer 1GG, 3GG, The reduction of the voltage of the semiconductor wafer (10) and the power supply bus, Na Na, Na, Na, due to signal interference, and the conductor chip 100, 300 can provide a relatively stable power supply voltage. Ming Shenguan 34 to Fig. 39, when the semiconductor chip 1〇〇, 3〇〇 thick metal line 15〇, is used as the grounding machine row, the semiconductor wafer, the thick metal line (10), 350 series are electrically connected to The ground busbar 135' within the semiconductor wafer 1 (10) is provided, for example, by a thin film wiring layer 134, and is also electrically connected to a ground busbar 335 within the semiconductor wafer, such as provided by a thin film wiring layer 334. The thick metal line 150 of the semiconductor wafer (10) is connected to the thick metal line of the semiconductor wafer 3 (10) in a large area and is electrically connected to the ground bus 135 and the coffee in the semiconductor wafers (9), 3 (10), so that the semiconductor wafer can be reduced by 4 (10), the grounding bus 135 of the coffee, the degree of voltage change caused by the signal interference, and the semiconductor chip (10), the coffee can provide a relatively stable ground voltage. 4. The two-thick metal wiring of the two semiconductor wafers is used as a signal transmission in one of the semiconductor wafers. FIG. 40 to FIG. 43 are diagrams showing another type of wafer structure according to the second embodiment of the present invention. The schematic diagram of the semiconductor wafer of FIG. 4A and FIG. 42 is the same as that of the semiconductor wafer of FIG. The semiconductor wafer (10) of FIG. 41 and FIG. 43 is the same as the semiconductor wafer of FIG. 23, and the semiconductor wafer of FIG. 4 is similar to the semiconductor wafer of FIG. 22, and the semiconductor wafer of FIG. 42 and FIG. 43_ The same is true of the semiconductor wafer 3 of FIG. 43 200814211 26, which will not be described herein; the difference is that the thick metal line 150 of the semiconductor wafer and the thin film wiring layers 132, 134 in the semiconductor wafer 100, 136 is in an electrically disconnected state, and the thick metal lines 150 and 350 of the semiconductor wafers 1 and 3 are used for signal transmission in the semiconductor wafer 3, as described below. Referring to FIG. 40 to FIG. 43, when the thick metal lines 15 and 350 of the semiconductor wafers 1 and 300 are used for signal transmission in the semiconductor wafer 3, one of the electronic components 312 in the semiconductor wafer 3 (10). (for example, electronic component 312a) is adapted to output an electronic signal that is transmitted through thin film wiring layers 332, 334, 336 and through protective layer 34, and then to thick metal lines 350, 150 of semiconductor wafers 300, 100. And then passing through the protective layer 340 and transmitted to at least one of the other electronic components 312 (such as the electronic component 312b) in the semiconductor wafer 3 via the thin film wiring layers 336, 334, 332; wherein the electronic signal The thick metal lines 35A, 150, which are not via the semiconductor wafers 3, 1 , are directly transferred into the semiconductor wafer 1 . At this time, the thick metal line 150 of the semiconductor wafer 1 and the thick metal line 350 of the semiconductor wafer 300 can be used for signal transmission in the semiconductor wafer 300, and not used for signal transmission in the semiconductor wafer 100 or the semiconductor wafer 100. , 300 signal transmission. Since the thick metal line 150 of the semiconductor wafer is directly connected to the thick metal line 350 of the semiconductor wafer 300, the thick metal line 150 of the semiconductor wafer 100 can electrically connect the thick metal line 350 of the semiconductor wafer 300 over a large area. This can increase the electrical transmission quality of this electronic signal. The two-thick metal circuit of the two semiconductor wafers is used as a power source g-plane or a ground bus of one of the semiconductors 44 200814211. FIG. 44 to FIG. 47, (four) according to the first embodiment of the present invention A cross-sectional view of another type of wafer assembly, wherein the semiconductor wafer of FIG. 44 and FIG. 46 is identical to the semiconductor wafer of FIG. 22 and the semiconductor wafer (10) of FIG. 47 is identical to the semiconductor wafer of FIG. 4() and the semiconductor wafer of FIG. 41 are identical to the semiconductor wafer of (4) to FIG. 37, and the semiconductor wafers of FIGS. 42 and 43 are similar to the semiconductor wafer 3 of FIG. 38 and FIG. 39, here. It is no longer praised; the only difference is that the thick metal line (10) of the semiconductor wafer and the thin film circuit layers 132, 134, and 136 in the semiconductor wafer (10) exhibit an open circuit test state, and the rotating wafer is just 300 Thick metal lines 15 〇, coffee is used as a semiconductor wafer _ power bus or ground busbar 'as follows. Referring to FIG. 44 to FIG. 47, when the thick metal line 15 of the semiconductor wafer 100 is used as the power bus of the semiconductor wafer 300, the semiconductor wafer i (9) and the thick metal lines 150, 350 are electrically connected to the semiconductor wafer. The power bus 335, the power bus 335 is provided by the thin film circuit layer 334 of the semiconductor wafer 300, wherein the thick metal lines 15 and 350 of the semiconductor wafer 100, 300 are connected to the power supply in the semiconductor wafer 1 There is an electrical disconnect between the rows. Since the thick metal line 150 of the semiconductor wafer is directly connected to the thick metal line 350 of the semiconductor wafer 300 and electrically connected to the power bus 335 ' in the semiconductor wafer 300, the power of the semiconductor wafer 3 can be reduced. The bus bar 335 is electrically variable due to signal interference, and the semiconductor wafer 300 can provide a relatively stable power supply voltage. 45 200814211 口月", 44 to 47, when the thick metal line 15 of the semiconductor wafer is used as the ground bus of the semiconductor wafer 300, the thick metal line 150 of the semiconductor wafer 1〇〇, 3〇〇, The 350 series is suitable for electrically connecting the ground bus bars of the semiconductor wafer, and the ground bus bar 335 is provided by the thin film circuit layer 334 of the semiconductor wafer 3, wherein the thick metal lines of the semiconductor wafers 1G0 and 3GG are 15 An electrical disconnection occurs between the ground bus and the ground bus in the semiconductor wafer. The thick metal line 150 of the semiconductor wafer is directly connected to the thick metal line 35 of the semiconductor wafer, and is electrically connected to the semiconductor. The ground bus bar 335 in the wafer 300 can reduce the degree of voltage variation of the ground bus bar 335 of the semiconductor chip 3 due to signal interference, and the semiconductor chip 300 can provide a relatively stable ground voltage. The metal layer structure of the interconnected two-thick metal lines is in this embodiment, regarding the thick metal line 15 of the semiconductor wafer 1 For example, there is a metal layer structure as shown in FIG. 16 or FIG. 17 in the first embodiment, which will not be described again. Referring to FIG. 48, a semiconductor wafer 3 is illustrated in the second embodiment of the present invention. A schematic cross-sectional view of one of the metal layer stacking structures of the thick metal line 350. The thick metal line 350 of the semiconductor wafer 300 includes, for example, an underlying metal layer 3511 and a top metal layer 3516, and the underlying metal layer 3511 is formed directly on the protective layer 340, for example. Upper (as shown in Figures 21 to 25, 28 to 31, 34 to 37, 40, 41, 44 and 45) or the top film line 337 (Figure 26, Figure 27, 32, FIG. 33, FIG. 38, FIG. 39, FIG. 42, FIG. 43, FIG. 46 and FIG. 47), the top metal layer 3516 is on the bottom layer 46 200814211 metal layer 3511, wherein the material of the bottom metal layer 3511 is as The material of the top metal layer 3516 is, for example, gold, and the thickness J1 of the top metal layer 3516 is, for example, greater than ! micron, in a preferred case, such as a system. More than 5 microns. In addition, the semiconductor wafer 300 The 塾36〇 may also have the same metal layer structure as shown in FIG. 48 as the thick metal line 350. Please refer to FIG. 49, which shows the metal of the thick metal line 350 of the semiconductor wafer in the embodiment of the present invention. A schematic diagram of a layered structure. The thick metal line of the semiconductor wafer 300 includes, for example, an underlying metal layer and a top metal layer 3526. The top metal layer 3526 is positioned on the underlying metal layer 3521, wherein the underlying metal layer 3521 is bonded by an adhesive layer. The barrier layer 3522, a copper layer 23, a nickel layer 24 and a gold layer 3525 are formed, and the adhesion/barrier layer 3522 is formed directly on the protective layer 340, for example (FIG. 21 to FIG. 25, FIG. 28). As shown in FIG. 31, FIG. 34 to FIG. 37, FIG. 40, FIG. 41, FIG. 44 and FIG. 45) or the top film line 337 (FIG. 26, FIG. 27, FIG. 3, FIG. 38, FIG. 42, FIG. 43, FIG. 46 and FIG. 47), a copper layer (4) is formed on the adhesion/barrier layer 3522, a nickel layer 3524 is formed on the copper layer 3523, and a gold layer 3525 is formed on the 3524. The material f of the adhesive/transfer layer 3522 is, for example, titanium, agglomerated alloy titanium nitrogen compound, group or group nitrogen compound, etc. Alternatively, the adhesion/barrier layer 3522 can also be formed by sequentially depositing a chromium layer and a chromium-copper alloy layer, wherein the chromium-copper alloy layer is on the chromium layer. The top metal layer 3526 is formed on the gold layer 3525 of the underlying metal layer 3521, and the material of the top metal layer 3526 is, for example, a solder of a tin-alloy, tin, tin-silver alloy or tin-silver steel alloy. The thickness J2 is, for example, greater than i microns, and in the case of the preferred 47 200814211 'such as greater than 5 microns. Further, the pads 36 of the semiconductor wafer may have a metal layer structure as shown in Fig. j7 which is the same as the thick metal and the wiring 350. In the present invention, the connection manner of the semiconductor wafer 100 and the thick metal lines 150 and 350 can be roughly divided into two mechanisms. The first type is a gold-gold eutectic bonding method, that is, a semiconductor wafer just and coffee. The thick metal line and the top metal layer of the coffee are all gold. When the semiconductor wafers 100 and 300 are bonded, the thick metal line 15G_metal layer of the semiconductor wafer 100 can be bonded through the gold-gold eutectic. The top metal layer of the thick metal line 35A of the semiconductor wafer 300 is connected, for example, the material line (10) of the semiconductor wafer (10) has a metal layer structure as shown in FIG. 16, and the thick metal line 350 of the semiconductor wafer 3 has The metal layer structure shown in FIG. 48, in which the top metal layer 1516 of the thick metal line 15 of the semiconductor wafer (10) and the metal layer 3516 of the thick metal line 350 of the semiconductor wafer are all gold, when the semiconductor wafer When the thick metal line 150 of the (10) is bonded to the thick metal line of the semiconductor wafer 3 (9), the top metal layer 1516 of the thick metal line 150 of the semiconductor wafer 1 is bonded by gold and gold. A thick metal top lines of bonding the semiconductor wafer 3〇〇 35〇 metal layer of coffee. The second type is a solder joint, that is, the thick metal line of the semiconductor wafer (10) = the metal layer of the material is solder, # semiconductor wafer (10), when the joint is joined, "the top metal of the thick metal line of the sheet The layer can be joined to the thick metal line of the semiconductor wafer 300 by solder bonding. For example, the thick metal line 150 of the semiconductor wafer (10) has a metal layer structure as shown in FIG. 17, and the top layer of the thick metal line (10) of the semiconductor wafer 100 at this time. The material of the metal layer inspection is a rod material. When the thick metal line 150 of the semiconductor 48 200814211 ( ^ (10) is bonded to the thick metal line of the semiconductor wafer _ the thickness of the semi-finished metal layer 1526 of the thick metal lining 15G of the semiconductor crystal is utilized. Tan bonding method to bond the semiconductor crystal; ί thick metal line _. If the thick metal line 350 of the semiconductor cymbal is as shown in Fig. 48, the top metal layer 3516 _ 曰 thick gold layer, in the better case The top metal layer of the thick metal line (10) of the semiconductor wafer (10) is, for example, a tin layer having a very thin thickness. Alternatively, it may be a top of a thick metal line 35 of the semiconductor wafer. The material of the layer metal layer is solder. When the semiconductor wafer is bonded, the thick metal line (10) of the semiconductor wafer (10) can be bonded to the top metal layer of the thick metal line 350 of the semiconductor wafer by solder bonding. For example, a semiconductor The thick metal line of the wafer has a metal layer structure as shown in FIG. 49. At this time, the thick metal line 3 of the semiconductor wafer 300, the material of the layer metal layer 3526 is made of solder as a semiconductor wafer (10), thin thickness = genus When the lines 150, 350 are joined, the thick metal line (10) of the semiconductor wafer is bonded to the top metal layer of the thick metal line of the semiconductor wafer 3 in a manner that is connected to the interface. If it is a thick metal line 150 of the semiconductor wafer (10) As shown in FIG. 16, the metal layer 1516 is a thick gold layer. In the preferred case, the top metal layer of the semiconductor wafer 30k thick metal line is, for example, a thin tin layer. It is also possible to use a thick metal line (10), a top layer, and a 'layer' of the semiconductor wafer as a solder. When the semiconductor wafer (10) is bonded, the semiconductor wafer 1GD The top metal layer of the thick metal line 150 can be soldered to the metal layer of the thick metal line connecting the semiconductor aa# _. For example, the thick metal line 150 of the semiconductor wafer (10) of the semi-conductive 49 200814211 has the structure shown in FIG. The metal layer structure, the thick metal line of the semiconductor wafer has a thick metal line as shown in FIG. 49, and the metal layer of the thick metal line is written as the metal layer of the thick metal line 3526. : When the thick metal lines (10) and 35 体 of the body wafers 100 and 300 are bonded, the top metal layer 1526 of the thick metal line 150 of the semiconductor wafer 1 (10) is connected by means of floating joints = thick metal of the | The top layer metal layer 3526 of the line 35. III. Third Embodiment of Wafer Construction In the above implementation, the thick metal line (10) of the semi-dragon wafer (10) is directly connected to the line 212 of the substrate 2GG, as described in the first embodiment, or directly connected. Another thick semiconductor circuit of the semiconductor wafer is as described in the second embodiment. However, the application of the present invention is not limited thereto, and the thick metal line (10) of the semiconductor wafer may be electrically connected to the line 412 of a circuit connecting member 400 through a conductive layer containing the polymer 452 and the plurality of metal particles 454. As shown in FIG. 50 to FIG. 54 , the structure and material of the semiconductor wafer 1GG are described in detail in the first embodiment, and are not described herein again. The circuit connecting member 400 is, for example, a semiconductor wafer of any type or Beautiful board. In this embodiment, the circuit connecting member 4 is, for example, a glass substrate. Generally, the wiring layer 410 of the glass substrate 400 is formed, for example, of transparent indium tin oxide. In the embodiment, the circuit layer 410 is, for example. Line 412 and pads 414 are included. The following diagrams illustrate several possible implementation scenarios: 1. The circuit of the metal circuit and the glass substrate of the half V body is used as the reference for the signal transmission in the semiconductor wafer 50 200814211. FIG. 5( 纟 纟 纟 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体The extension path of the thick metal line is obtained by cutting the cross section of the semiconductor wafer vertically; FIG. 51 is a schematic cross-sectional view showing the wafer structure of the semiconductor wafer and the glass substrate in FIG. Referring to FIG. 50, before the semiconductor wafer 100 is bonded to the glass substrate 400, a conductive layer 450 such as an anisotropic conductive paste (ACP) or an anisotropic conductive film (ACF) may be used. First formed on the glass substrate 400, which is formed on the wiring 412 of the glass substrate 4 and the pad 414 of the glass substrate 400. The composition of conductive layer 450 includes polymer 452 and a plurality of metal particles 454 that are distributed in polymer 452. In the form of a line, the line 412 of the glass substrate 4 can extend in the top of the glass substrate 400 in any direction, such as in the form of a straight line extending, in the form of a curved extension, or in the form of a discontinuous concave portion. The extension path. In a preferred case, the thick metal line 15 of the semiconductor wafer 100 is in a mirror relationship with the line 412 of the glass substrate 400, so that when the semiconductor wafer 1 is bonded to the glass substrate 400, the semiconductor wafer 100 The thick metal line 150 can be aligned with the line 412 of the glass substrate 400. In one embodiment, the thick metal line 150 of the semiconductor wafer and the line 412 of the glass substrate 4 are, for example, spiral inductor elements, as shown in FIGS. 50A and 50B, wherein FIG. 50A is in FIG. The line 412 of the glass substrate 400 is projected onto the plane 51 200814211 on the plane 1〇5〇; FIG. 50B is a schematic plan view of the thick metal line 15〇 of the semiconductor wafer loo in FIG. 50 projected onto the plane 1000. Referring to FIG. 50A and FIG. 50B, a mirrored relationship between the winding path of the semiconductor device 1 and the winding path of the line 412 of the glass substrate 400 is shown. The inductive component 412 of the glass substrate 400 is shown in FIG. The extension extends along the path 11〇〇, for example, from the X point of the path 1100 to the γ point of the path 11〇〇; the inductive component 150 of the semiconductor wafer 100 extends along the path 1200, such as from the path 12 The point extends to the y point of path 1200. Referring to FIG. 51, after the semiconductor wafer 1 and the glass substrate 4 are provided, the step of bonding can be performed, so that the thick metal line 15 of the semiconductor wafer 100 can be pressed into the conductive layer 450 on the glass substrate 400. The thick metal lines 150 of the semiconductor wafer 100 can be electrically connected to the metal lines 454 of the conductive layer 450 to be electrically connected to the lines 412 of the glass substrate 400, and the bumps 160 of the semiconductor wafer 1 can pass through the metal particles 454 of the conductive layer 450. Connected to the pads 414 of the glass substrate 400. At this time, the polymer 452 of the conductive layer 450 may coat the periphery of the thick metal line 15 〇 and the bump 16 半导体 of the semiconductor wafer 1 . A plane 1000 is defined which is substantially parallel to the active surface 114 of the semiconductor substrate 11 , wherein the thick metal lines of the semiconductor wafer 1 and the line 412 of the glass substrate 4 are projected onto the overlapping area of the plane 1 的The extension distance L is, for example, greater than 5 μm, or such as 疋 greater than 800 μm, or such as greater than 12 μm; the thick metal line 150 of the semiconductor wafer 100 and the line 412 of the glass substrate 4 are projected onto the plane 1000. The area of the overlap region is, for example, greater than 3 〇, 〇〇〇 square micron, or, for example, greater than 80,000 square microns, or such as greater than 15 〇, 〇〇〇 square microns. 52 200814211 In the embodiment - referring to FIG. 50A and FIG. 5B, when the inductance element 412 of the glass substrate shed is bonded to the inductance element 15 of the semiconductor wafer 1 through the conductive layer 450, the inductance of the glass substrate 400 The eight, six, (:, 〇, and 6,000 regions of the element 412 are respectively bonded to the a, b, c, d, e, f, and g regions of the inductive element 15 of the semiconductor wafer (10) through the conductive layer 450. 51A, which is a schematic plan view showing the connection area of the two inductive elements 412, 150 of FIG. 5A and FIG. 5 being projected onto a plane, wherein the two inductive elements 150, 412 are projected onto the plane. The extent of the overlap region (the region of the oblique line in FIG. 5U) (the distance that the path 1200 extends from the X point to the y point) is, for example, greater than 5 μm, or such as greater than 800 μm, or such as greater than 12 〇. 〇micron; the area of the overlapping area of the two inductive elements 150, 412 projected onto the plane 1〇〇〇 (the area of the oblique line in FIG. 51A) is, for example, greater than 30,000 square micrometers, or, for example, greater than go, squared Micron, or for example greater than 150, Referring to FIG. 51, in electrical transmission, one of the electronic components ι12 in the semiconductor wafer 1 (such as the electronic component 112a) is adapted to output an electronic signal through the thin film. After the circuit layers 132, 134, 136 pass through the protective layer 140, they are transferred to the thick metal line 150 and the line 412 of the glass substrate 400, and then pass through the protective layer 140 and are transferred to the semiconductor via the thin film wiring layers 136, 134, and 132. At least one of the other electronic components 112 in the wafer 100 (such as the electronic component U2b); at this time, the thick metal line 150 of the semiconductor wafer 100 and the line 412 of the glass substrate 400 can be used for signal transmission in the semiconductor wafer 100. In addition, after transmitting from the electronic component 112a to the thick metal line 150 and the line 412 of the glass substrate 400, the electronic signal can also be transmitted to the glass wall 53 200814211 substrate 400; at this time, the thick metal line 15 of the semiconductor wafer loo The line 412 between the 〇 and the glass substrate can also be used for signal transmission between the semiconductor wafer 1 and the glass substrate 4. The electrical properties of the bump 160 The semiconductor wafer 1 can be transported to transmit the electronic signal to the glass substrate 400 through the bump 1 (9), or the electronic signal transmitted from the glass substrate 400 can be received through the bump 160. As described above, the semiconductor wafer 1 In addition to the lateral transmission of the electronic signal, the thick metal line 150 and the glass substrate 420 can be used as the lateral transmission between the semiconductor wafer 100 and the glass substrate 400. The thick metal line 150 of the semiconductor wafer is Since the conductive layer 450 is connected to the wiring 412 of the glass substrate 400 over a large area, the electrical connection between the semiconductor wafer 1 and the glass substrate 4 can be greatly increased, and the generation of noise can be reduced. In the electrical transmission of the electronic signal, the thick metal line 15 of the semiconductor wafer and the line 412 of the glass substrate 400 are used for signal transmission in the semiconductor wafer 1 'also as a semiconductor wafer 1 ' For signal transmission between the glass substrate and the substrate. However, the application of the present invention is not limited thereto, and the thick metal line 15 of the semiconductor wafer 1 (10) and the line 412 of the glass substrate 400 may also be used only for signal transmission in the semiconductor wafer 1 and not as a semiconductor wafer. For signal transmission between the glass substrate 4 and the glass substrate 400, the line 412 of the glass substrate 400 and the other lines in the glass substrate 4 are electrically disconnected. In other implementations, the glass substrate 400 can also be adapted to output an electronic signal, 54 200814211 to the line 412 of the glass substrate 400 and the thick metal line 150, and then through the protective layer 14 of the semiconductor wafer 100, and through the film. The circuit layers 136, 134, 132 are transferred to at least one electronic component 112 (such as the electronic components 112a and 112b) in the semiconductor wafer 1A. In FIGS. 50 and 51, the thick metal wiring 150 is directly formed on the protective layer 140. However, the 'thick metal line 150 may also be formed on the polymer layer 180 on the protective layer 14' as shown in FIG. 52, which shows a cross section of another wafer structure in accordance with the third embodiment of the present invention. The arrangement in which the position and material of the polymer layer 180 are described in detail in the first embodiment will not be described again. In FIGS. 50 to 52, the thick metal line 150 is connected to the thin film wiring layer 136 of the top layer through the small opening 142 of the protective layer 140; however, the thick metal wiring 15 () may also be transparent to the protective layer 14 The opening 142 is connected to the top film layer 136 over a large area, as shown in Figures 53 and 54, which show a cross-sectional view of another form of the gusset assembly in accordance with a third embodiment of the present invention. In the present embodiment, the connection relationship between the thick metal line 15A of the semiconductor wafer 100 shown in FIGS. 53 and 54 and the thin film line 137 is the same as that of the semiconductor wafer shown in FIGS. 4 to 5 in the first embodiment. The connection relationship between the thick metal line 15〇 and the thin film line 137'. For a more detailed description, reference may be made to the thick metal line 15 () and the 137 line of the semiconductor wafer (10) exemplified in the first embodiment. For the actual operation of the inductor element, if the description of this part is referred to, the connection relationship between the thick metal of the semiconductor chip 100 and the line 15 〇舆 film line 137 in this embodiment will be more clearly understood. Referring to FIG. 53 and FIG. 54, in electrical transmission, one of the electronic components 112 in the semiconductor wafer loo (for example, the electronic component 112a) is adapted to output an electronic signal via the thin film wiring layer 132. After 134, the film 412 can be transferred to the thin film line 137, the thick metal line 150, and the glass substrate 400, and then transferred to the other electronic components in the semiconductor wafer 1 via the thin film wiring layers 134, 132. One of them (for example, electronic component H2b); at this time, the film line 137, the thick metal line 150, and the line 412 of the glass substrate 4 can be used for signal transmission in the semiconductor wafer. In addition, the electronic signal can be transmitted to the glass substrate after being transferred to the thin film line 137, the thick metal line 15 and the line 412 of the glass substrate 400. At this time, the thin film line 137, the thick metal line 150 and the glass substrate 400 are Line 412 can also be used for signal transmission between semiconductor wafer 100 and glass substrate 400. In addition, the glass substrate 400 is also adapted to output an electronic signal, which is transmitted to the circuit 412 of the glass substrate 4 and the thick metal line 15 and the thin film line 137 of the semiconductor wafer 100, and then transmitted to the semiconductor via the thin film wiring layers 134 and 132. At least one electronic component 112 (such as electronic components 112a and 112b) within the wafer 1 . In addition, in terms of electrical transmission of the bump 160, the semiconductor wafer 1 can transmit an electronic signal to the glass substrate 4 through the bump 160, or can receive the glass substrate 400 through the bump 16 Electronic signal. As described above, the thin film line 137 of the semiconductor wafer, the thick metal line 150, and the line 412 of the glass substrate 400 can be used as a lateral transmission between the semiconductor wafer 1 and the substrate 200 in addition to the lateral transmission of the electronic signal. transmission. Since the thick metal line 56 200814211 150 is connected to the thin film line 137 and the glass substrate shed in a large area, at least the area of the electronic signal can be increased, so that the transmission quality of the electronic signal can be improved. 2. The thick metal line of the semiconductor wafer and the circuit of the glass substrate serve as a signal transmission wheel between the semiconductor wafer and the glass substrate. 4 is a cross-sectional view showing another type of wafer structure according to a third embodiment of the present invention, wherein the semiconductor wafers of FIGS. 55 to 58 are respectively identical to those of the second embodiment. The semiconductor wafer of FIG. 5 is just the same, and the glass substrate shed of FIG. 55 to FIG. 10 is similar to the glass substrate side of FIG. 5Q to FIG. 54 and will not be described here; the difference is that the semiconductor wafer is thick. The metal line 15A and the line 412 of the glass substrate 400 serve only for signal transmission between the semiconductor wafer 1 and the glass substrate side, and are not used for signal transmission in the semiconductor wafer, as described below. Referring to FIG. 55 and FIG. 56, in the electrical transmission, one of the electronic components 112 in the semiconductor chip 1 (for example, the electronic component 112a) is adapted to output an electronic signal, and the electronic signal is transmitted through the thin film circuit layer. After passing through the protective layer 14 , the film is transferred to the thick metal line 150 of the semiconductor wafer 1 and the line 4 丨 2 of the glass substrate 4 , and then transferred to the glass substrate 400; The thick metal line 150 of the semiconductor wafer and the line 412 of the glass substrate 400 can be used for signal transmission between the semiconductor wafer 1 and the glass substrate 400. In other implementations, the glass substrate 400 is also adapted to output an electronic signal.
*于月！I 至玻璃基板400之線路412及半導體晶片100之厚金屬線路15〇，接 57 200814211 著再穿過半導體晶片100之保護層140,並經由薄膜線路層136、134、 132傳輸至半導體晶片1〇〇内之至少一電子元件112(比如是電子元件 . 112a)。 請參照圖57及圖58，在電性傳輸上，半導體晶片1〇〇内之電子 元件112的其中一個（比如是電子元件H2a)係適於輸出一電子訊號， 此電子訊號經由薄膜線路層132、134後，傳輸至薄膜線路137、厚金 屬線路150及玻璃基板400之線路412，接著再傳輸至玻璃基板4〇〇 / 内；此時，半導體晶片100之厚金屬線路150與玻璃基板4〇〇之線路 412係可以作為半導體晶片100與玻璃基板400間之訊號傳輸之用。 在其他實施情形中，玻璃基板400亦適於輸出一電子訊號，傳輸 至玻璃基板400之線路412及半導體晶片100之厚金屬線路150及薄 膜線路137 ’接著再經由薄膜線路層134、132傳輸至半導體晶片 内之至少一電子元件112(比如是電子元件112a)。 請參照圖55至圖58，就凸塊160的電性傳輸而言，半導體晶片 〔 100可以透過凸塊160傳送電子訊號至玻璃基板4〇〇，或是可以透過凸 塊160接收由玻璃基板4〇〇所傳來的電子訊號。 如上所述，半導體晶片100之厚金屬線路15〇與玻璃基板4〇〇之 線路412除了可以作為電子訊號的橫向傳輸之外，還可以作為半導體 晶片100與基板2〇〇間的縱向傳輸。由於半導體晶片1〇〇之厚金屬線 路150係透過導電層450大面積地連接玻璃基板4〇〇之線路412，因 此可以大幅地增加半導體晶片1〇〇與玻璃基板4〇〇間電性連接的效 58 200814211 月匕，且可以減少雜訊的產生。 3.半導體g之厚金肠路與_基_線路係料電源匯流排 或接地匯流排之用。 請參照圖59至圖62，其緣示依照本發明第三實施例之另一類型晶 片構裝的剖面示意圖，其中圖59至圖62之半導體晶片⑽係分別雷_曰 第一實施例中圖2至圖5之半導體晶片1〇〇，且圖59至圖從之破=基板 侧係雷同於圖50至圖54之玻璃基板_，在此便不再贅述；惟不同點係 在於半導體晶片1GG之厚金屬線路⑽與玻璃基板之線路412係作為 電源匯流排或接地匯流排之用，如下所述。 請參照® 59至圖62,當半導體晶片1〇〇之厚金屬線路15〇與玻璃基 板棚之線路412係作為電源匯流排時，轉體晶片1〇〇之厚金屬線路15〇 與玻璃絲棚之線路412比如係電性連接至半導體晶片丨⑽内之電源匯 流排135，比如係由薄膜線路層134提供之，並且還電性連接至玻璃基板 柳内的電源匯流排。由於半導體晶片1〇〇之厚金屬線路15〇係透過導 電層450大面積地連接玻璃基板4〇〇之線路412，且電性連接至半導體 晶片100内之電源匯流排135,如此可以減少半導體晶片1〇〇之電源匯流 排135因爲受到訊號干擾而產生電壓變化的程度，並且半導體晶片 可以提供較為穩定之電源電壓。 或者，在其他的實施情況中，半導體晶片1〇〇之厚金屬線路15〇與玻 璃基板400之線路412係電性連接於半導體晶片100之電源匯流排135，但 是卻與玻璃基板400内的線路之間呈現電性斷路。 59 200814211 請參照圖59至圖62,當半導體晶片loo之厚金屬線路15〇與玻璃基 板400之線路412係作為接地匯流排時，半導體晶片ι〇〇之厚金屬線路⑽ 與玻璃基板400之線路412比如係電性連接至半導體晶片1〇〇内之接地匯 流排135，比如係由薄膜線路層134提供之，並且還電性連接至玻璃基板 400内的接地匯流排。由於半導體晶片100之厚金屬線路15〇係透過導 電層450大面積地連接玻璃基板400之線路412，且電性連接至半導體 晶片100内之接地匯流排135,如此可以減少半導體晶片1〇〇之接地匯流 排135因爲受到訊號干擾而產生電壓變化的程度，並且半導體晶片上⑻ 可以提供較為穩定之接地電壓。 或者，在其他的實施情況中，半導體晶片之厚金屬線路與玻 璃基板400之線路412係電性連接於半導體晶片100之接地匯流排135，但 是卻與玻璃基板400内的線路之間呈現電性斷路。 4.半導體晶片之厚金屬線路係作為玻璃基板内之訊號傳輸之 用、或是作為基板之電源匯流排或接地匯流排之用 請參照圖63及圖64，其繪示依照本發明第三實施例之另一類型 晶片構裝的剖面示意圖，其中圖63及圖64之半導體晶片1〇〇係分別 雷同於圖2及圖3之半導體晶片100,且圖63及圖以之玻璃基板4〇() 係雷同於如前所述之玻璃基板400，在此便不再贅述；惟不同點係在 於半導體晶片1GG之厚金屬線路15G係與半導體晶片削内之薄膜線 32 134、136之間呈現電性斷路的狀態，且半導體晶片之 厚金屬線路150與玻璃基板侧之線路412係作為玻璃基板棚内之 200814211 訊號傳輸之用、或是作為玻璃基板400之電源匯流排或接地匯流排之 用，如下所述。 請參照圖63及圖64，當半導體晶片1〇〇之厚金屬線路15〇與玻 璃基板400之線路412係作為玻璃基板400内之訊號傳輸之用時，一 電子訊號適於經由玻璃基板400傳輸至玻璃基板400之線路412與半 導體晶片100之厚金屬線路150，經由玻璃基板4〇〇之線路412與半 導體晶片100之厚金屬線路150的傳輸後，再傳輸至玻璃基板4〇〇之 其他線路，其中此電子訊號並未經由玻璃基板4〇〇之線路412與半導 體晶片100之厚金屬線路150直接傳輸至半導體晶片1〇〇内。如上所 述，半導體晶片100之厚金屬線路15〇與玻璃基板4〇〇之線路412可 以僅作為玻璃基板4〇〇内之電子訊號傳輸之用，而不作為半導體晶片 100内之訊號傳輸之用或是作為半導體晶片刚與玻璃基板棚間之 訊说傳輸之用。由於半導體晶片議之厚金屬線路15()係透過導電層*Yuyue! The line 412 to the glass substrate 400 and the thick metal line 15 of the semiconductor wafer 100 are then passed through the protective layer 140 of the semiconductor wafer 100 and transferred to the semiconductor wafer via the thin film wiring layers 136, 134, 132. At least one electronic component 112 in the crucible (such as an electronic component 112a). Referring to FIG. 57 and FIG. 58, one of the electronic components 112 in the semiconductor wafer 1 (for example, the electronic component H2a) is adapted to output an electronic signal through the thin film circuit layer 132. After 134, the line 412 is transferred to the thin film line 137, the thick metal line 150, and the glass substrate 400, and then transferred to the glass substrate 4?/; at this time, the thick metal line 150 and the glass substrate 4 of the semiconductor wafer 100 The line 412 can be used for signal transmission between the semiconductor wafer 100 and the glass substrate 400. In other implementations, the glass substrate 400 is also adapted to output an electronic signal, and the thick metal line 150 and the thin film line 137 ′ transmitted to the line 412 of the glass substrate 400 and the semiconductor wafer 100 are then transferred to the thin film wiring layers 134 and 132 to At least one electronic component 112 (such as electronic component 112a) within the semiconductor wafer. Referring to FIG. 55 to FIG. 58 , in terms of electrical transmission of the bumps 160 , the semiconductor wafers 100 can transmit electronic signals to the glass substrate 4 through the bumps 160 or can be received by the bumps 160 by the glass substrate 4 . The electronic signal from the 。. As described above, the thick metal line 15 of the semiconductor wafer 100 and the line 412 of the glass substrate 4 can be used as a lateral transmission between the semiconductor wafer 100 and the substrate 2 in addition to the lateral transmission of the electronic signal. Since the thick metal line 150 of the semiconductor wafer is connected to the line 412 of the glass substrate 4 through the conductive layer 450, the electrical connection between the semiconductor wafer 1 and the glass substrate 4 can be greatly increased. Effect 58 200814211 Month, and can reduce the generation of noise. 3. Thickness of the semiconductor g and the _ base _ line system power bus or ground bus. Referring to FIG. 59 to FIG. 62, there is shown a schematic cross-sectional view of another type of wafer assembly according to a third embodiment of the present invention, wherein the semiconductor wafers (10) of FIGS. 59-62 are respectively in the first embodiment. 2 to the semiconductor wafer 1 of FIG. 5, and FIG. 59 to FIG. 59 is broken from the substrate side and is similar to the glass substrate of FIG. 50 to FIG. 54, and will not be described again here; the only difference lies in the semiconductor wafer 1GG. The thick metal line (10) and the glass substrate line 412 are used as a power bus or ground bus, as described below. Referring to FIG. 59 to FIG. 62, when the thick metal line 15〇 of the semiconductor wafer and the line 412 of the glass substrate are used as the power bus, the thick metal line 15〇 and the glass shed of the rotating wafer 1〇〇 The line 412 is, for example, electrically connected to a power bus 135 within the semiconductor wafer cassette (10), such as provided by the thin film circuit layer 134, and is also electrically connected to a power bus bar within the glass substrate. Since the thick metal line 15 of the semiconductor wafer is connected to the wiring 412 of the glass substrate through the conductive layer 450 and electrically connected to the power bus 135 in the semiconductor wafer 100, the semiconductor wafer can be reduced. The power supply bus 135 has a voltage variation due to signal interference, and the semiconductor wafer can provide a relatively stable power supply voltage. Alternatively, in other implementations, the thick metal line 15 of the semiconductor wafer and the line 412 of the glass substrate 400 are electrically connected to the power bus 135 of the semiconductor wafer 100, but with the line within the glass substrate 400. There is an electrical disconnection between them. 59 200814211 Referring to FIG. 59 to FIG. 62, when the thick metal line 15 of the semiconductor wafer loo and the line 412 of the glass substrate 400 are used as the ground bus, the thick metal line (10) of the semiconductor wafer and the line of the glass substrate 400 are used. The 412 is electrically connected to the ground bus bar 135 of the semiconductor wafer 1 , for example, by the thin film circuit layer 134 , and is also electrically connected to the ground bus bar in the glass substrate 400 . Since the thick metal line 15 of the semiconductor wafer 100 is connected to the line 412 of the glass substrate 400 through the conductive layer 450 and electrically connected to the ground bus 135 in the semiconductor wafer 100, the semiconductor wafer can be reduced. The ground bus 135 is subject to voltage variations due to signal interference, and the semiconductor chip (8) can provide a relatively stable ground voltage. Alternatively, in other implementations, the thick metal lines of the semiconductor wafer and the line 412 of the glass substrate 400 are electrically connected to the ground bus bar 135 of the semiconductor wafer 100, but are electrically connected to the lines in the glass substrate 400. Open circuit. 4. The thick metal circuit of the semiconductor wafer is used for signal transmission in the glass substrate or as a power bus or ground bus of the substrate. Please refer to FIG. 63 and FIG. 64, which illustrate a third embodiment according to the present invention. A cross-sectional view of another type of wafer structure, wherein the semiconductor wafers of FIGS. 63 and 64 are identical to the semiconductor wafer 100 of FIGS. 2 and 3, respectively, and the glass substrate 4 of FIG. 63 and FIG. The same is true for the glass substrate 400 as described above, and will not be described again here; the only difference is that the thick metal line 15G of the semiconductor wafer 1GG is electrically connected to the thin film lines 32 134, 136 of the semiconductor wafer. The state of the open circuit, and the thick metal line 150 of the semiconductor wafer and the line 412 on the glass substrate side are used for the transmission of the 200814211 signal in the glass substrate, or as the power bus or the ground bus of the glass substrate 400, As described below. Referring to FIG. 63 and FIG. 64, when the thick metal line 15 of the semiconductor wafer 1 and the line 412 of the glass substrate 400 are used for signal transmission in the glass substrate 400, an electronic signal is suitable for transmission via the glass substrate 400. The line 412 to the glass substrate 400 and the thick metal line 150 of the semiconductor wafer 100 are transferred to the thick metal line 150 of the semiconductor wafer 100 via the line 412 of the glass substrate 4, and then transferred to other lines of the glass substrate 4 The electronic signal is not directly transmitted to the semiconductor wafer 1 via the thick metal line 150 of the semiconductor wafer 100 via the line 412 of the glass substrate 4 . As described above, the thick metal line 15 of the semiconductor wafer 100 and the line 412 of the glass substrate 4 can be used only for the electronic signal transmission in the glass substrate 4, and not as the signal transmission in the semiconductor wafer 100 or It is used as a communication between the semiconductor wafer and the glass substrate shed. Because the thick metal line 15 () of the semiconductor wafer is transmitted through the conductive layer
450大面積地連接玻璃基板侧之線路412，因此可以增加此電子訊號 的電性傳輸品質。 喷參照圖63及圖64，當半導體晶片1〇〇之厚金屬線路150與玻 璃基板400之線路412係作為破璃基板棚之電源匯流排時，半導體 曰曰片1〇0之厚金屬線路150肖破璃基板棚之線路412係適於電性連 内之電源匯流排’其中半導體晶片議之厚金屬線路 150係與半導體晶片⑽内之電源匯流排之間呈現電性斷路。由於 日日 之厚金屬線路15〇係透過導電層450大面積地連接玻璃 200814211 基板400之線路412，且電性連接至玻璃基板400内之電源匯流排， 如此可以減少玻璃基板400之電源匯流排因爲受到訊號干擾而產生電 壓變化的程度，並且玻璃基板400可以提供較為穩定之電源電壓。 請參照圖63及圖64，當半導體晶片1〇〇之厚金屬線路150與玻 璃基板400之線路412係作為玻璃基板400之接地匯流排時，半導體 晶片100之厚金屬線路150與玻璃基板400之線路412係適於電性連 接玻璃基板400内之接地匯流排，其中半導體晶片1〇〇之厚金屬線路 150係與半導體晶片1〇〇内之接地匯流排之間呈現電性斷路。由於半 導體晶片100之厚金屬線路150係透過導電層450大面積地連接玻璃 基板400之線路412，且電性連接至玻璃基板4〇〇内之接地匯流排， 如此可以減少玻璃基板400之接地匯流排因爲受到訊號干擾而產生電 壓變化的程度，並且玻璃基板400可以提供較為穩定之接地電壓。 四、結論 綜上所述，本發明之晶片構裝及其製程，由於半導體晶片之厚金 屬線路可以是直接魏地大面舰接電路連接猶之線路，或是透過 含有聚合物及金屬粒子的導電層大面積地連接電路連接構件之線路， 藉以降低半導體晶片之厚金屬線路與電路連接構件之線路間的電阻。 若是大面積電性連接之半導體晶片之厚金屬線路與電路接構件之線 路係作為職傳輸之科，辭導體晶片之厚金躲路與電路連接構 件之線路可以提供較敎的訊號傳輸；奸大面積電性連接之半導體 晶片之厚金屬線路與電路連接構件之線路係作為電源匯流排或接地匯 62 200814211 抓排之用日守’則半導體晶片之厚金屬、線路及/或電路連接構件之線路可 以提供較穩定的電源電壓或接地電壓。 雖然本發明已以多錄佳實關揭露如上，然其並非用以限定本 發明，任何熟習此技藝者，在不脫離本發日月之精神和範_，當可作 些許之更動與潤飾，因此本發明之保護範圍當視後附之中請專利範圍 所界定者為準。 【圖式簡單說明】 圖1緣摊照本發明第-實施例之晶片構裝在組裝前半導體晶片及基 板的剖面示意圖。 圖1A係為圖1中基板200之線路212投影至平面刪上的平面 示意圖。 圖1B係為圖1十半導體晶片100之厚金屬線路150投影至平面 1000上的平面示意圖。 圖2至圖5分別緣示本發明第一實施例之半導體晶片與基板接合後之 曰曰片構裝的拍不意圖’其中半導體晶片之厚金屬線路與基板的線路係作 為半導體晶片内之訊號傳輸之用。 圖2A’其綠不圖1A及圖1B之二電感元件212、150接合後之連 接區域投影鮮面麵上的平面示意圖。 圖5A繪不圖4及圖5中厚金屬線路與薄膜線路連接之區域投影至 平面1000上的剖面示意圖。 圖至圖9刀別緣不依照本發明第一實施例之另_類型晶片構裝的剖 63 200814211 。圖’、巾轉體晶片之厚金屬線路與基板的線路健為半導體晶片 與基板間之訊號傳輪之用。 圖10至圖13分別繪示依照本發明第_實施例之另一類型晶片構裝的 J面丁Μ圖其中半導體晶片之厚金屬線路與基板的線路係作為電源匯流 排或接地匯流排之用。 圖Η及圖15分別繪示依照本發明第一實施例之另一類型晶片構裝的 抽不思圖’其巾半導體晶片之厚金屬線路係作為絲狀訊號傳輸之 用或疋作為基板之電源匯流排或接地匯流排之用。 圖16及圖17分別緣示在本發明第一實施例中半導體晶片之厚金屬線 路之其中-種金屬層堆積結構的剖面示意圖。 圖18至圖20分別緣不在本發明第—實施例中基板之線路之其中一種 金屬層堆積結構的剖面示意圖。 圖21緣示依照本發明第二實施例之晶片構裝在組裝前二半導體晶片 的剖面示意圖。 圖22至圖27分別繪示本發明第實二施例之半導體晶片與基板接合後 之晶片構裝的剖面示意圖，其中二半導體晶片之相互連接的二厚金屬線路 係作為半導體晶片内之訊號傳輸之用。 圖28至圖33分別繪示依照本發明第二實施例之另一類型晶片構裝的 剖面示意圖，其中二半導體晶片之相互連接的二厚金屬線路係作為二半導 體晶片間之訊號傳輸之用。 圖34至圖39分別繪示依照本發明第二實施例之另一類型晶片構裝的 64 200814211 係作為電源匯 剖面示意圖’其中二半導體晶片之相互連接的二厚金屬線路 流排或接地匯流排之用。 圖40至圖43分別緣示依照本發明第二實施例之另—麵 剖面示意圖，其中二半導_之相互連接的二厚金屬線路係H的 半導體晶片内之訊號傳輸之用。 ' 圖44至圖47分別緣示依照本發明第二實施例之另—類型晶片構裝的 剖面不意圖’其中二半導體晶片之相互連接的二厚金屬線路係作為其中一 半導體晶片之電源匯流排或接地匯流排之用。 片300之厚金 圖48及圖49分別!會示在本發明第三實施例中半導體晶 屬線路350之其中-種金屬層堆積結構的剖面示意圖。 圖50緣示依照本發明第三實施例之晶片構裝在組裝前之半導體晶片 與玻璃基板的剖面示意圖。 圖51至圖54分別繪示本發明第三實施例之半導體晶片與基板接合後 之晶片構震的剖面示意圖，其中半導體晶片之厚金屬線路與玻璃基板的線 路係作為半導體晶片内之訊號傳輸之用。 圖50A係為圖50中玻璃基板400之線路412投影至平面1〇5〇上 的平面示意圖。 圖5〇β係為圖50中半導體晶片100之厚金屬線路150投影至平面 1000上的平面示意圖。 圖51A緣示圖50Α及圖5〇Β之二電感元件412、15〇接合後之連接 區域㈣至平面1咖上的平面示意圖。 65 200814211 圖55至圖58繪示依照本發明第三實施例之另一類型晶片構奢的剖面 半導體晶 示意圖，其中半導體晶片之厚金屬線路與玻璃基板的線路係作為 片與玻璃基板間之訊號傳輸之用。 圖59至圖62繪示依照本發明第三實施例之另一類型晶片構裝的剖面 示意圖，其中半導體晶片之厚金屬線路與玻璃基板的線路係作為電源匯流 排或接地匯流排之用。 圖63及圖64繪示依照本發明第三實施例之另一類型晶片構裴的剖面 示意圖，其中半導體晶片之厚金屬線路係作為玻璃基板内之訊號傳輸之 用、或是作為基板之電源匯流排或接地匯流排之用。 【主要元件符號說明】 100 :半導體晶片 110 :半導體基底 112、112a、112b :電子元件 114 :主動表面 12卜123、125 :導通孔 122、124、126 :薄膜介電層 132、134、136 :薄膜線路層 135 :電源匯流排或接地匯流排 137 :薄膜線路 140 :保護層 142 :保護層之開口 66 200814211 150 :厚金屬線路 160 :凸塊 170 :聚合物層 180 :聚合物層 182 :聚合物層之開口 200 :基板 210 :線路層 212 :線路 214 :接墊 220 :焊罩層 300 :半導體晶片 310 :半導體基底 312、312a、312b :電子元件 314 ··主動表面 32卜323、325 :導通孔 322、324、326 :薄膜介電層 332、334、336 :薄膜線路層 335 :電源匯流排或接地匯流排 337 :薄膜線路 340 :保護層 342 :保護層之開口 67 200814211 350 :厚金屬線路 360 :接墊 380 :聚合物層 382 :聚合物層之開口 400 :玻璃基板 410 :線路層 412 :線路 414 :接墊 450 :導電層 452 :聚合物 454 :金屬粒子 1000、1050 :表面 1100、1200 :路徑 68450 is connected to the line 412 on the glass substrate side over a large area, so that the electrical transmission quality of the electronic signal can be increased. Referring to FIGS. 63 and 64, when the thick metal line 150 of the semiconductor wafer 1 and the line 412 of the glass substrate 400 are used as the power busbar of the glass substrate, the thick metal line 150 of the semiconductor wafer 1〇0. The circuit 412 of the Xiao-glass substrate shed is suitable for the power busbar of the electrical connection. The thick metal line 150 of the semiconductor wafer and the power bus of the semiconductor wafer (10) are electrically disconnected. Since the thick metal line 15 is connected to the line 412 of the glass 200814211 substrate 400 through the conductive layer 450 and electrically connected to the power bus bar in the glass substrate 400, the power bus of the glass substrate 400 can be reduced. The degree of voltage change is caused by signal interference, and the glass substrate 400 can provide a relatively stable power supply voltage. Referring to FIG. 63 and FIG. 64, when the thick metal line 150 of the semiconductor wafer 1 and the line 412 of the glass substrate 400 are used as the ground bus bar of the glass substrate 400, the thick metal line 150 and the glass substrate 400 of the semiconductor wafer 100 are used. The line 412 is adapted to be electrically connected to the ground bus bar in the glass substrate 400, wherein the thick metal line 150 of the semiconductor wafer 1 and the ground bus bar in the semiconductor wafer 1 are electrically disconnected. Since the thick metal line 150 of the semiconductor wafer 100 is connected to the line 412 of the glass substrate 400 through the conductive layer 450 and electrically connected to the ground bus bar in the glass substrate 4, the ground connection of the glass substrate 400 can be reduced. The row is subjected to a voltage change due to signal interference, and the glass substrate 400 can provide a relatively stable ground voltage. IV. Conclusion In summary, the wafer assembly and the process of the present invention, because the thick metal lines of the semiconductor wafer can be connected directly to the Wei-Dai surface connection circuit, or through the polymer and metal particles. The conductive layer connects the lines of the circuit connecting members over a large area to reduce the resistance between the thick metal lines of the semiconductor wafer and the lines of the circuit connecting members. If the circuit of the thick metal circuit and the circuit connecting component of the semiconductor chip of the large-area electrical connection is used as the service transmission section, the circuit of the thick gold escaping circuit and the circuit connecting component of the conductor chip can provide a relatively short signal transmission; The circuit of the thick metal line and the circuit connecting member of the semiconductor chip electrically connected to the area is used as a power bus or grounding junction 62. The use of the thick metal, line and/or circuit connecting member of the semiconductor chip A stable supply voltage or ground voltage can be provided. Although the present invention has been disclosed above in detail, it is not intended to limit the present invention, and any person skilled in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of protection of the present invention is defined by the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a semiconductor wafer and a substrate before assembly in accordance with a wafer of a first embodiment of the present invention. 1A is a plan view showing the line 212 of the substrate 200 of FIG. 1 projected onto a plane. Figure 1B is a schematic plan view showing the thick metal line 150 of the semiconductor wafer 100 of Figure 10 projected onto a plane 1000. FIG. 2 to FIG. 5 respectively illustrate the splicing of the semiconductor wafer after bonding the semiconductor wafer and the substrate according to the first embodiment of the present invention, wherein the thick metal wiring of the semiconductor wafer and the substrate are used as signals in the semiconductor wafer. For transmission. Fig. 2A' is a schematic plan view showing the fresh surface of the connecting region after the joining of the inductive elements 212, 150 of Fig. 1A and Fig. 1B. 5A is a cross-sectional view showing the area where the thick metal line and the thin film line are connected to the plane 1000, which is not shown in FIG. 4 and FIG. Fig. 9 is a cross-sectional view of a wafer assembly of another type according to the first embodiment of the present invention. The thick metal lines of the wafer and the substrate are used for the signal transmission between the semiconductor wafer and the substrate. 10 to FIG. 13 respectively illustrate a J-side diagram of another type of wafer structure according to the embodiment of the present invention, wherein the thick metal line of the semiconductor wafer and the circuit of the substrate are used as a power bus or ground bus. . Figure 15 and Figure 15 respectively illustrate another type of wafer assembly in accordance with a first embodiment of the present invention. The thick metal line of the wafer semiconductor wafer is used as a power source for the transmission of the filament signal or as a substrate. Used for bus or ground bus. 16 and 17 are schematic cross-sectional views showing a metal layer stacking structure of a thick metal line of a semiconductor wafer in the first embodiment of the present invention. 18 to 20 are schematic cross-sectional views showing a metal layer stacking structure which is not one of the lines of the substrate in the first embodiment of the present invention. Figure 21 is a cross-sectional view showing the wafer structure of the second semiconductor wafer before assembly according to the second embodiment of the present invention. 22 to FIG. 27 are schematic cross-sectional views showing the wafer structure after bonding the semiconductor wafer and the substrate of the second embodiment of the present invention, wherein the two thick metal lines of the two semiconductor wafers are used as signal transmission in the semiconductor wafer. Use. 28 to 33 are schematic cross-sectional views showing another type of wafer structure in accordance with a second embodiment of the present invention, wherein two interconnected two thick metal lines of the semiconductor wafer are used for signal transmission between the two semiconductor wafers. FIG. 34 to FIG. 39 respectively illustrate a second embodiment of a wafer assembly in accordance with a second embodiment of the present invention. The 200814211 is used as a schematic diagram of a power supply junction. Two of the semiconductor wafers are connected to each other by a thick metal line flow line or a ground bus. Use. 40 to 43 are schematic cross-sectional views showing another embodiment of the present invention, in which the two semiconductors are connected to each other in a semiconductor wafer of a two-thick metal wiring line H for signal transmission. 44 to 47 respectively illustrate a cross-section of another type of wafer structure according to a second embodiment of the present invention, which is not intended to be a two-thick metal circuit in which two semiconductor wafers are connected as a power bus of one of the semiconductor wafers. Or ground busbars. The thick gold of the sheet 300 Fig. 48 and Fig. 49 respectively show a cross-sectional view of a metal layer stacking structure of the semiconductor crystal line 350 in the third embodiment of the present invention. Figure 50 is a cross-sectional view showing a semiconductor wafer and a glass substrate before assembly of a wafer according to a third embodiment of the present invention. 51 to FIG. 54 are schematic cross-sectional views showing the structure of the wafer after bonding of the semiconductor wafer and the substrate according to the third embodiment of the present invention, wherein the thick metal lines of the semiconductor wafer and the circuit of the glass substrate are used as signal transmission in the semiconductor wafer. use. Figure 50A is a schematic plan view showing the line 412 of the glass substrate 400 of Figure 50 projected onto a plane 1〇5〇. 5 is a schematic plan view showing the thick metal line 150 of the semiconductor wafer 100 of FIG. 50 projected onto the plane 1000. Fig. 51A is a plan view showing the connection region (4) to the plane 1 after the bonding of the inductive elements 412 and 15 of Fig. 50A and Fig. 5B. 65 200814211 FIG. 55 to FIG. 58 are schematic diagrams showing a cross-sectional semiconductor crystal of another type of wafer structure according to a third embodiment of the present invention, wherein the thick metal line of the semiconductor wafer and the circuit of the glass substrate serve as signals between the sheet and the glass substrate. For transmission. 59 to 62 are schematic cross-sectional views showing another type of wafer structure in accordance with a third embodiment of the present invention, in which the thick metal lines of the semiconductor wafer and the circuit of the glass substrate are used as a power bus or ground bus. 63 and FIG. 64 are schematic cross-sectional views showing another type of wafer structure according to a third embodiment of the present invention, wherein the thick metal line of the semiconductor wafer is used for signal transmission in the glass substrate or as a power supply sink of the substrate. Used for row or ground bus. [Main component symbol description] 100: semiconductor wafer 110: semiconductor substrate 112, 112a, 112b: electronic component 114: active surface 12 123, 125: via holes 122, 124, 126: thin film dielectric layers 132, 134, 136: Film line layer 135: power bus bar or ground bus bar 137: film line 140: protective layer 142: opening of protective layer 66 200814211 150: thick metal line 160: bump 170: polymer layer 180: polymer layer 182: polymerization The opening of the object layer 200: substrate 210: circuit layer 212: line 214: pad 220: solder mask layer 300: semiconductor wafer 310: semiconductor substrate 312, 312a, 312b: electronic component 314 · active surface 32 323, 325: Via 322, 324, 326: thin film dielectric layer 332, 334, 336: thin film wiring layer 335: power bus or ground bus 337: thin film wiring 340: protective layer 342: opening of protective layer 67 200814211 350: thick metal Line 360: pad 380: polymer layer 382: polymer layer opening 400: glass substrate 410: circuit layer 412: line 414: pad 450: conductive layer 452: polymer 454: metal particles 1000, 1050: surface 1100 1200: Diameter 68