TWI395191B - Lcd devices and driving methods thereof - Google Patents

Description

Liquid crystal display device and driving method thereof

The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly to a liquid crystal display device and a driving method thereof for controlling charge sharing according to a Most Significant Bit (MSB) of a data signal.

Liquid crystal display has been widely used in notebook computers and personal digital assistants because it has the advantages of low radiation, small size and low energy consumption. It has gradually replaced the traditional cathode ray tube display. (personal digital assistant, PDA), flat-screen TV, or mobile phone and other information products.

Please refer to FIG. 1 , which is a schematic diagram of a liquid crystal display 10 in the prior art. The liquid crystal display 10 includes a liquid crystal display panel 12, a timing controller 14, a source driver 16, and a gate driver 18. The liquid crystal display panel 12 is provided with a plurality of parallel data lines D ₁ -D _m , a plurality of parallel gate lines G ₁ -G _n , and a plurality of display units P ₁₁ - P _mn . The data lines D ₁ -D _m and the gate lines G ₁ -G _n are alternately arranged with each other, and the display units P ₁₁ -P _mn are respectively disposed at the intersection of the corresponding data lines and the gate lines. The timing controller 14 is used to generate control signals and clock signals required to drive the liquid crystal display panel 12. The source driver 16 and the gate driver 18 respectively generate corresponding data signals and gate signals according to the signals transmitted from the timing controller 14. Each display unit on the liquid crystal display panel 12 includes a thin film transistor (TFT) switch and a liquid crystal capacitor, and one end of each liquid crystal capacitor is coupled to a corresponding one through a corresponding thin film transistor switch. The data line is coupled to a common voltage V _com . When the gate transistor signal generated by the gate driver 18 is received to turn on the thin film transistor switch of the display unit, the liquid crystal capacitor of the display unit is electrically connected to the corresponding data line to receive the slave source driver 16 The information signal is transmitted, so the display unit can control the rotation degree of the liquid crystal molecules according to the charge of the liquid crystal capacitor memory to display images of different gray levels.

As the demand for large-sized applications continues to increase, the panel size of liquid crystal displays continues to increase, the load on the panels increases accordingly, and the dynamic power consumption is also greatly increased. How to reduce power consumption has become an important issue in designing liquid crystal displays. In general, the polarity of the voltage applied across the liquid crystal capacitor must be reversed every predetermined time to avoid permanent polarization of the liquid crystal material. The common method of driving the liquid crystal display panel includes dot inversion. (dot inversion) and line inversion (line inversion) and so on. When the polarity of the voltage driving the liquid crystal display panel starts to reverse, the current consumption of the source driver is the largest, so this is also the time when the liquid crystal display is loaded the most.

Therefore, some liquid crystal displays use charge sharing to reduce power consumption, and redistribute the charge before the source driver outputs the data signal, thereby saving the consumed dynamic current by half. In the liquid crystal display 10 of the prior art, the source driver 160 includes a plurality of output buffers OB and a plurality of charge sharing switches CS, and the source driver 16 can transmit the data signals to the corresponding data lines through the output buffer OB. A charge sharing switch CS is coupled between two adjacent data lines to achieve charge sharing by turning on the charge sharing switch CS. In the liquid crystal display 10 of the prior art, regardless of the potential level of the input data signal, charge sharing is performed between the odd data lines and the even data lines in each writing period, and the source driver 16 may perform unnecessary. The charge sharing, on the contrary, increases power consumption.

The present invention provides a liquid crystal display device for controlling charge sharing according to a maximum effective bit of a data signal, comprising a first data line for receiving a first output data signal; and a second adjacent to the first data line The data line is configured to receive a second output data signal; and a source driving circuit coupled to the first and second data lines. The source driving circuit includes a first driving module for generating a corresponding first output data signal according to a first input data signal, and the first driving module includes a first shift register. For receiving a start signal and a clock signal, and generating a first clock control signal according to the start signal and the clock signal; a first sample holder coupled to the first shift register, Receiving the first input data signal, and latching the first input data signal according to the first clock control signal to generate a corresponding one of the first sample data signals; and a first output switch for using a switch Controlling the signal to transmit the first output data signal to the first data line, the first output switch includes a control end for receiving the switch control signal; an input coupled to the first sample holder; An output terminal is coupled to the first data line; a second driving module is configured to generate a corresponding one of the second output data signals according to a second input data signal, where the second driving module includes a first Two shift a buffer for receiving the start signal and the clock signal, and generating a second clock control signal according to the start signal and the clock signal; and a second sample holder coupled to the second shift a bit buffer for receiving the second input data signal, and latching the second input data signal according to the second clock control signal to generate a corresponding one of the second sample data signals; a second output switch, The second output switch includes: a control end for receiving the switch control signal; and an input end coupled to the first control circuit for transmitting the second output data signal to the second data line And an output terminal coupled to the second data line; a switch control circuit coupled to the first and second sample holders for sensing the first and second sampled data signals The maximum effective bit generates the switch control signal; and a charge sharing switch coupled between the output end of the first output switch and the output end of the second output switch, and the first connection is electrically connected according to the switch control signal The output terminal of the switch and the output terminal of the second output of the switch, or an output terminal is electrically isolated from the first output switch and the output terminal of the second output of the switch.

The present invention further provides a liquid crystal display device for controlling charge sharing according to a maximum effective bit of a data signal, comprising a data line for receiving an output data signal, and a source driving circuit coupled to the data line, including a driving module for generating a corresponding output data signal according to an input data signal, the source driving circuit comprising a shift register for receiving a start signal and a clock signal, and The start signal and the clock signal generate a clock control signal; a sample holder coupled to the shift register for receiving the input data signal, and latching the input data signal according to the clock control signal Generating a corresponding sampling data signal; an output switch for transmitting the output data signal to the data line according to a switch control signal, the output switch comprising a control end for receiving the switch control signal; and an input end And coupled to the sample holder; and an output coupled to the data line; a switch control circuit coupled to the sample holder for The most significant bit of the sampled data signal generates the switch control signal; a first power source for providing a high potential operating voltage; a second power source for providing a low potential operating voltage; and a third power source for Providing a common voltage; and a charge sharing switch for electrically connecting the output end of the output switch to the first power source, the second power source or the third power source according to the switch control signal.

The present invention further provides a source driving circuit for controlling charge sharing according to a maximum effective bit of a data signal, comprising a first driving module for generating a corresponding one of the first output data signals according to a first input data signal To drive a first load, the first driving module includes a first shift register for receiving a start signal and a clock signal, and generating a first time according to the start signal and the clock signal a first sample holder, coupled to the first shift register for receiving the first input data signal, and latching the first input data signal according to the first clock control signal Generating a corresponding first sampling data signal; a first output switch for transmitting the first output data signal to the first load according to a switch control signal, the first output switch comprising a control end for receiving The switch control signal; an input coupled to the first sample holder; and an output coupled to the first load; and a second drive module for using a second input data Generating a corresponding second output data signal to drive a second load, the second driving module includes a second shift register for receiving the start signal and the clock signal, and The first signal and the clock signal generate a second clock control signal; a second sample holder coupled to the second shift register for receiving the second input data signal, and according to the second time The pulse control signal latches the second input data signal to generate a corresponding one of the second sample data signals; and a second output switch is configured to transmit the second output data signal to the second load according to the switch control signal, The second output switch includes a control terminal for receiving the switch control signal; an input terminal coupled to the second sample holder; and an output terminal coupled to the second load; a switch control circuit coupled And the first and second sample holders are configured to generate the switch control signal according to the most significant bits of the first and second sampled data signals; and a charge sharing switch coupled to the output of the first output switch And the output end of the second output switch is configured to electrically connect the output end of the first output switch and the output end of the second output switch according to the switch control signal, or electrically separate the first output switch The output end and the output end of the second output switch.

The present invention further provides a source driving circuit for controlling charge sharing according to a maximum effective bit of a data signal, comprising a driving module for generating a corresponding one of the output data signals according to an input data signal to drive a load, The driving module includes a shift register for receiving a start signal and a clock signal, and generating a clock control signal according to the start signal and the clock signal; a sample holder coupled to the shift a bit buffer for receiving the input data signal, and latching the input data signal according to the clock control signal to generate a corresponding sample data signal; and an output switch for transmitting the signal according to a switch control signal Outputting a data signal to the data line, the output switch includes a control end for receiving the switch control signal; an input end coupled to the sample holder; and an output end coupled to the data line; a switch a control circuit coupled to the sample holder for generating the switch control signal according to a maximum effective bit of the sampled data signal; Providing a high potential operating voltage; a second power supply for providing a low potential operating voltage; a third power supply for providing a common voltage; and a charge sharing switch for outputting the output switch according to the switch control signal The output end is electrically connected to the first power source, the second power source or the third power source.

The present invention further provides a method for driving a liquid crystal display device according to a maximum effective bit of a data signal, comprising: providing a start signal, a first input data signal, and a second input data signal; providing according to the first input data signal Corresponding to one of the first output data signals; providing a corresponding one of the second output data signals according to the second input data signal; latching the first and second input data signals according to the start signal to respectively generate corresponding signals a first sampling data signal and a second sampling data signal; generating a switch control signal according to the most significant bit of the first and second sampled data signals; and a first output switch controlling the first according to the switch control signal Outputting a data signal to a signal transmission path of a first data line on a liquid crystal display device; and a second output switch controlling the signal of the second output data signal to a second data line of the liquid crystal display device according to the switch control signal a transmission path; and a charge sharing switch electrically connecting the first output switch according to the switch control signal The second end and the output end of the output switch or output terminal is electrically isolated from the first output switch and the output terminal of the second output of the switch.

The present invention further provides a method for driving a liquid crystal display device according to a maximum effective bit of a data signal, comprising: providing a start signal and an input data signal; providing a high potential operating voltage, a low potential operating voltage, and a common voltage Providing a corresponding one of the output data signals according to the input data signal; latching the input data signal according to the start signal to generate a corresponding one of the sampled data signals; generating a switch control according to the most significant bit of the sampled data signal An output switch controls the output data signal to a signal transmission path of a data line on the liquid crystal display device according to the switch control signal; and a charge sharing switch electrically connects the output end of the output switch according to the switch control signal To the high potential operating voltage, the low potential operating voltage or the common voltage.

Please refer to FIG. 2, which is a schematic diagram of a liquid crystal display 20 in the present invention. The liquid crystal display 20 includes a liquid crystal display panel 22, a timing controller 24, a source driver 26, and a gate driver 28. The liquid crystal display panel 22 is provided with a plurality of mutually parallel data lines D ₁ -D _m , a plurality of mutually parallel gate lines G ₁ -G _n , and a plurality of display units P ₁₁ -P _mn . The data lines D ₁ -D _m and the gate lines G ₁ -G _n are alternately arranged with each other, and the display units P ₁₁ -P _mn are respectively disposed at the intersection of the corresponding data lines and the gate lines. The timing controller 24 is used to generate control signals and clock signals required to drive the liquid crystal display panel 22. The source driver 26 and the gate driver 28 respectively generate corresponding gate signals and data signals according to the signals transmitted from the timing controller 24. Each of the display units on the liquid crystal display panel 22 includes a thin film transistor switch and a liquid crystal capacitor. One end of each liquid crystal capacitor is coupled to a corresponding data line through a corresponding thin film transistor switch, and the other end is connected to the other end. Then coupled to a common voltage V _com . When the gate transistor signal generated by the gate driver 28 is received to turn on the thin film transistor switch of the display unit, the liquid crystal capacitor of the display unit is electrically connected to the corresponding data line to receive the slave source driver 26 The information signal is transmitted, so the display unit can control the rotation degree of the liquid crystal molecules according to the charge of the liquid crystal capacitor memory to display images of different gray levels.

The source driver 26 of the present invention includes a first driving module 100, a second driving module 200, and a switch control circuit 300. The switch control circuit 300 generates a corresponding switch control signal SW _according to the input data signals D _{IN_O} and D _{IN_E} from the timing controller 24 . The first driving module 100 can generate an output data signal D _{OUT_O} required to drive an odd number of data lines according to the input data signal D _{IN_O} and the switch control signal SW, and the second driving module 200 can be based on the input data signal D _{IN_E} and the switch. The control signal SW generates an output data signal D _{OUT_E} required to drive an even number of data lines.

Please refer to FIG. 3, which is a functional block diagram of the source driver 26 in the first embodiment of the present invention. In this embodiment, the source driver 26 includes a first driving module 100, a second driving module 200, a switch control circuit 300, and a charge sharing switch 90. The first driving module 100 includes a shift register 31, a sample hold (Sample & Hold) 41, a level shifter (Level Shifter) 51, and a digital analog converter (Digital- To-Analog Converter (DAC) 61, an operational amplifier (Aperture Amplifier) 71, and an output switch 81. The second driving module 200 includes a shift register 32, a sample holder 42, a one-bit shifter 52, a digital analog converter 62, an operational amplifier 72, and an output switch 82. The source driver 26 drives the odd-numbered and even-numbered data lines through the output switches 81 and 82, respectively, and the charge-sharing switch circuit 90 is coupled to the odd-numbered and even-numbered data lines. The input of the switch control circuit 300 is coupled to the sample holders 41 and 42, and the output is coupled to the output switches 81, 82 and the charge sharing switch 90.

The shift register 31 of the first driving module 100 can generate a corresponding clock control signal S _{CLK — O} according to the clock signal SCLK and the start signal SP generated by the timing controller. The sample holder 41 is coupled to the shift register 31, and can sample the input data signal D _{IN_O} according to the clock control signal S _{CLK — O} , and generate a corresponding sample data signal D _{SH — O} . The level shifter 51 is coupled to the sample holder 41 to adjust the voltage level of the sampled data signal D _{SH_O} . The digital analog converter 61 is coupled to the level shifter 51 to convert the sampled data signal D _{SH_O} into an analog data signal D _{Analog_O} . The operational amplifier 71 is coupled to the digital analog converter 61 to amplify the analog data signal D _{Analog_O} and generate a corresponding output data signal D _{OUT — O} . The output switch 81 is coupled to the operational amplifier 71 and the switch control circuit 300 and can be operated according to the switch control signal SW. When the switch control signal SW is turned on (short-circuited) the output switch 81, the first drive module 100 can output the data signal D. _{OUT_O is} transferred to an odd number of data lines.

Similarly, the shift register 32 of the second driving module 200 can generate a corresponding clock control signal S _{CLK_E} according to the clock signal SCLK and the start signal SP generated by the timing controller. The sample holder 42 can sample the input data signal D _{IN_E} according to the clock control signal S _{CLK_E} and generate a corresponding sample data signal D _{SH_E} . The level shifter 52 is coupled to the sample holder 42 to adjust the voltage level of the sampled data signal D _{SH_E} . The digital analog converter 62 is coupled to the level shifter 52 to convert the sampled data signal D _{SH_E} into an analog data signal D _{Analog_E} . The operational amplifier 72 is coupled to the digital analog converter 62 to amplify the analog data signal D _{Analog_E} and generate a corresponding output data signal D _{OUT_E} . The output switch 82 is coupled to the operational amplifier 72 and the switch control circuit 300 and can be operated according to the switch control signal SW. When the switch control signal SW is turned on (short-circuited) the output switch 82, the second drive module 200 can output the data signal D. _{OUT_E is} transferred to an even number of data lines.

After receiving the sampled data signal D _{SH_O} and the sampled data signal D _{SH_E} , the switch control circuit 300 generates a corresponding signal according to the sampled data signal D _{SH_O} and the most significant bit (MSB) of the sampled data signal D _{SH_E} . The switch controls the signal SW. Please refer to FIG. 4, which is a functional block diagram of the switch control circuit 300 according to an embodiment of the present invention. In this embodiment, the switch control circuit 300 includes MSB latches 281 and 282, D-type Flip-Flops 291 and 292, an OR gate 270, and a shift temporary The memory 30. The MSB latches 281 and 282 are respectively coupled to the output ends of the sample holders 41 and 42, and the maximum effective bit MSB_o of the sampled data signal D _{SH_O and} the most significant bit MSB_e of the sampled data signal D _{SH_E} can be respectively determined. The D-type flip-flops 291 and 292 are negative-triggered flip-flops, the trigger terminals CLK are respectively coupled to the MSB latches 281 and 282, the output terminal Q is coupled to the OR gate 270, and the reset terminal RST is receivable. Reset signal STB. When MSB_o changes from "1" to "0", the output terminal Q of the D-type flip-flop 291 outputs a signal "1"; when the MSB_e changes from "1" to "0", the D-type flip-flop 292 The output terminal Q will output the signal "1". The level shifter 30 is coupled to the OR gate 270 to adjust the voltage level of the control signal SW. When one of MSB_o or MSB_e changes from "1" to "0", the control signal SW output from gate 270 turns off the output switch and turns on the charge sharing switch. At this time, source driver 26 turns off the output and resets. When the STB has a high potential, the charge sharing is performed; when one of the MSB_o or MSB_e changes from "0" to "1", the control signal SW outputted by the gate 270 turns off the output switch and turns off the charge sharing switch. The pole driver 26 turns off the output but does not perform charge sharing.

Please refer to FIG. 5. FIG. 5 is a timing chart of the source driver 26 in the first embodiment of the present invention during charge sharing. In Fig. 5, W _STB represents the waveform of the reset signal STB, W _MSB represents the waveform of the most significant bit MSB_o or the most significant bit MSB_e, and D _{IN_O} and D _{IN_E} represent the waveforms of the odd and even pen input data signals, respectively. D _{OUT_O} ' and D _{OUT_E} ' respectively represent the waveforms of the odd and even pen output data signals when the charge sharing is not performed, and D _{OUT_O} and D _{OUT_E} represent the waveforms of the odd and even pen output data signals of the present invention, respectively. At the time points T2, T4..., the odd-numbered input data signal D _{IN_O} with a positive polarity is _lowered from a high potential to a low potential, and the even-numbered input signal D _{IN_E having} a negative polarity is _raised from a low potential to a high potential, so The valid bit MSB_o and the most significant bit MSB_e will change from 1 to 0. At this time, the present invention performs charge sharing during the reset signal STB with a high potential, and pulls the waveform W _{OUT_O} and the waveform W _{OUT_E} to the target standard in advance. Bit. At the time points T1, T3, T5..., the odd-numbered input data signal D _{IN_O} with a positive polarity _rises from a low potential to a high potential, and the even-numbered input signal D _{IN_E} with a negative polarity _decreases from a high potential to a low potential. Therefore, the most significant bit MSB_o and the most significant bit MSB_e will change from 0 to 1, and the present invention does not perform redundant charge sharing, thereby achieving power saving purposes.

Please refer to FIG. 6. FIG. 6 is a functional block diagram of the source driver 26 in the second embodiment of the present invention. In this embodiment, the source driver 26 includes a driving module 15, a switch control circuit 68, a charge sharing switch 93, and a power supply circuit 95. The driving module 15 includes a shift register 33, a sample holder 43, a one-bit shifter 53, a digital analog converter 63, an operational amplifier 73, and an output switch 83. The input end of the switch control circuit 68 is coupled to the sample holder 43 , and the output end is coupled to the output switch 83 and the charge sharing switch 93 . The source driver 26 drives the data line through the output switch 83, and the charge sharing switch circuit 93 is coupled between the data line and the power supply circuit 95. The power supply circuit 95 can provide different operating voltages, such as V _DD with a high potential, V _GND with a low potential, and a common voltage Vcom.

The shift register 33 of the driving module 15 can generate a corresponding clock control signal according to the clock signal and the start signal generated by the timing controller. The sample holder 43 is coupled to the shift register 33 to sample the input data signal according to the clock control signal and generate a corresponding sample data signal. The level shifter 53 is coupled to the sample holder 43 to adjust the voltage level of the sampled data signal. The digital analog converter 63 is coupled to the level shifter 53 to convert the sampled data signal into an analog data signal. The operational amplifier 73 is coupled to the digital analog converter 63 to amplify the analog data signal and generate a corresponding output data signal. At the same time, after receiving the sampled data signal, the switch control circuit 68 generates a corresponding switch control signal SW according to the most significant bit of the sampled data signal. The output switch 83 is coupled to the operational amplifier 73 and the switch control circuit 68, and can be operated according to the switch control signal SW. When the switch control signal SW is turned on (short-circuit) the output switch 83, the drive module 15 can transmit the output data signal to the data. line. The charge sharing switch 93 is coupled between the data line and the power supply circuit 95 and can be operated according to the switch control signal SW. When the switch control signal SW turns on the charge share switch 93, the data line is coupled to the power supply circuit 95. Corresponding driving voltages are performed to perform charge sharing.

Please refer to FIG. 7. FIG. 7 is a timing diagram of the source driver 26 in the charge sharing mode according to the second embodiment of the present invention. In Fig. 7, the _STB W is represented by a waveform of the reset signal STB, and _D IN_O waveform D _{IN_E} represent odd and even strokes of a pen input data signals, representative of the maximum _odd-W MSB_O pen input data signals _D IN_O of effective bits MSB_o Waveform, W _{MSB_E} represents the waveform of the most significant bit MSB_e of the even pen input data signal D _{IN_E} , D _{OUT_O} ' and D _{OUT_E} ' respectively represent the waveform of the odd and even pen output data signals when the charge sharing is not performed, and D _{OUT_O} And D _{OUT_E} represent the waveforms of the odd-numbered pen and even-number pen output data signals in the present invention, respectively. At time point T1, T3, T5 ..., the pen having an odd number of data signals of positive polarity and _D IN_O of even a pen input data signals D _{IN_E} negative computed by the low-potential was raised to a high potential, so that the maximum effective bits MSB_o It will change from 0 to 1, and the most significant bit MSB_e will change from 1 to 0. At this time, the present invention performs charge sharing during the reset signal STB with a high potential, and couples the odd data lines through the charge sharing switch 93. The power supply V _DD connected to the power supply circuit 76 couples the even data lines to the power supply Vcom of the power supply circuit 76 through the charge sharing switch 93, so that the waveform W _{OUT_O} and the waveform W _{OUT_E can} be pulled to the target standard in advance. At time point T2, T4 ... when, with the pen input data signals _D IN_O odd positive polarity sum of even a pen input data signals D _{IN_E} computed by the high negative potential dropped to a low potential, so that the maximum effective bits will MSB_o The change from 1 to 0, and the most significant bit MSB_e will change from 0 to 1. At this time, the present invention performs charge sharing while the reset signal STB has a high potential, and couples the odd data lines through the charge sharing switch 93. The power supply Vcom to the power supply circuit 76 couples the even data lines to the power supply V _{GND of the} power supply circuit 76 through the charge sharing switch 93, so that the waveform W _{OUT_O} and the waveform W _{OUT_E can} be pulled to the target standard in advance.

The liquid crystal display of the invention can control the charge sharing according to the MSB change of the data signal, and generate the corresponding switch control signal SW through the switch control circuit, thereby avoiding unnecessary charge sharing, reducing the current consumption of the source driving circuit, and reducing The heat is diverging.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10, 20. . . LCD Monitor

12, 22. . . LCD panel

14, 24. . . Timing controller

16, 26. . . Source driver

18, 28. . . Gate driver

270. . . Gate

30 to 33. . . Shift register

41~43. . . Sample holder

51～53. . . Level shifter

61-63. . . DAC

71-73. . . Operational Amplifier

81～83. . . Output switch

D ₁ -D _m . . . Data line

G ₁ -G _n . . . Gate line

P ₁₁ -P _mn . . . Display unit

OB. . . Output buffer

95. . . Power supply circuit

281, 282. . . MSB latch

291 292. . . D-type flip-flop

68, 300. . . Switch control circuit

90, 93, CS. . . Charge sharing switch

15, 100, 200. . . Drive module

Figure 1 is a schematic view of a liquid crystal display in the prior art.

Figure 2 is a schematic view of a liquid crystal display of the present invention.

Fig. 3 is a functional block diagram of a source driver in the first embodiment of the present invention.

Figure 4 is a functional block diagram of a switch control circuit in accordance with an embodiment of the present invention.

Fig. 5 is a timing chart of the source driver of the first embodiment of the present invention at the time of charge sharing.

Figure 6 is a functional block diagram of a source driver in a second embodiment of the present invention.

Figure 7 is a timing chart of the source driver of the second embodiment of the present invention during charge sharing.

31, 33. . . Shift register

41, 42. . . Sample holder

51, 52. . . Level shifter

61, 62. . . DAC

71, 72. . . Operational Amplifier

81, 82. . . Output switch

90. . . Charge sharing switch

300. . . Switch control circuit

100, 200. . . Drive module

Claims (33)

A liquid crystal display device for controlling charge sharing according to a Most Significant Bit (MSB) of a data signal, comprising: a first data line for receiving a first output data signal; and an adjacent first The second data line of the data line is configured to receive a second output data signal; a source driver circuit (Source Driver) coupled to the first and second data lines, comprising: a first driving module, Corresponding to the first input data signal according to a first input data signal, comprising: a first shift register (Shift Register) for receiving a start signal and a clock signal, and The first signal and the clock signal generate a first clock control signal; a first sample hold (Sample & Hold) coupled to the first shift register for receiving the first input data signal, And latching the first input data signal according to the first clock control signal to generate a corresponding one of the first sample data signals; and a first output switch for transmitting the first output data signal according to a switch control signal to a first data line, the first output switch includes: a control end for receiving the switch control signal; an input end coupled to the first sample holder; and an output end coupled to the first data a second driving module for generating a corresponding one of the second output data signals according to a second input data signal, comprising: a second shift register for receiving the start signal and the And generating a second clock control signal according to the start signal and the clock signal; a second sample holder coupled to the second shift register for receiving the second input Data signal, and latching the second input data signal according to the second clock control signal to generate a corresponding one of the second sample data signals; and a second output switch for controlling the signal according to the switch to transmit the second Outputting a data signal to the second data line, the second output switch includes: a control end for receiving the switch control signal; an input end coupled to the second sample holder; and an output end coupled On the second data line a switch control circuit coupled to the first and second sample holders for generating the switch control signal according to the most significant bits of the first and second sampled data signals; and a charge sharing switch coupled Between the output end of the first output switch and the output end of the second output switch, and according to the switch control signal, the output end of the first output switch and the output end of the second output switch are electrically connected, or The output of the first output switch and the output of the second output switch are separated. The liquid crystal display device of claim 1, wherein the switch control circuit comprises: a first logic circuit, comprising: a trigger terminal for receiving a maximum effective bit of the first sampled data signal; and a reset terminal For receiving a reset signal, and an output terminal for outputting a first logic signal according to the signal received by the trigger terminal and the reset terminal; a second logic circuit comprising: a trigger terminal for receiving a maximum effective bit of the second sampled data signal; a reset terminal for receiving the reset signal; and an output terminal for outputting a second logic according to the signal received by the trigger terminal and the reset terminal And a third logic circuit for generating the switch control signal according to the first and second logic signals, the third logic circuit comprising: a first input end coupled to the output of the first logic circuit a second input end coupled to the output end of the second logic circuit; and an output end for outputting the switch control signal. The liquid crystal display device of claim 2, wherein the first and second logic circuits comprise a D-type Flip-Flop, and the third logic circuit comprises an OR gate (OR Gate) ). The liquid crystal display device of claim 2, wherein the switch control circuit further comprises: a first maximum effective bit latch coupled to the first sample holder and the first logic circuit for obtaining the a maximum effective bit of the first sampled data signal; and a second most significant bit latch coupled to the second sample holder and the second logic circuit for obtaining the maximum of the second sampled data signal Valid bit. The liquid crystal display device of claim 2, wherein the switch control circuit further comprises: a level shifter (Level Shifter) coupled to the third logic circuit for adjusting a voltage level of the switch control signal . The liquid crystal display device of claim 1, wherein the first driving module further comprises: a first level shifter coupled to the first sample holder for adjusting the first sampled data signal a voltage level of a digital-to-analog converter (DAC) coupled to the first level shifter for converting the first sampled data signal into a corresponding one a first analog signal; and a first operational amplifier (Operational Amplifier) coupled to the first digital analog converter for amplifying the first analog signal to generate a corresponding first output data signal; The second driving module further includes: a second level shifter coupled to the second sample holder for adjusting a voltage level of the second sampled data signal; and a second digital analog converter coupled The second level shifter is configured to convert the second sampled data signal into a corresponding second analog signal; and a second operational amplifier is coupled to the second digital analog converter for Amplify the second analog signal to produce a phase It should be of the second output data signals. The liquid crystal display device of claim 1, further comprising a timing controller for providing the start signal and the clock signal. A liquid crystal display device for controlling charge sharing according to a maximum effective bit of a data signal, comprising: a data line for receiving an output data signal; and a source driving circuit coupled to the data line, comprising: a driving The module is configured to generate a corresponding output data signal according to an input data signal, comprising: a shift register for receiving a start signal and a clock signal, and according to the start signal and the clock The signal is used to generate a clock control signal; a sample holder coupled to the shift register for receiving the input data signal, and latching the input data signal according to the clock control signal to generate a corresponding one of the samples An output switch for transmitting the output data signal to the data line according to a switch control signal, the output switch comprising: a control end for receiving the switch control signal; and an input end coupled to the data signal a sampling holder; and an output coupled to the data line; a switch control circuit coupled to the sample holder for use according to the sampled data signal The large effective bit generates the switch control signal; a first power source for providing a high potential operating voltage; a second power source for providing a low potential operating voltage; and a third power source for providing a common voltage; And a charge sharing switch for electrically connecting the output end of the output switch to the first power source, the second power source or the third power source according to the switch control signal. The liquid crystal display device of claim 8, wherein the switch control circuit comprises a logic circuit, the logic circuit comprising: a trigger terminal for receiving a maximum effective bit of the sampled data signal; and a reset terminal for Receiving a reset signal; and an output terminal for outputting the switch control signal according to the signal received by the trigger terminal and the reset terminal. The liquid crystal display device of claim 9, wherein the logic circuit comprises a D-type flip-flop. The liquid crystal display device of claim 9, wherein the switch control circuit further comprises: a maximum effective bit latch coupled to the sample holder and the logic circuit for obtaining the maximum effective value of the sampled data signal Bit. The liquid crystal display device of claim 9, wherein the switch control circuit further comprises: a bit shifter coupled to the logic circuit for adjusting a voltage level of the switch control signal. The liquid crystal display device of claim 8, wherein the driving module further comprises: a one-position shifter coupled to the sample holder for adjusting a voltage level of the sampled data signal; a digital analog conversion And the operational amplifier is coupled to the digital analog converter for amplifying the analog signal to generate Corresponding to the output data signal. The liquid crystal display device of claim 8, further comprising a clock controller for providing the start signal and the clock signal. A source driving circuit for controlling charge sharing according to a maximum effective bit of a data signal, comprising: a first driving module, configured to generate a corresponding one of the first output data signals according to a first input data signal to drive a The first load module includes: a first shift register for receiving a start signal and a clock signal, and generating a first clock control according to the start signal and the clock signal a first sample holder, coupled to the first shift register, for receiving the first input data signal, and latching the first input data signal according to the first clock control signal to generate a phase Corresponding to one of the first sampling data signals; a first output switch for transmitting the first output data signal to the first load according to a switch control signal, the first output switch comprising: a control end for receiving the a switch control signal; an input coupled to the first sample holder; and an output coupled to the first load; a second drive module for generating a second input data signal Corresponding to one of the second output data signals to drive a second load, the second driving module includes: a second shift register for receiving the start signal and the clock signal, and according to the start The signal and the clock signal generate a second clock control signal; a second sample holder coupled to the second shift register for receiving the second input data signal, and according to the second clock The control signal latches the second input data signal to generate a corresponding one of the second sample data signals; and a second output switch for transmitting the second output data signal to the second load according to the switch control signal, the The second output switch includes: a control terminal for receiving the switch control signal; an input terminal coupled to the second sample holder; and an output terminal coupled to the second load; a switch control circuit coupled And the first and second sample holders are configured to generate the switch control signal according to the most significant bits of the first and second sampled data signals; and a charge sharing switch coupled to the output of the first output switch end The output end of the second output switch is electrically connected to the output end of the first output switch and the output end of the second output switch according to the switch control signal, or electrically separate the first output switch An output and an output of the second output switch. The source driving circuit of claim 15, wherein the switch control circuit comprises: a first logic circuit, comprising: a trigger terminal for receiving a maximum effective bit of the first sampled data signal; and a reset terminal For receiving a reset signal, and an output terminal for outputting a first logic signal according to the signal received by the trigger terminal and the reset terminal; and a second logic circuit comprising: a trigger end, used for: Receiving a maximum effective bit of the second sampled data signal; a reset terminal for receiving the reset signal; and an output terminal for outputting a second signal according to the trigger terminal and the signal received by the reset terminal a logic signal; and a third logic circuit for generating the switch control signal according to the first and second logic signals, the third logic circuit comprising: a first input end coupled to the first logic circuit An output end; a second input end coupled to the output end of the second logic circuit; and an output end for outputting the switch control signal. The source driver circuit of claim 16, wherein the first and second logic circuits comprise a D-type flip-flop, and the third logic circuit comprises an OR gate. The source driving circuit of claim 16, wherein the switch control circuit further comprises: a first maximum effective bit latch coupled to the first sample holder and the first logic circuit for obtaining a second most significant bit latch of the first sampled data signal; and a second maximum valid bit latch coupled to the second sample holder and the second logic circuit for obtaining the second sampled data signal The most significant bit. The source driver circuit of claim 16, further comprising a one-bit shifter coupled to the third logic circuit for adjusting a voltage level of the switch control signal. The source driving circuit of claim 15, wherein the first driving module further comprises: a first level shifter coupled to the first sample holder for adjusting the first sampling data a voltage level of the signal; a first digital analog converter coupled to the first level shifter for converting the first sampled data signal into a corresponding first analog signal; and a first An operational amplifier coupled to the first digital analog converter for amplifying the first analog signal to generate a corresponding first output data signal; and the second driving module further comprising: a second bit shift The second sampling holder is coupled to the second sampling holder for adjusting the voltage level of the second sampling data signal; a second digital analog converter is coupled to the second level shifting device for The second sample data signal is converted into a corresponding second analog signal; and a second operational amplifier is coupled to the second digital analog converter for amplifying the second analog signal to generate the corresponding Second, the output data signal. A source driving circuit for controlling charge sharing according to a maximum effective bit of a data signal, comprising: a driving module, configured to generate a corresponding one of the output data signals according to an input data signal to drive a load, comprising: The shift register is configured to receive a start signal and a clock signal, and generate a clock control signal according to the start signal and the clock signal; a sample holder coupled to the shift register, Receiving the input data signal, and latching the input data signal according to the clock control signal to generate a corresponding sample data signal; and an output switch for transmitting the output data signal to the data according to a switch control signal The output switch includes: a control terminal for receiving the switch control signal; an input terminal coupled to the sample holder; and an output coupled to the data line; a switch control circuit coupled The sample holder is configured to generate the switch control signal according to the most significant bit of the sampled data signal; a first power source for providing a high potential operation a second power source for providing a low potential operating voltage; a third power source for providing a common voltage; and a charge sharing switch for electrically controlling the output of the output switch according to the switch control signal Connected to the first power source, the second power source, or the third power source. The source driving circuit of claim 21, wherein the switch control circuit comprises a logic circuit, the logic circuit comprising: a trigger terminal for receiving a maximum effective bit of the sampled data signal; and a reset terminal Receiving a reset signal; and an output terminal for outputting the switch control signal according to the signal received by the trigger end and the reset end. The source driver circuit of claim 22, wherein the logic circuit comprises a D-type flip-flop. The source driving circuit of claim 22, wherein the switch control circuit further comprises a maximum effective bit latch coupled to the sample holder and the logic circuit for obtaining the maximum effective value of the sampled data signal. Bit. The source drive circuit of claim 21, wherein the drive module further comprises: a one-position shifter coupled to the sample holder for adjusting a voltage level of the sampled data signal; a digital analogy a converter coupled to the level shifter for converting the sampled data signal to a corresponding analog signal; and an operational amplifier coupled to the digital analog converter for amplifying the analog signal The corresponding output data signal is generated. The source driver circuit of claim 21, further comprising a one-bit shifter coupled to the switch control circuit for adjusting a voltage level of the switch control signal. The source driving circuit of claim 21, further comprising a clock controller for providing the start signal and the clock signal. A method for driving a liquid crystal display device according to a maximum effective bit of a data signal, comprising: providing a start signal, a first input data signal, and a second input data signal; and providing corresponding signals according to the first input data signal a first output data signal; providing a corresponding one of the second output data signals according to the second input data signal; latching the first and second input data signals according to the start signal to respectively generate a corresponding one of the first a sampling data signal and a second sampling data signal; generating a switching control signal according to the most significant bit of the first and second sampling data signals; and a first output switch controlling the first output data signal according to the switching control signal a signal transmission path of a first data line on a liquid crystal display device; a second output switch controls a signal transmission path of the second output data signal to a second data line of the liquid crystal display device according to the switch control signal; And a charge sharing switch electrically connecting the output end of the first output switch according to the switch control signal and the An output terminal of the second output switch, or electrically separated from the first output terminal of the output switch and the output terminal of the second output of the switch. The method of claim 28, further comprising: determining whether the most significant bit of the first sampled data signal is converted from a first value to a second value; determining whether the most significant bit of the second sampled data signal is Converting the first value to the second value; and when the first significant value of the first or second sampled data signal is converted from the first value to the second value, generating the switch control signal to close the first An output switch and the second output switch simultaneously turn on the charge sharing switch. The method of claim 28, further comprising: adjusting a voltage level of the first sampled data signal, the second sampled data signal, and the switch control signal; converting the first and second sampled data signals into phases Corresponding to one of the first analog signal and the second analog signal; and respectively amplifying the first and second analog signals to generate corresponding first and second output data signals. A method for driving a liquid crystal display device according to a maximum effective bit of a data signal, comprising: providing a start signal and an input data signal; providing a high potential operating voltage, a low potential operating voltage, and a common voltage; The input data signal provides a corresponding one of the output data signals; the input data signal is latched according to the start signal to generate a corresponding one of the sampled data signals; and a switch control signal is generated according to the most significant bit of the sampled data signal; The output switch controls the output data signal to a signal transmission path of a data line on the liquid crystal display device according to the switch control signal; and a charge sharing switch electrically connects the output end of the output switch to the high according to the switch control signal a potential operating voltage, the low potential operating voltage, or the common voltage. The method of claim 31, further comprising: determining whether the most significant bit of the sampled data signal is converted from a first value to a second value or from the second value to the first value; When the most significant bit of the sampled data signal is converted from the first value to the second value, the output end of the output switch is electrically connected to the high potential operating voltage or the low potential operating voltage; and when the sampled data signal is When the most significant bit is converted to the first value by the second value, the output end of the output switch is electrically connected to the common voltage. The method of claim 31, further comprising: adjusting a voltage level of the sampled data signal and the switch control signal; converting the sampled data signal to a corresponding analog signal; and amplifying the analog signal to generate a corresponding signal The output data signal.