TWI706389B - Source driver and method thereof - Google Patents

Abstract

A source driver includes a digital to analog converter and a line latch. The line latch is coupled to the digital to analog converter. The digital to analog converter is configured to receive a data signal having a plurality of digital data and convert the digital data into a plurality of analog driving signals. The line latch is configured to latch the analog drive signals and output the analog drive signals according to a rising edge of a clock signal.

Description

Source driver and its method

This case is about a display driving technology, especially a source driver and its method.

At present, display devices have been widely used in various electronic devices such as televisions (TV), tablet PCs, mobile phones, smart watches, and smart home appliances.

The display device has the function of displaying images. General display devices include a source driver and a gate driver. Among them, the driving method of the display device is to transmit signals through the source driver and the gate driver to drive the pixels on the display device. When the pixels on the display device are driven, the display device can display the corresponding image.

However, the number of pixels and frame per second (FPS) of current display devices are gradually increasing. The signal is limited by the driving structure in the source driver, and the signal may cause the display performance of the display device to decrease due to the driving delay.

In view of the above, this case proposes a source driver. The source driver includes a digital-to-analog conversion circuit and a line latch circuit. The line latch circuit is coupled to the digital-to-analog conversion circuit. Here, the digital-to-analog conversion circuit is used to receive and convert a data signal with multiple digital data Multiple digital data are converted into multiple analog drive signals. The line latch circuit is used for latching a plurality of analog driving signals and outputting a plurality of analog driving signals according to the rising edge of a timing signal.

This case discloses a source driving method in another embodiment. The method includes: receiving a data signal with multiple digital data; converting the multiple digital data into multiple analog driving signals; and latching the multiple analog driving signals according to a timing signal.

To sum up, according to the source driver and method of the present case, the digital analog is converted into a program first, and then the latch output program is executed, so that the signal is not delayed during the source driving process, thereby maintaining the display of the display device efficacy.

10: Source driver

20: timing controller

100: data interface circuit

200: Displacement temporary storage circuit

300: data temporary storage circuit

310: Data Temporary Storage Sub-circuit

400: Level shift circuit

500: Digital analog conversion circuit

510: Input

520: output

530: switch side

540: The first switch circuit

550: second switching circuit

600: Conversion latch circuit

700: Line latch circuit

800: output buffer circuit

D1: Data signal

D2: Timing signal

D3: Clock signal

W: square wave

W _R : rising edge

W _F : Falling edge

Y: Digital data

Y1~Y960: Digital data

Y’: analog drive signal

M: Transistor

BK: Horizontal scan data during blank period

S10~S18: steps

T1: Square wave time span

T2: The time interval from "the last data received from the data interface circuit" to "the rising edge of the timing signal"

T3: The transmission time corresponding to the shorter transmission path

T4: The transmission time corresponding to the longer transmission path

T5: The time interval between "the beginning of the first digital data of the data signal" and "the end of the last digital data of the data signal"

T6: The time interval from "the end of the last digital data of the data signal" to "the beginning of the first digital data of the next data signal"

FIG. 1 is a schematic diagram of a source driver according to an embodiment of the present application.

FIG. 2 is a signal diagram of source driving according to an embodiment of the present application.

FIG. 3 is a schematic diagram of a source driver according to another embodiment of the present application.

FIG. 4 is a schematic diagram of a digital-to-analog conversion circuit according to an embodiment of the present application.

FIG. 5 is a schematic diagram of a digital data transmission path according to an embodiment of the present application.

Fig. 6 is a signal diagram of the sequence of digital data according to an embodiment of the present application.

FIG. 7 is a flowchart of a source driving method according to an embodiment of the present application.

1, in one embodiment, the source driver 10 includes a data interface circuit (data interface) 100, a shift register circuit (shift register) 200, a data register circuit (data register) 300, a digital Analog conversion circuit (digital to analog converter (DAC) 500, a line latch 700 and an output buffer 800.

Please refer to FIG. 7. Here, according to an embodiment, the source driver 10 is used to receive a data signal D1 having a plurality of digital data Y (step S10), and convert the plurality of digital data Y into a plurality of analog driving signals Y '(Step S12), and latch a plurality of analog driving signals Y'according to the timing signal D2 (Step S14). In one embodiment, the source driver 10 buffers the latched analog driving signals Y'(step S16) and outputs the buffered analog driving signals Y'according to the timing signal D2 (step S18).

In one embodiment, the process of receiving, converting, and outputting the aforementioned data signal D1 in the source driver 10 sequentially passes through the data interface circuit 100, the data temporary storage circuit 300, the digital-to-analog conversion circuit 500, the line latch circuit 700, and the output buffer. Circuit 800. In other words, here, the displacement temporary storage circuit 200 and the data temporary storage circuit 300 are respectively coupled to the data interface circuit 100. The data temporary storage circuit 300 is coupled to the displacement temporary storage circuit 200. The digital-to-analog conversion circuit 500 is coupled to the data temporary storage circuit 300. The line latch circuit 700 is coupled to the digital-to-analog conversion circuit 500. The output buffer circuit 800 is coupled to the latch circuit 700.

In one embodiment, the data interface circuit 100 is used to process the data signal D1 and output the clock signal D3. Specifically, the data interface circuit 100 is the receiving end of the source driver 10, so the data interface circuit 100 is used to receive a data signal D1 having a plurality of digital data Y. Among them, a plurality of digital data Y are arranged in series in the data signal D1. The data interface circuit 100 can convert a plurality of digital data Y arranged in series into a plurality of digital data Y arranged in parallel. The data interface circuit 100 then outputs a data signal D1 having a plurality of digital data Y arranged in parallel to the data temporary storage circuit 300. The data temporary storage circuit 300 is used for temporary storage according to the clock signal D3 Data signal D1. In one embodiment, the shift register circuit 200 generates a sequential signal (not shown in the figure) to the data register circuit 300 according to the periodicity of the clock signal D3. The displacement temporary storage circuit 200 controls the data temporary storage circuit 300 according to the sequential signal to temporarily store the data signal D1 by sampling one digital data Y at a time. According to an embodiment, the timing controller 20 is used to output the timing signal D2, that is, the timing controller 20 controls the action timing in the source driver 10 through the timing signal D2.

In one embodiment, the digital-to-analog conversion circuit 500 is used to receive a data signal D1 having a plurality of digital data Y, and can convert the plurality of digital data Y into a plurality of analog drive signals Y', and output a plurality of analog drive signals Y' To the line latch circuit 700. In one embodiment, the digital-to-analog conversion circuit 500 receives the data signal D1 through the data temporary storage circuit 300, that is, every time the data temporary storage circuit 300 receives a piece of digital data Y, the data temporary storage circuit 300 outputs the digital data Y to Digital-to-analog conversion circuit 500.

According to an embodiment, the line latch circuit 700 is used to latch a plurality of analog driving signals Y′, and output a plurality of analog driving signals Y′ according to the rising edge W _{R of the} timing signal D2. Specifically, when the rising edge W _{R of the} timing signal D2 starts to be enabled, the line latch circuit 700 will latch the multiple analog drive signals Y′ output from the digital-to-analog conversion circuit 500 to the line latch circuit 700. Wherein, the line latch circuit 700 latches the analog drive signal Y', and the line latch circuit 700 only latches the analog drive signal Y'in the same set of data signals D1. Therefore, the data signal D1 latched by the line latch circuit 700 will not be overwritten by the data signal D1 of other groups. When the line latch circuit 700 receives the rising edge W _{R of the} timing signal D2, the line latch circuit 700 outputs a plurality of analog driving signals Y′ (ie, a set of data signals D1) latched by the line latch circuit 700. After the line latch circuit 700 finishes outputting a group of data signals D1, the line latch circuit 700 restarts to latch the next group of data signals D1.

In one embodiment, the output buffer circuit 800 buffers the latched analog driving signals Y′ and outputs the buffered analog driving signals Y′ according to the timing signal D2. Specifically, the output buffer circuit 800 receives a plurality of analog driving signals Y′ output from the line latch, and buffers the plurality of analog driving signals Y′. When the output buffer circuit 800 receives a timing signal D2 falling edge W _F, i.e. the output buffer circuit 800 is output a plurality of analog output signals Y buffer circuit 800 drives buffer '. Generally, the multiple analog drive signals Y′ output by the output buffer circuit 800 each time are a set of data signals D1.

In an embodiment, the source driver 10 further includes a level shifter 400 (level shifter). The level shift circuit 400 is coupled between the data temporary storage circuit 300 and the digital-to-analog conversion circuit 500. The level shift circuit 400 is used to convert the data signal D1 suitable for the operation of the data temporary storage circuit 300 into a data signal D1 suitable for the operation of the digital-to-analog conversion circuit 500. Generally, the voltage of the data signal D1 suitable for the operation of the digital-to-analog conversion circuit 500 is higher than the voltage of the data signal D1 of the data temporary storage circuit 300.

In one embodiment, the source driver 10 is further coupled to a timing controller (TCON) 20 to receive the data signal D1 and the timing signal D2 output by the timing controller 20. The timing controller 20 controls the operation timing of the source driver 10 through the timing signal D2. In addition, the timing controller 20 can convert an image signal into a data signal D1 that can be used by the source driver 10. The timing controller 20 then outputs the data signal D1 to enable the source driver 10 to output the analog driving signal Y'for driving the display device. According to an embodiment, the timing controller 20 is used to output the clock signal D3 to the data interface circuit 100. That is, the timing controller 20 outputs the clock signal D3 to the shift register circuit 200 through the data interface circuit 100.

Please refer to FIG. 2, for clarity, in some embodiments, the digital data Y of different pens are respectively labeled Y1 to Y960. In some embodiments, the data signal D1 may be marked with gray levels L0 to L255, respectively.

Please continue to refer to FIG. 2, in one embodiment, a set of data signals D1 has a plurality of digital data Y and a horizontal blanking period (horizontal blanking period) data BK. When the data signal D1 is in the source driving process, multiple digital data Y will be converted into multiple analog drive signals Y'. Therefore, the source driving process is to first receive a set of data signals D1 with multiple digital data Y, and then output a set of data signals D1 with multiple analog drive signals Y'. The timing signal D2 is a periodic square wave W, and the square wave W has a rising edge W _R and a falling edge W _F , so the timing signal D2 has a rising edge W _R and a falling edge W _F. Among them, the rising edge W _R and the falling edge W _{F of the} timing signal D2 are respectively used as signals for controlling the operation of the source driver 10. Timing signal D2 is typically a square wave W corresponds to a set of data signals D1, i.e. a rising edge of a square wave W W _R W _F. And a falling edge controlling the source driver 10 processes a set of data signals D1.

According to an embodiment, the display device outputs a display image through a plurality of horizontal scanning lines, and the display device outputs one horizontal scanning line at a time. Among them, a plurality of digital data Y1 to Y960 in a set of data signal D1 are signals to be output by one horizontal scan line. The data BK during the horizontal scanning blank period is used as a buffer signal between two adjacent horizontal scanning lines output by the display device. And in a group of data signals D1, the data BK during the horizontal scanning blank period is set before the plurality of digital data Y1 to Y960. According to an embodiment, in a group of data signals D1, the data BK during the horizontal scanning blank period is arranged after the plurality of digital data Y1 to Y960.

According to an embodiment, the data interface circuit 100 is used to determine the plurality of digital data Y1 to Y960 in the data signal D1 and the data BK during the horizontal scanning blank period. In other words In other words, the data interface circuit 100 can determine the digital signal Y to be output on the horizontal scan line and the buffer signal between two adjacent horizontal scan lines.

Please refer to FIG. 3, in one embodiment, the digital-to-analog conversion circuit 500 and the line latch circuit 700 are integrated into a conversion latch circuit 600. Specifically, the conversion latch circuit 600 has the functions of the digital-to-analog conversion circuit 500 and the line latch circuit 700. The conversion latch circuit 600 is used for receiving a data signal D1 having a plurality of digital data Y, and can convert the plurality of digital data Y into a plurality of analog driving signals Y′, and latching a plurality of analog driving signals Y′. The conversion latch circuit 600 outputs a plurality of analog driving signals Y′ according to the rising edge W _{R of the} timing signal D2.

Please refer to FIG. 3 continuously. In one embodiment, the output buffer circuit 800 is coupled to the conversion latch circuit 600. The output buffer circuit 800 can output driving signals corresponding to the plurality of analog Y 'signal D2 based on the timing of the falling edge of W _F.

Referring to FIG. 4, in an embodiment, a set of digital-to-analog conversion circuits 500 includes a plurality of switch terminals 530, a plurality of input terminals 510, an output terminal 520, and a plurality of transistors M. The multiple input terminals 510 are coupled to the output terminal 520 through multiple transistors M arranged in multiple levels. Each switch terminal 530 corresponds to a level of transistor M (for example, R _A 0 to R _A 7, R _A 0'to R _A 7', R _B 0 to R _B 7, and R _B 0'to R _B 7'). When the digital-to-analog conversion circuit 500 is operating, the input terminal 510 corresponds to the output terminal 520 in a one-to-one manner. That is, at most only one input terminal 510 and output terminal 520 are in a conductive state, and the remaining input terminals 510 and output terminals 520 are disconnected. The switch terminal 530 controls the transistors M of each level in a dichotomy (for example, only one of R _A 0 and R _A 0'will turn on the corresponding transistor M), so there is only one input terminal 510 and output Each transistor M between the terminals 520 is turned on, and at least one transistor M between the other input terminals 510 and the output terminal 520 must be open. When the input terminal 510 and the output terminal 520 are conductive, the digital-to-analog conversion circuit 500 inputs the digital data Y from the conductive input terminal 510, and outputs the corresponding analog driving signal Y′ from the output terminal 520. Among them, the analog conversion circuit 500 converts the digital data Y into an analog driving signal Y′. In one embodiment, each input terminal 510 is used to transmit different sets of data signals D1 (for example, L0 to L255 in the figure).

According to an embodiment, as shown in FIG. 4, the source driver 10 includes two sets of digital-to-analog conversion circuits 500. The digital-to-analog conversion circuit 500 further includes a first switch circuit 540 and a second switch circuit 550. Each group of data signal D1 with a plurality of digital data Y has a corresponding input terminal 510 in each group of digital-to-analog conversion circuit 500. The switch terminals 530 in each group of digital-to-analog conversion circuits 500 are all coupled to the first switch circuit 540. The output terminal 520 of each group of digital-to-analog conversion circuits 500 is coupled to the second switch circuit 550. The first switch circuit 540 is used to selectively control the switch terminals 530 of one group of digital-to-analog conversion circuits 500 so that one of the input terminals 510 and the output terminal 520 of the group of digital-to-analog conversion circuits 500 are turned on. The second switch circuit 550 selectively controls the output terminal 520 in one of the digital-to-analog conversion circuits 500 so that the controlled output terminal 520 outputs a data signal D1 having a plurality of analog driving signals Y'.

4, in an embodiment, when the first switch circuit 540 controls the switch terminal 530 in one of the conversion latch circuits 600 to make the input terminal 510 and the output terminal 520 conductive, the conversion latch circuit 600 converts a plurality of digits The data Y becomes a plurality of analog drive signals Y', and the plurality of analog drive signals Y'are latched. The second switch circuit 550 controls the output terminal 520 in one of the switching latch circuits 600, so that the controlled output terminal 520 outputs a plurality of analog driving signals Y'that are latched.

Please refer to FIG. 1, FIG. 5 and FIG. 6 at the same time. According to some embodiments, in the process of source driving, the process of receiving the data signal D1 with multiple digital data Y is determined according to the path length of the multiple digital data Y. The receiving order of multiple digital data Y. Specifically, the information The temporary storage circuit 300 includes a plurality of data temporary storage sub-circuits 310. When the source driver 10 is processing a group of data signals D1, each data temporary storage sub-circuit 310 processes a piece of digital data Y respectively. Therefore, the distance that the digital data Y is transferred from the data interface circuit 100 to the line latch circuit 700 will vary due to different digital data Y. By receiving the digital data Y with a longer transmission path first and receiving the digital data Y with a closer transmission path later, the source driver 10 can reduce the difference in the transmission time of each digital data Y. Therefore, this embodiment can avoid the situation that the output time of each analog driving signal Y'is inconsistent in the source driving process, which causes the voltage output slew rate of each analog driving signal Y'to be different. The aforementioned rate of change of voltage output refers to the slope of the analog drive signal Y'. Please refer to FIGS. 3, 5 and 6 at the same time. According to an embodiment, the distance of the digital data Y from the data interface circuit 100 to the conversion latch circuit 600 will be different due to different digital data Y. By receiving the digital data Y with a longer transmission path first and receiving the digital data Y with a closer transmission path later, the source driver 10 can reduce the difference in the transmission time of each digital data Y.

Please continue to refer to FIG. 5 and FIG. 6, the procedure of receiving a data signal D1 with a plurality of digital data Y is to determine the receiving order of the plurality of digital data Y according to the path length of the transmission of the plurality of digital data Y as shown below. A group of data signals D1 includes digital data Y1 to digital data Y960. The digital data Y1 and Y960 have a shorter transmission path, and the digital data Y480 and Y481 have a longer transmission path. Therefore, the data interface circuit 100 receives the digital data Y480 and Y481 first, and the data interface circuit 100 receives the digital data Y1 and Y960 afterwards. Among them, the transmission time T3 corresponding to the shorter transmission path is less than the transmission time T4 corresponding to the longer transmission path.

In one embodiment, the latching time point of the plurality of analog driving signals Y′ corresponding to the rising edge W _{R of the} timing signal D2 is not later than the rising edge W _{R of the} aforementioned timing signal D2. That is, the time for latching a plurality of analog driving signals Y′ needs to be completed during the rising edge W _R of the timing signal D2. Specifically, the rising edge W _{R of the} timing signal D2 is used to drive the line latch circuit 700 to output a plurality of analog drive signals Y', so the line latch circuit 700 must complete the latch before receiving the rising edge W _{R of the} timing signal D2 The aforementioned analog drive signal Y'(ie, a set of data signals D1).

Referring to FIG. 2, in one embodiment, the time interval between the rising edge W _R and the falling edge W _F of the same square wave W in the timing signal D2 is a square wave time interval T1. The aforementioned square wave time interval T1 must be greater than the time interval from "the line latch circuit 700 outputs multiple analog drive signals Y'" to "the output buffer circuit 800 receives the aforementioned multiple analog drive signals Y'". Accordingly, when the falling edge of the output W _F. 800 W according to the square wave output buffer circuit driving the plurality of analog signals Y ', the plurality of the analog driving signals Y' have been transferred to the output buffer circuit 800.

In some embodiments, the source driver 10 and the timing signal D2 method can meet the rising edge W _R analog driving signals corresponding to the plurality of Y 'time point of the latch is not later than the rising edge of the timing signal W _R D2, so It can avoid the situation that the output time of each analog driving signal Y'is inconsistent in the process of source driving, which causes the voltage output change rate of each analog driving signal Y'to be different.

Referring to FIG. 6, according to an embodiment, the time interval T5 between "the first digital data Y of the data signal D1 starts" and "the last digital data Y of the data signal D1 ends" is reduced to satisfy the timing signal D2 The latching time point of the multiple analog drive signals Y′ corresponding to the rising edge W _{R of} , is no later than the rising edge W _{R of the} aforementioned timing signal D2.

In one embodiment, by increasing the transmission rate of the data signal D1 in the source drive, the timing signal D2 corresponding to the rising edge W _R of the plurality of analog drive signals Y'is latched no later than the aforementioned timing signal. The rising edge of D2 W _R.

In one embodiment, the source driver 10 is disposed in a display device (not shown), and the source driver 10 is used to drive pixels on the display device to display images.

In one embodiment, when the resolution of the display device is "3840*2160", it means that the number of pixels of the display device is 3840 rows, which means that the display device has 3840 scan lines and 2160 data lines . Each pixel includes 3 sub-pixels. The display device may use at least one or more source drivers 10 (in this embodiment, the display device uses twelve source drivers 10 for illustration), and each source driver 10 uses a two-pair transmission method. Therefore, each source driver 10 can process two packets at the same time. Front-end transmission time (that is, the source driver processes a set of data signals, between "the first digital data Y is received from the data interface circuit 100" to "the last analog drive signal Y'is output to the line latch circuit 700" The time interval is 300 nanoseconds (ns). In this embodiment, a piece of digital data Y and a corresponding piece of analog drive signal Y′ are referred to as a piece of data. The time interval T2 from "the last data Y received from the data interface circuit 100" to "the rising edge W _{R of the} timing signal D2" is 181.25 ns. The number of bits of a piece of data and a packet is 9 bits (bit). The original transmission rate may be 1.44 billion bits per second (Gbps).

In summary, therefore, the number of packets processed by one source driver 10 in one horizontal scan line is 960 (3840*3/12=960, the number of horizontal pixels*the number of sub-pixels/the number of source drivers). In a pair type transmission mode, the number of packets processed by a source driver 10 in a horizontal scan line is 480 (960/2). Therefore, in order to satisfy that the latching time point of the multiple analog driving signals Y′ corresponding to the rising edge W _{R of the} timing signal D1 is no later than the rising edge W _{R of the} aforementioned timing signal D1. The last data is still missing 118.75ns (300-181.25=118.75). The original transmission time of each piece of data is 6.25ns (1*9/1.44=6.25, the number of bits of a piece of data/original transmission rate). The original transmission time of each piece of data must be reduced by 0.2474ns (118.75/480≒0.2474). The corrected transmission time of each piece of data is 6.026ns (6.25-0.2474=6.0026). The corrected transmission time converted to one bit is 0.66696ns (6.0026/9≒0.66696). Finally, the modified transmission time is converted into a modified transmission rate of 1.5Gbps. Therefore, by increasing the transmission rate of each data to 1.5Gbps, the time interval T5 between "the first digital data of data signal D1 starts Y" and "the last digital data Y of data signal D1 ends" is reduced to The latching time point of the multiple analog driving signals Y′ corresponding to the rising edge W _{R of the} timing signal D2 is no later than the rising edge W _{R of the} foregoing timing signal D2.

In one embodiment, the time interval T6 from "end of the last digital data Y of the data signal D1" to "start of the first digital data Y of the next data signal D1" is added to meet the rising of the timing signal D2 The latching time points of the multiple analog driving signals Y′ corresponding to the edge W _R are no later than the rising edge W _{R of the} aforementioned timing signal D2.

In one embodiment, the time length of data BK in the horizontal scanning blanking period can be increased by reducing the number of data packets in the vertical blanking period. Increase the time interval T2 from "the last digital data Y received from the data interface circuit 100" to "the rising edge W _{R of the} timing signal D2", so increase the "end of the last digital data Y from the data signal D1" to "Next" The time interval T6 between the start of the first digital data Y of a data signal D1 to meet the rising edge W _{R of the} timing signal D2 The latching time point of the multiple analog drive signals Y'is no later than the aforementioned timing signal The rising edge of D2 W _R.

To sum up, according to the source driver and method of the present case, the digital analog is converted into a program first, and then the latch output program is executed, so that the signal is not delayed during the source driving process, thereby maintaining the display of the display device efficacy. According to some embodiments, this solution can avoid the situation in which the output time of each analog driving signal is inconsistent during the source driving process, and the output change rate of each analog driving signal voltage is different, thereby further improving the charging efficiency of the display panel.

10: Source driver

20: timing controller

100: data interface circuit

200: Displacement temporary storage circuit

300: data temporary storage circuit

400: Level shift circuit

500: Digital analog conversion circuit

700: Line latch circuit

800: output buffer circuit

D1: Data signal

D2: Timing signal

D3: Clock signal

Y: Digital data

Y’: analog drive signal

Claims (11)

A source driver includes: a digital-to-analog conversion circuit for receiving a data signal with a plurality of digital data and converting the digital data into a plurality of analog driving signals; and a line latch circuit coupled to the digital-to-analog conversion The circuit is used for latching the analog driving signals and outputting the analog driving signals according to a rising edge of a timing signal. The source driver according to claim 1, wherein the digital-to-analog conversion circuit and the line latch circuit are integrated into a conversion latch circuit. The source driver according to claim 2 further includes an output buffer circuit coupled to the conversion latch circuit for outputting the corresponding analog driving signals according to the falling edge of the timing signal. The source driver according to claim 1, further comprising an output buffer circuit, coupled to the line latch circuit, for outputting the analog driving signals according to the falling edge of the timing signal. The source driver according to claim 1, further comprising: a data interface circuit for processing the data signal and outputting a clock signal; and a data temporary storage circuit coupled to the data interface circuit and the digital analog conversion Between circuits, it is used to temporarily store the data signal according to the clock signal. The source driver according to any one of claims 1 to 5, wherein the time point of latching of the analog driving signals corresponding to the rising edge of the timing signal is no later than the rising edge of the timing signal. A source driving method includes: receiving a data signal with a plurality of digital data; Converting the digital data into a plurality of analog driving signals; and latching the analog driving signals according to a timing signal. The source driving method described in claim 7 further includes: buffering the analog driving signals after the latch; and outputting the buffered analog driving signals according to the timing signal. The source driving method according to claim 7 or 8, wherein the step of receiving the data signal with the digital data is based on the path length of the digital data from the data interface circuit to the line latch circuit to determine the The receiving order of digital data. For example, the source driving method of claim 7 or 8, further comprising: reducing the time interval between the beginning of the first digital data of the data signal and the end of the digital data of the data signal to satisfy the A rising edge of the timing signal corresponds to the latching time point of the analog driving signals not later than the rising edge of the timing signal. The source driving method described in claim 7 or 8, further comprising: increasing the time interval from the end of the digital data of the last data signal to the beginning of the first digital data of the next data signal to The latching time point of the analog driving signals corresponding to a rising edge of the timing signal is not later than the rising edge of the timing signal.

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