201025254 六、發明說明： 【發明所屬之技術領域】 本發明相關於一種液晶顯示裝置及其驅動方法，尤指一 種依據資料訊號之最大有效位元（Most Significant Bit， MSB)來控制電荷分享之液晶顯示裝置及其驅動方法。201025254 VI. Description of the Invention: [Technical Field] The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly to a liquid crystal for controlling charge sharing according to a Most Significant Bit (MSB) of a data signal. Display device and its driving method.
【先前技術】 由於液晶顯示器（liquid crystal display)具有低輻射、體 積小及低耗能等優點，已逐漸取代傳統的陰極射線管顯示器 (cathode ray tube display)，因而被廣泛地應用在筆記型電 腦、個人數位助理（personal digital assistant，PDA)、平面電 視，或行動電話等資訊產品上。 請參考第1圖，第1圖為先前技術中一液晶顯示器10 ® 之示意圖。液晶顯示器10包含一液晶顯示面板12、一時序 控制器（timing controller) 14、一源極驅動器（source driver)16，和一閘極驅動器（gate driver)18。液晶顯示面板 上設有複數條互相平行之資料線(data line)D丨-Dm、複數條互 相平行之閘極線(gate line)GrGn，以及複數個顯示單元 Pll_Pmn。資料線〇1-0„!和閘極線GpGn彼此交錯設置，而顯 示單元P i rPmn則分別設於相對應資料線和閘極線之交會 處。時序控制器14用來產生驅動液晶顯示面板12所需之控 201025254 制訊號和時脈訊號。源極驅動器16和閘極驅動器18依據時 序控制器14傳來之訊號分別產生相對應之資料訊號和閘極 訊號。液晶顯示面板12上之每個顯示單元皆包含有一薄膜 電晶體(thin film transistor，TFT)開關和一液晶電容，每一液 晶電容之一端透過一相對應之薄膜電晶體開關耦接於一相 對應之資料線，而另一端則耦接於一共同電壓VC()m。當收到 閘極驅動器18所產生之閘極訊號而開啟一顯示單元之薄膜 ❹ 電晶體開關時，此顯示單元之液晶電容會被電性連接至其相 對應之資料線以接收從源極驅動器16傳來之資料訊號，因 此顯示單元可依據其液晶電容内存之電荷來控制液晶分子 的旋轉程度，以顯示不同灰階之影像。 隨著大尺寸應用的需求不斷增加’液晶顯示器的面板尺 寸不斷變大，面板的負載也相應增加，動態功率消耗也會大 幅提昇，如何降低功率消耗也成為設計液晶顯示器時的重要 ® 課題。一般而言，施加在液晶電容兩端的電壓極性必須每隔 一預定時間進行反轉，以避免液晶材料產生極化 (polarization)而造成永久性的破壞，常見驅動液晶顯示面 板之方式包含點反轉（dot inversion)和線反轉（Hne inversion)等。當驅動液晶顯示面板的電壓極性開始反轉之 際，源極驅動器之電流消耗最大，故此時也是液晶顯示器負 載最大的時間。 201025254 於是有的液晶顯示器便使用電荷分享（charge sharing)的 方法來降低功率消耗，在源極驅動器輸出資料訊號之前，先 將電荷重新分配，藉此可以將消耗的動態電流節省一半。在 先前技術之液晶顯示器10中，源極驅動器160包含複數個 輸出緩衝器OB和複數個電荷分享開關CS，源極驅動器16 可透過輸出緩衝器OB將資料訊號傳至相對應之資料線，每 〇 一電荷分享開關CS則耦接於兩相鄰之資料線之間，透過開 啟電荷分享開關CS來達到電荷分享的效果。在先前技術之 液晶顯示器10中，無論輸入資料訊號的電位高低，在每一 寫入週期皆會在奇數條資料線和偶數條資料線之間執行電 荷分享，源極驅動器16可能會執行不必要的電荷分享，反 而因此而增加功率消耗。 _ 【發明内容】 ❿ 本發明提供一種依據資料訊號之最大有效位元來控制 電荷分享之液晶顯示裝置，其包含一第一資料線，用來接收 一第一輸出資料訊號；一相鄰該第一資料線之第二資料線， 用來接收一第二輸出資料訊號；以及一源極驅動電路，耦接 於該第一及第二資料線。該源極驅動電路包含一第一驅動模 組，用來依據一第一輸入資料訊號以產生相對應之該第一輸 出資料訊號，該第一驅動模組包含一第一移位暫存器，用來 201025254 接收-起始訊號及—時脈訊號，並依據該起始訊 訊號來產生一第一時脈控制訊號；-第一取樣"該時脈[Prior Art] Because liquid crystal display has the advantages of low radiation, small size and low energy consumption, it has gradually replaced the traditional cathode ray tube display, and thus is widely used in notebook computers. , personal digital assistant (PDA), flat-screen TV, or mobile phone and other information products. Please refer to FIG. 1 , which is a schematic diagram of a liquid crystal display 10 ® in the prior art. The liquid crystal display 10 includes a liquid crystal display panel 12, a timing controller 14, a source driver 16, and a gate driver 18. The liquid crystal display panel is provided with a plurality of data lines D丨-Dm parallel to each other, a plurality of gate lines GrGn which are parallel to each other, and a plurality of display units P11_Pmn. The data line 〇1-0„! and the gate line GpGn are alternately arranged with each other, and the display unit P i rPmn is respectively disposed at the intersection of the corresponding data line and the gate line. The timing controller 14 is used to generate the driving liquid crystal display panel. 12 required control 201025254 signal and clock signal. The source driver 16 and the gate driver 18 respectively generate corresponding data signals and gate signals according to the signals transmitted from the timing controller 14. Each of the liquid crystal display panels 12 Each of the display units includes a thin film transistor (TFT) switch and a liquid crystal capacitor, and one end of each liquid crystal capacitor is coupled to a corresponding data line through a corresponding thin film transistor switch, and the other end And coupled to a common voltage VC()m. When the gate signal generated by the gate driver 18 is received and the thin film ❹ transistor switch of a display unit is turned on, the liquid crystal capacitor of the display unit is electrically connected to The corresponding data line receives the data signal transmitted from the source driver 16, so that the display unit can control the rotation degree of the liquid crystal molecules according to the charge of the liquid crystal capacitor memory. Displaying images of different gray levels. As the demand for large-size applications continues to increase, the panel size of LCD displays continues to increase, the load on the panels increases, and the dynamic power consumption increases dramatically. How to reduce power consumption has also become a design for LCDs. The important issue of time. Generally speaking, the polarity of the voltage applied across the liquid crystal capacitor must be reversed every predetermined time to avoid permanent polarization of the liquid crystal material. Commonly used to drive the liquid crystal display panel. The method includes dot inversion and Hne inversion, etc. When the polarity of the voltage driving the liquid crystal display panel starts to reverse, the current consumption of the source driver is the largest, so the liquid crystal display has the largest load at this time. 201025254 So some LCD monitors use charge sharing to reduce power consumption. Before the source driver outputs the data signal, the charge is redistributed, which can save half of the consumed dynamic current. In the prior art liquid crystal display 10, the source The driver 160 includes a plurality of output buffers OB and a plurality of charge sharing switches CS. The source driver 16 can transmit the data signals to the corresponding data lines through the output buffer OB, and each of the charge sharing switches CS is coupled to the two. Between the adjacent data lines, the charge sharing effect is achieved by turning on the charge sharing switch CS. In the prior art liquid crystal display 10, regardless of the potential of the input data signal, an odd number of data is generated in each writing cycle. The charge sharing is performed between the line and the even data lines, and the source driver 16 may perform unnecessary charge sharing, thereby increasing power consumption. _ [Summary] The present invention provides a maximum effective bit according to the data signal. a liquid crystal display device for controlling charge sharing, comprising: a first data line for receiving a first output data signal; and a second data line adjacent to the first data line for receiving a second output data signal And a source driving circuit coupled to the first and second data lines. The source driving circuit includes a first driving module for generating a corresponding first output data signal according to a first input data signal, and the first driving module includes a first shift register. Used for the 201025254 receiving-starting signal and the clock signal, and generating a first clock control signal according to the initial signal signal; - the first sampling " the clock
該第-移位暫存器，用來接收該第一輸入資料訊：器，接 該第-時脈控制訊制鎖該第—輸人資料訊^ ’並依據 應之-第-取樣資料訊號；一第一輸出開關:=相對 關控制訊號以傳送該第—輸出資料訊號至該第依據-開 第-輸出開關包含一控制端，用來接收該開關控制：：，該 輸入端，耦接於該第一取樣保持器；以及一輪出唬，一 該第-資料線；-第二驅動模組，用來依據」第蠕’轉接於 訊號以產生相對應之-第二輸出資料訊號，:輪入資料 包含-第二移位暫存器’用來接收該起始訊號及:::模組 號，並依據該起始訊號及該時脈訊號來產生一第_吁脈Λ 訊號；一第二取樣保持器，耦接該第二移位暫存器用 收該第二輸入資料訊號，並依據該第二時脈控制訊號閂鎖該 第二輸入資料訊號以產生相對應之一第二取樣資料訊號；一 第二輸出開關’用來依據該開關控制訊號以傳送該第二輸出 資料訊號至該第二資料線’該第二輸出開關包含：一控制 端，用來接收該開關控制訊號；一輸入端，耦接於該第二取 樣保持器；以及一輸出端，耦接於該第二資料線；一開關控 制電路，耦接於該第一及第二取樣保持器，用來依據該第一 及第二取樣資料訊號之最大有效位元產生該開關控制訊 號；以及〆電荷分享開關’耗接該第—輸出開關之輸出端和 該第二輸出開關之輸出端之間，且依據該開關控制訊號來電 201025254 :連輪出開關之輸出端和該第二輸出開關之輸出 關之輸出端。 關之輪出心亥第二輸出開 制電，^另提供一種依據資料訊號之最大有效位元來控 m 顯示裝置’其包含-資料線，用來接收- ❹ =’用來依據一輸入資料訊號以產生相對應之該輸出 =㈣’該源極驅動電路包含—移位暫存器，用料t 並依據該起始訊號及該時脈訊號來 _收該;：：取:::二輕接該移位暫存器， == 取樣資料訊號，·-輸出開關， 訊號以傳送該輪出資料訊號至該資料 制端’用來接收該開關控制訊號; 資==該取樣保持器;以及一輪出端•該 貝枓線，一開關控制電路，減於該取樣保持器 ==最大ί效位元產生該開關控制訊號；-第電源用來k供一南電位操作電壓· • ’一第二雷满，用來 提供-低電位操作電麗；一第三電源，用來提供一:同電 墨；以及-電荷分享關，用來依據該開 ㈣ 出開關之輸出端電性連接至該第—電 將抑 該第二電源或該第 201025254 。本發明另提供一種依據資料錢之最大有效位元來控 制電何分享之源極驅動電路，包含一第一驅動模組，用來依 據。第輪入資料訊號產生相對應之一第一輸出資料訊號 ^驅動第-負載，該第一驅動模組包含一第一移位暫存 器’用來接收-起始訊號及—時脈訊號，並依據該起始訊號 及該時脈訊號產生一第一時脈控制訊號；一第一取樣保持 ❹器’麵接該第-移位暫存器’用來接收該第一輸入資料訊 號’並依據該第-時脈控制訊號閃鎖該第一輸人資料訊號以 產生相對應之—第—取樣資料訊號；-第〆輸出開關，用來 依據-開關控制訊號傳送該第一輸出資料訊號至該第一負 載，該第一輸出開關包含一控制端，用來接收該開關控制訊 號，一輸入端，耦接於該第一取樣保持器；以及一輸出端， 麵接於該第一負載；一第二驅動模組，用來依據一第二輸入 資料訊號產生相對應之一第二輸出資料訊號以驅動一第二 _ 負載’該第二驅動模組包含一第二移位暫存器，用來接收該 起始訊號及該時脈訊號，並依據該起始訊號及該時脈訊號產 生一第二時脈控制訊號；一第二取樣保持器，耦接該第二移 位暫存器’用來接收該第二輸入資料訊號，並依據該第二時 脈控制訊號閂鎖該第二輸入資料訊號以產生相對應之一第 二取樣資料訊號；一第二輸出開關，用來依據該開關控制訊 號傳送該第二輸出資料訊號至該第二負載，該第二輸出開關 包含一控制端’用來接收該開關控制訊號；一輸入端，耦接 201025254 於該第二取樣保持器；以及—輸出端 -開關控制電路，接於該第一及伴=二負載; 據該第-及第二取樣資料訊號之最大有效位元==依 出端和該第二輸出開關之 輪出開關之輪 訊號電性連接哕第來依據該開關控制 之輸出端開關之輸出端和該第二輸出開關 ❹ φ 輸出開關之輪疋出端。分離該第一輸出開關之輪出端和該第二 制電2用另提供一種依據資料訊號之最大有效位元來控 -龄之源極驅動電路，其包含―_模組，用來依據 輸貝枓職產生相對應之—輸Μ料訊號以驅動一負 驅動触包含—㈣暫存11，料接收-起始訊號及 ，、錢，並依獅起始訊號及該時脈訊絲產生一時脈 峨；—取樣保持器，補該移位暫存器，用來接收該 輸入資料訊號，並依據該時脈控制訊朗鎖該輸人資料訊號 、產生相對應之—取樣資料訊號；—輸出關，用來依據一 汗關控制訊號以傳送該輪出資料訊號至該資料線，該輸出開 哥匕3控制端，用來接收該開關控制訊號；一輸入端，輛 接於該取樣保持器；以及—輸出端，搞接於該資料線·一開 關控制電路，耦接於該取樣保持器，用來依據該取樣資料訊 號之最大有效位元產生該開關控制訊號；一第一電源，用 來提供而電位操作電壓；一第二電源，用來提供一低電位 201025254 操作電壓；一第三電源，用來提供一共同電壓；以及一電荷 分享開關，用來依據該開關控制訊號將該輸出開關之輸出端 電性連接至該第一電源、該第二電源或該第三電源。 本發明另提供一種依據資料訊號之最大有效位元來驅 動液晶顯示裝置之方法，其包含提供一起始訊號、一第一輸 入資料訊號和一第二輸入資料訊號；依據該第一輸入資料訊 I 號提供相對應之一第一輸出資料訊號；依據該第二輸入資料 訊號提供相對應之一第二輸出資料訊號；依據該起始訊號閂 鎖該第一及第二輸入資料訊號以分別產生相對應之一第一 取樣資料訊號和一第二取樣資料訊號；依據該第一及第二取 樣資料訊號之最大有效位元產生一開關控制訊號；一第一輸 出開關依據該開關控制訊號來控制該第一輸出資料訊號至 一液晶顯示裝置上一第一資料線之訊號傳送路徑；一第二輸 出開關依據該開關控制訊號來控制該第二輸出資料訊號至 ® 該液晶顯示裝置上一第二資料線之訊號傳送路徑；以及一電 荷分享開關依據該開關控制訊號來電性連接該第一輸出開 關之輸出端和該第二輸出開關之輸出端，或是電性分離該第 一輸出開關之輸出端和該第二輸出開關之輸出端。 本發明另提供一種依據資料訊號之最大有效位元來驅 動液晶顯示裝置之方法，其包含提供一起始訊號和一輸入資 料訊號；提供一高電位操作電壓、一低電位操作電壓，以及 201025254 一共同電壓；依據該輸入資料訊號提供相對應之一輸出資料 訊號；依據該起始訊號閃鎖該輸入資料訊號以產生相對應之 一取樣資料訊號；依據該取樣資料訊號之最大有效位元產生 一開關控制訊號；一輸出開關依據該開關控制訊號來控制該 輸出資料訊號至一液晶顯示裝置上一資料線之訊號傳送路 徑；以及一電荷分享開關依據該開關控制訊號將該輸出開關 之輸出端電性連接至該高電位操作電壓、該低電位操作電壓 義 或該共同電壓。 Ο 【實施方式】 請參考第2圖，第2圖為本發明中一液晶顯示器20之 示意圖。液晶顯示器20包含一液晶顯示面板22、一時序控 制器24、一源極驅動器26，和一閘極驅動器28。液晶顯示 面板22上設有複數條互相平行之資料線DrDm、複數條互 相平行之閘極線GrGn，以及複數個顯示單元PirPmn。資料 ® 線Di-Dm和閘極線GrGn彼此交錯設置，而顯示單元PirPmn 則分別設於相對應資料線和閘極線之交會處。時序控制器24 用來產生驅動液晶顯示面板22所需之控制訊號和時脈訊 號。源極驅動器26和閘極驅動器28依據時序控制器24傳 來之訊號分別產生相對應之閘極訊號和資料訊號。液晶顯示 面板22上之每個顯示單元皆包含有一薄膜電晶體開關和一 液晶電容，每一液晶電容之一端透過一相對應之薄膜電晶體 開關耦接於一相對應之資料線，而另一端則耦接於一共同電 11 201025254 壓VCQm。當收到閘極驅動器28所產生之閘極訊號而開啟一 顯示單元之薄膜電晶體開關時，此顯示單元之液晶電容會被 電性連接至其相對應之資料線以接收從源極驅動器26傳來 之資料訊號，因此顯示單元可依據其液晶電容内存之電荷來 控制液晶分子的旋轉程度’以顯示不同灰階之影像。 本發明之源極驅動器26包含第一驅動模組100、第二驅 φ 動模組200，以及一開關控制電路300。開關控制電路300 依據時序控制器24傳來之輸入資料訊號DIN_〇和D丨N E來產 生相對應之開關控制訊號SW。第一驅動模組100可依據輸 入資料訊號DIN_〇*開關控制訊號SW來產生驅動奇數條資 料線所需之輸出資料訊號D0UT 0,而第二驅動模組200可依 據輸入資料訊號DIN E和開關控制訊號SW來產生驅動偶數 條資料線所需之輸出資料訊號D OUT_E ° 請參考第3圖’第3圖為本發明第一實施例中源極驅動 器26之功能方塊圖。在此實施例中，源極驅動器26包含一 第一驅動模組100、一第二驅動模組200、一開關控制電路 300 ’以及一電荷分享開關90。第一驅動模組1 〇〇包含一移 位暫存器（Shift Register ) 3 卜一取樣保持（Sample & Hold ) 器41、一位準移位器（Level Shifter) 51、一數位類比轉換 器（Digital-to-Analog Converter，DAC) 61、一運算放大器 (0Perati〇nal Amplifier ) 71，以及一輸出開關8丨。第二驅動 12 201025254 模組200包含一移位暫存器32、一取樣保持器42 移位器52、-數位類比轉換器62、一運算放大器72，= 一輸讓82。源極驅動器26分別透過輸出開關81和82 來驅動奇數條和偶數條資料線，而電荷分享開關電路 麵接於奇數條和偶數條資料線。_控制電路3⑼之輸 搞接至取樣保持器41和42，輪出端_接至輸出開關81、 82及電荷分享開關90。 第一驅動模組議之移位暫存器31可依據時序控制器 所產生之時脈訊號SCLK矛口起始訊號sp來產生相對應之時 脈控制訊號seLK』。取樣保持^ 41减於移位暫存器^， 可依據時脈控制訊號seLK_。來對輸人資料訊號Din。進行取 樣，並產生相對應之取樣資料訊號dsho。位準移位器51耦 接於取樣保持器4卜可調整取樣資料訊號Dsh〇之電壓準 ❹位。數位類比轉換器61耦接於位準移位器51，可將取樣資 料訊號Dsh-〇轉換為一類比資料訊號DAnalog 0。運算放大器 71耦接於數位類比轉換器61，可放大類比資料訊號The first shift register is configured to receive the first input data message, and connect the first-infrared data control to the first-input data message and according to the -first-sampling data signal a first output switch: = relatively close control signal to transmit the first output signal to the first base - open first - output switch includes a control terminal for receiving the switch control::, the input end, coupled And the first sample holder; and one round of the output, the first data line; and the second driving module, for transmitting the signal according to the "first creep" to generate a corresponding - second output data signal, The rounding data includes a second shift register for receiving the start signal and the ::: module number, and generating a first signal according to the start signal and the clock signal; a second sample holder coupled to the second shift register for receiving the second input data signal, and latching the second input data signal according to the second clock control signal to generate a corresponding second Sampling data signal; a second output switch is used to control the signal according to the switch Sending the second output data signal to the second data line 'the second output switch includes: a control end for receiving the switch control signal; an input end coupled to the second sample holder; and an output The switch is coupled to the second data line; the switch control circuit is coupled to the first and second sample holders for generating the switch control according to the most significant bits of the first and second sampled data signals a signal; and a charge sharing switch consuming between the output of the first output switch and the output of the second output switch, and according to the switch control signal, call 201025254: the output of the serial switch and the second The output of the output switch is turned off. Guan Zhilun out of the second output of the Xinhai power supply, ^ also provides a maximum effective bit according to the data signal to control the m display device 'its contain - data line, used to receive - ❹ = ' used to input data The signal is generated to generate the corresponding output=(4) 'The source driving circuit includes a shift register, and the material t is used according to the start signal and the clock signal to receive the;;: take::: two Lightly connect the shift register, == sample data signal, ·- output switch, signal to transmit the round data signal to the data terminal 'to receive the switch control signal; capital == the sample holder; And a round of the exit • the Bellows line, a switch control circuit, minus the sample holder == maximum ί effect bit to generate the switch control signal; - the first power supply is used for a south potential operating voltage · • ' a second full, for providing - low potential operation; a third power supply for providing: a same ink; and - a charge sharing switch for electrically connecting to the output of the open (four) switch The first power will suppress the second power or the 201025254. The invention further provides a source driving circuit for controlling the sharing of electricity according to the most significant bit of the data money, comprising a first driving module for relying on. The first round of the data signal generates a corresponding one of the first output data signals to drive the first load, and the first driving module includes a first shift register for receiving the start signal and the clock signal. And generating a first clock control signal according to the start signal and the clock signal; a first sample hold buffer is connected to the first shift register to receive the first input data signal and The first input data signal is flashed according to the first clock control signal to generate a corresponding first-sampling data signal; and the third output switch is configured to transmit the first output data signal according to the -switch control signal to The first output switch includes a control terminal for receiving the switch control signal, an input end coupled to the first sample holder; and an output end coupled to the first load; a second driving module is configured to generate a second output data signal according to a second input data signal to drive a second _ load. The second driving module includes a second shift register. Used to receive the start signal And the clock signal, and generating a second clock control signal according to the start signal and the clock signal; a second sample holder coupled to the second shift register to receive the second Inputting a data signal, and latching the second input data signal according to the second clock control signal to generate a corresponding one of the second sample data signals; and a second output switch for transmitting the second according to the switch control signal Outputting a data signal to the second load, the second output switch includes a control terminal 'for receiving the switch control signal; an input terminal coupled to the second sample holder of 201025254; and an output terminal-switch control circuit Connected to the first and second = two loads; according to the first and second sampling data signals, the most significant bit == according to the output of the wheel and the second output switch of the wheel switch electrical connection The output end of the output switch controlled by the switch and the output end of the second output switch ❹ φ output switch. Separating the round output end of the first output switch and the second power supply 2 further provides a source driving circuit for controlling the age based on the most significant bit of the data signal, which includes a _ module for Bellow's job produces a corresponding signal—the feed signal is driven to drive a negative drive touch—(4) temporary storage 11, material receiving-starting signal and, money, and the lion start signal and the time signal generation a pulse holder; a sample holder, which is adapted to receive the input data signal, and according to the clock control, locks the input data signal, generates a corresponding-sampling data signal; Off, used to transmit the rounding data signal to the data line according to a sweat control signal, the output is connected to the control terminal for receiving the switch control signal; and an input terminal is connected to the sample holder And the output terminal is connected to the data line and a switch control circuit coupled to the sample holder for generating the switch control signal according to the most significant bit of the sampled data signal; Come to provide potential operation a voltage; a second power supply for providing a low potential 201025254 operating voltage; a third power supply for providing a common voltage; and a charge sharing switch for outputting the output switch based on the switch control signal Electrically connected to the first power source, the second power source, or the third power source. The present invention further provides a method for driving a liquid crystal display device according to a maximum effective bit of a data signal, comprising: providing a start signal, a first input data signal, and a second input data signal; Providing a corresponding one of the first output data signals; providing a corresponding one of the second output data signals according to the second input data signal; latching the first and second input data signals according to the start signal to respectively generate phases Corresponding to one of the first sampled data signal and the second sampled data signal; generating a switch control signal according to the most significant bit of the first and second sampled data signals; and the first output switch controls the switch according to the switch control signal a first output data signal to a signal transmission path of a first data line on a liquid crystal display device; a second output switch controls the second output data signal to a second data of the liquid crystal display device according to the switch control signal a signal transmission path of the line; and a charge sharing switch electrically connecting the first according to the switch control signal Output of the switch and the output terminal of the second output terminal of the output switch or output terminal is electrically isolated from the first output switch and the output terminal of the second output of the switch. The invention further provides a method for driving a liquid crystal display device according to a maximum effective bit of a data signal, which comprises providing a start signal and an input data signal; providing a high potential operating voltage, a low potential operating voltage, and 201025254 a voltage; providing a corresponding one of the output data signals according to the input data signal; flashing the input data signal according to the start signal to generate a corresponding one of the sampled data signals; generating a switch according to the most significant bit of the sampled data signal a control signal; an output switch controls the output data signal to a signal transmission path of a data line on the liquid crystal display device according to the switch control signal; and a charge sharing switch outputs the output end of the output switch according to the switch control signal Connected to the high potential operating voltage, the low potential operating voltage sense or the common voltage.实施 [Embodiment] Please refer to FIG. 2, which is a schematic view of a liquid crystal display 20 of the present invention. The liquid crystal display 20 includes a liquid crystal display panel 22, a timing controller 24, a source driver 26, and a gate driver 28. The liquid crystal display panel 22 is provided with a plurality of mutually parallel data lines DrDm, a plurality of mutually parallel gate lines GrGn, and a plurality of display units PirPmn. The data ® line Di-Dm and the gate line GrGn are alternately arranged, and the display unit PirPmn is respectively disposed at the intersection of the corresponding data line and the gate line. The timing controller 24 is used to generate control signals and clock signals required to drive the liquid crystal display panel 22. The source driver 26 and the gate driver 28 respectively generate corresponding gate signals and data signals according to the signals transmitted from the timing controller 24. Each of the display units on the liquid crystal display panel 22 includes a thin film transistor switch and a liquid crystal capacitor. One end of each liquid crystal capacitor is coupled to a corresponding data line through a corresponding thin film transistor switch, and the other end is connected to the other end. Then coupled to a common power 11 201025254 pressure VCQm. When the gate transistor signal generated by the gate driver 28 is received to turn on the thin film transistor switch of the display unit, the liquid crystal capacitor of the display unit is electrically connected to the corresponding data line to receive the slave source driver 26 The information signal is transmitted, so the display unit can control the degree of rotation of the liquid crystal molecules according to the charge of the liquid crystal capacitor memory to display images of different gray levels. The source driver 26 of the present invention comprises a first driving module 100, a second driving module 200, and a switching control circuit 300. The switch control circuit 300 generates a corresponding switch control signal SW based on the input data signals DIN_〇 and D丨N E from the timing controller 24. The first driving module 100 can generate an output data signal D0UT 0 required to drive an odd number of data lines according to the input data signal DIN_〇* switch control signal SW, and the second driving module 200 can be based on the input data signal DIN E and The switch control signal SW is used to generate an output data signal D OUT_E ° required to drive an even number of data lines. Please refer to FIG. 3, which is a functional block diagram of the source driver 26 in the first embodiment of the present invention. In this embodiment, the source driver 26 includes a first driving module 100, a second driving module 200, a switch control circuit 300', and a charge sharing switch 90. The first driving module 1 〇〇 includes a shift register (Shift Register) 3 a sample hold (Sample & Hold) 41, a level shifter (Level Shifter) 51, a digital analog converter (Digital-to-Analog Converter, DAC) 61, an operational amplifier (0Perati〇nal Amplifier) 71, and an output switch 8丨. The second driver 12 201025254 The module 200 includes a shift register 32, a sample holder 42 shifter 52, a digital analog converter 62, an operational amplifier 72, and an input 82. The source driver 26 drives the odd and even data lines through the output switches 81 and 82, respectively, and the charge sharing switch circuit is connected to the odd and even data lines. The input of the control circuit 3 (9) is connected to the sample holders 41 and 42, and the wheel terminal _ is connected to the output switches 81, 82 and the charge sharing switch 90. The first drive module of the shift register 31 can generate a corresponding clock control signal seLK according to the clock signal SCLK edge start signal sp generated by the timing controller. The sample hold ^ 41 is reduced to the shift register ^, and can be controlled according to the clock control signal seLK_. Come to the input information signal Din. Sampling is performed and a corresponding sampling data signal dsho is generated. The level shifter 51 is coupled to the sample holder 4 to adjust the voltage reference position of the sampled data signal Dsh. The digital analog converter 61 is coupled to the level shifter 51 to convert the sampled signal Dsh-〇 into an analog data signal DAnalog 0. The operational amplifier 71 is coupled to the digital analog converter 61 to amplify the analog data signal
Analog_0 並產生相對應之輸出資料訊號DOUT O。輸出開關81耦接於 運算放大器71和開關控制電路300，可依據開關控制訊號 sw來運作，當開關控制訊號sw開啟（短路）輸出開關81 時’第一驅動模組10〇可將輸出資料訊號D〇UT〇傳送至奇數 條資料線。 13 201025254 同理，第二驅動模組200之移位暫存器32可依據時序 控制器所產生之時脈訊號SCLK和起始訊號sp來產生相對 應之時脈控制訊號ScLK E。取樣保持器42可依據時脈控制 訊號SCLK_E來對輸入資料訊號！^進行取樣，並產生相對 應之取樣資料訊號Dsh_e。位準移仇器52搞接於取樣保持器 42 ’可調整取樣資料訊號Dshe之電壓準位。數位類比轉換 器62耗接於位準移位器52，可將取樣資料訊號轉換 ❹為一類比資料訊號DAnal〇g_E。運算放大器72城於數位類比 轉^器62 ’可放大類比㈣訊號D-ne並產生相對應之輸 出資料訊號D〇ut_e。輸出開關82耦接於運算放大器72和開 關控制電路300，可依據開關控制訊號sw來運作，當開關 控制訊號sw開啟（短路）輸出開關82時，第二驅動模組 2〇〇 了將輸出負料讯號d〇ut e傳送至偶數條資料線。 _ 在接收到取樣資料訊號Dsh 〇和取樣資料訊號Dsh eAnalog_0 and generate the corresponding output data signal DOUT O. The output switch 81 is coupled to the operational amplifier 71 and the switch control circuit 300, and can be operated according to the switch control signal sw. When the switch control signal sw is turned on (short-circuit) the output switch 81, the first drive module 10 can output the data signal. D〇UT〇 is transferred to an odd number of data lines. 13 201025254 Similarly, the shift register 32 of the second driving module 200 can generate the corresponding clock control signal ScLK E according to the clock signal SCLK and the start signal sp generated by the timing controller. The sample holder 42 can input the data signal according to the clock control signal SCLK_E! ^ Sampling is performed and a corresponding sampling data signal Dsh_e is generated. The level shifter 52 is connected to the sample holder 42' to adjust the voltage level of the sampled data signal Dshe. The digital analog converter 62 is consuming the level shifter 52 to convert the sampled data signal into an analog data signal DAnal〇g_E. The operational amplifier 72 is in the digital analog converter 62' to amplify the analog (4) signal D-ne and generate a corresponding output data signal D〇ut_e. The output switch 82 is coupled to the operational amplifier 72 and the switch control circuit 300, and can be operated according to the switch control signal sw. When the switch control signal sw is turned on (short-circuit) the output switch 82, the second drive module 2 outputs a negative output. The signal signal d〇ut e is transmitted to an even number of data lines. _ Receiving sampled data signal Dsh 〇 and sampling data signal Dsh e
後，開關控制電路300會依據取樣資料訊號Dsh 〇和取樣資 料訊號Dsh-e之最大有效位元（Most Significant Bit，MSB) 來產生相對應之開關控制訊號sw。請參考第4圖，第4 圖為本發明一實施例中開關控制電路300之功能方塊圖。在 此實施例中’開關控制電路300包含MSB閂鎖器281和 282、D 型正反器（D_typeFlipF1〇p)29i 和 292、一或閘（〇RThen, the switch control circuit 300 generates a corresponding switch control signal sw according to the sample data signal Dsh and the Most Significant Bit (MSB) of the sample data signal Dsh-e. Please refer to FIG. 4, which is a functional block diagram of the switch control circuit 300 according to an embodiment of the present invention. In this embodiment, the switch control circuit 300 includes MSB latches 281 and 282, D-type flip-flops (D_typeFlipF1〇p) 29i and 292, and a gate (〇R).
Gate) 270，以及一移位暫存器3〇。msb閂鎖器281和282 为別耦接於取樣保持器41和42之輸出端，可分別求出取樣 14 201025254 資料訊號Dsh o之最大有效位元MSB_o和取樣資料訊號 Dsh—ε之最大有效位元MSB_e。D型正反器291和292為負 緣觸發之正反器，其觸發端CLK分別耦接於MSB閂鎖器281 和282 ’輸出端Q耦接於或閘270，而重置端rSt可接收重 置訊號STB。當MSB一〇由”1”變為，，〇，，時，D型正反器291 之輸出端Q會輸出訊號”1” ；當MSB_e由’，1”變為，，〇，，時，D 型正反器292之輸出端Q會輸出訊號” Γ，。位準移位器3〇 ❹ 耦接於或閘270,可調整控制訊號SW之電壓準位。當MSB 〇 或MSB—e其中之一由”1”變為，，〇，，時，或閘27〇輸出之控制訊 號SW會關閉輸出開關和開啟電荷分享開關，此時源極驅動 器26會關閉輸出，並在重置訊號STB具高電位的期間執行 電荷分享；當MSB_o或MSB_e其中之一由，，〇，’變為”r，時， 或閘270輸出之控制訊號Sw會關閉輸出開關和關閉電荷分 享開關，此時源極驅動器26會關閉輸出，但並不會執行電 ©荷分享。 請參考第5 ®，第5圖為本發明第—實施例之源極驅動 器％在電荷分享時之時序i在第5圖巾，Wstb代表重置 »代號STB之波形，WMSB代表最大有效位力MSB_。或最大有 Mtg MSB_em DIN。和Din e分別代表奇數筆和 數筆輸入資料訊號之波形，d〇ut—〇,和d〇ut e，分別代表 行電荷分享時奇數筆和偶數筆輸出資料訊號之波形，而 ‘ dgut。和Dqute分別代表本㈣巾奇數筆和偶數筆輪出資 15 201025254 料訊號之波形。在時間點Τ2、T4…時，具正極性之奇數筆 輸入資料訊號DIN 0由高電位降至低電位，具負極性之偶數 筆輸入資料訊號Din_e由低電位升至南電位，因此最大有效 位元MSB_o和最大有效位元MSB_e皆會由1變到0，此時 本發明會在重置訊號STB具高電位的期間執行電荷分享，將 波形 W〇UT_0 和波形 W〇uT_E 提前拉至目標準位。在時間點 ΤΙ、T3、T5."時，具正極性之奇數筆輸入資料訊號DIN 0由 φ 低電位升至高電位，具負極性之偶數筆輸入資料訊號Dine 由高電位降至低電位，因此最大有效位元MSB_o和最大有 效位元MSB_e皆會由0變到1，此時本發明並不會執行多餘 的電荷分享，因此能達到省電目的。 請參考第6圖，第6圖為本發明第二實施例中源極驅動 器26之功能方塊圖。在此實施例中，源極驅動器26包含一 驅動模組15 、一開關控制電路68、一電荷分享開關93，以 胃及一電源供應電路95。驅動模組15包含一移位暫存器33、 一取樣保持器43、一位準移位器53、一數位類比轉換器63、 一運算放大器73，以及一輸出開關83。開關控制電路68之 輸入端耦接至取樣保持器43，輸出端則耦接至輸出開關83 及電荷分享開關93。源極驅動器26透過輸出開關83來驅動 資料線，而電荷分享開關電路93則耦接於資料線和電源供 應電路95之間。電源供應電路95可提供不同操作電壓，例 如具尚電位之V〇d、具低電位之V(jnd ’以及共同電壓Vcom。 16 201025254 驅動模組15之移位暫存器33可依據時序控制器所產生 之時脈訊號和起始訊號來產生相對應之時脈控制訊號 。取樣 保持器43祕於移位暫存器33，可依據時脈控制訊號來對 輸入資料訊號進行取樣’並產生相對應之取樣資料訊號。位 準移位器53摘接於取樣保持器43，可調整取樣資料訊號之 電壓準位。數位類比轉換器63耦接於位準移位器53，可將 ❿取樣資料訊號轉換為類比資料訊號。運算放大器73耦接於 數位類比轉換器63,可放大類比資料訊號並產生相對應之輪 出資料訊號。同時，在接收到取樣資料訊號後，開關控制電 路68會依據取樣資料訊號最大有效位元來產生相對應之開 關控制訊號SW。輸出開關83耦接於運算放大器73和開關 控制電路68，可依據開關控制訊號sw來運作，當開關控制 訊號SW開啟（短路）輸出開關83時，驅動模組15可將輪 ❹出資料訊號傳送至資料線。電荷分享開關93耦接於資料線4 和電源供應電路95之間，可依據開關控制訊號sw來運作， 當開關控制訊號sw開啟電荷分享開關時，資料線會麵 接至電源供應電路95所提供相對應之驅動電壓以執行電荷 分享。 請參考第7圖，第7圖為本發明第二實施例之源極驅動 器26在電荷分享時之時序圖。在第7圖中，wSTB代表重置 訊號STB之波形’ DIN_0* Din e分別代表奇數筆和偶數筆 17 201025254 輸入資料訊號之波形，wMSB 0代表奇數筆輸入資料訊號 Din o之最大有效位元MSB—〇的波形，wMSB—E代表偶數筆 輸入資料訊號DIN E之最大有效位元MSB_e的波形， DOUT O’和D〇ut_e’分別代表未執行電荷分享時奇數筆和偶數 筆輸出資料訊號之波形’而D0UT—〇和dout e分別代表本發 明中奇數筆和偶數筆輸出資料訊號之波形。在時間點T1、 T3、T5…時，具正極性之奇數筆輸入資料訊號Din—〇和具負 馨極性之偶數筆輸入資料訊號Din_e皆由低電位升至高電位， 因此最大有效位元MSB一〇會由〇變到1，而最大有效位元 MSB_e會由1變到〇,此時本發明會在重置訊號STB具高電 位的期間執行電荷分享，將奇數條資料線透過電荷分享開關 93耦接至電源供應電路76之電源VDD，將偶數條資料線透 過電荷分享開關93耦接至電源供應電路76之電源Vcom， 因此能將波形WOUTO和波形W0UTE提前拉至目標準位。在 _ 時間點T2、T4...時，具正極性之奇數筆輸入資料訊號Din_〇 和具負極性之偶數筆輸入資料訊號Dine皆由高電位降至低 電位，因此最大有效位元MSB_o會由1變到〇,而最大有效 位元MSB—e會由〇變到1，此時本發明會在重置訊號STB 具高電位的期間執行電荷分享，將奇數條資料線透過電荷分 享開關93耦接至電源供應電路76之電源vcom，將偶數條 資料線透過電荷分享開關93耦接至電源供應電路76之電源 VGND，因此能將波形wOUTO和波形W0UTE提前拉至目標準 位。 201025254 本發明之液晶顯示器能依據資料訊號之MSB變化來控 制電荷分享，透過開關控制電路來產生相對應之開關控制訊 號SW，因此可以避免多餘的電荷分享，減少源極驅動電路 的消耗電流，並降低熱能發散。 以上所述僅為本發明之較佳實施例，凡依本發明申請專 利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 ❹ 【圖式簡單說明】 第1圖為先前技術中一液晶顯示器之示意圖。 第2圖為本發明中一液晶顯示器之示意圖。 第3圖為本發明第一實施例中源極驅動器之功能方塊圖。 第4圖為本發明一實施例中開關控制電路之功能方塊圖。 第5圖為本發明第一實施例之源極驅動器在電荷分享時之時 G 序圖。 第6圖為本發明第二實施例中源極驅動器之功能方塊圖。 第7圖為本發明第二實施例之源極驅動器在電荷分享時之時 序圖。 【主要元件符號說明】 10、20 液晶顯示器 12、22 液晶顯示面板 14、24 時序控制器 16、26 源極驅動器 19 201025254 18、28 閘極驅動器 270 或閘 30 〜33 移位暫存器 41 〜43 取樣保持器 51 〜53 位準移位器 61 〜63 DAC 71 〜73 運算放大器 81 〜83 輸出開關 Di_Dm 資料線 〇!-〇η 閘極線 P ll_Pmn 顯示單元 OB 輸出緩衝器 95 電源供應電路 281 ' 282 MSB閂鎖器 291 292 D型正反器 68、300 開關控制電路 90 ' 93 ' CS 電荷分享開關 15 、 100 ， * 200 驅動模組Gate) 270, and a shift register 3〇. The msb latches 281 and 282 are coupled to the outputs of the sample holders 41 and 42 respectively, and the maximum effective bits of the sample 14 201025254 data signal Dsh o and the most significant bit of the sample data signal Dsh_ε can be respectively determined. Meta MSB_e. The D-type flip-flops 291 and 292 are negative-triggered flip-flops, and the trigger terminals CLK are coupled to the MSB latches 281 and 282 respectively. The output terminal Q is coupled to the OR gate 270, and the reset terminal rSt is receivable. Reset signal STB. When the MSB changes from "1" to "1", the output terminal Q of the D-type flip-flop 291 outputs a signal "1"; when MSB_e changes from ', 1" to, 〇,,, The output terminal Q of the D-type flip-flop 292 outputs a signal "Γ,. The level shifter 3〇 is coupled to the OR gate 270 to adjust the voltage level of the control signal SW. When one of the MSB 〇 or MSB_e is changed from "1" to ",", 〇, ,, or 闸 27 〇 output control signal SW turns off the output switch and turns on the charge sharing switch, at which time the source driver 26 turns off. Output, and perform charge sharing during reset signal STB with high potential; when one of MSB_o or MSB_e is changed from ,, 〇, 'to' r, control signal Sw output from gate 270 will turn off output switch and When the charge sharing switch is turned off, the source driver 26 will turn off the output, but will not perform the charge sharing. Please refer to the 5th, 5th, the source driver % of the first embodiment of the present invention during charge sharing. The timing i is in the 5th towel, Wstb represents the waveform of the reset»code STB, WMSB represents the maximum effective potential MSB_. or the maximum has Mtg MSB_em DIN. And Din e represents the waveform of the odd and several input data signals, respectively. D〇ut-〇, and d〇ut e, respectively represent the waveforms of the odd-numbered pen and even-numbered pen output data signals during line charge sharing, while 'dgut. and Dqute respectively represent the (4) towel odd-number pen and even-number pen wheel funding 15 201025254 Signal waveform At the time point Τ2, T4..., the odd-numbered input data signal DIN 0 with positive polarity drops from high potential to low potential, and the even-numbered input signal signal Din_e with negative polarity rises from low potential to south potential, so the most significant bit Both the MSB_o and the most significant bit MSB_e will change from 1 to 0. At this time, the present invention performs charge sharing while the reset signal STB has a high potential, and pulls the waveform W〇UT_0 and the waveform W〇uT_E to the target standard in advance. In the time point ΤΙ, T3, T5.", the odd-numbered input data signal DIN 0 with positive polarity rises from φ low potential to high potential, and the even-numbered input signal signal Dine from negative polarity decreases from high potential to low. The potential, therefore, the most significant bit MSB_o and the most significant bit MSB_e will change from 0 to 1. At this time, the present invention does not perform redundant charge sharing, thereby achieving power saving purposes. Please refer to Figure 6, page 6. The figure is a functional block diagram of the source driver 26 in the second embodiment of the present invention. In this embodiment, the source driver 26 includes a driving module 15, a switch control circuit 68, and a charge sharing switch 93 for the stomach and a power supply The circuit module 95 includes a shift register 33, a sample holder 43, a bit shifter 53, a digital analog converter 63, an operational amplifier 73, and an output switch 83. The input end of the control circuit 68 is coupled to the sample holder 43 and the output end is coupled to the output switch 83 and the charge sharing switch 93. The source driver 26 drives the data line through the output switch 83, and the charge sharing switch circuit 93 is coupled. Connected between the data line and the power supply circuit 95. The power supply circuit 95 can provide different operating voltages, such as V 〇 d with a potential, V (jnd ' with a low potential, and a common voltage Vcom. 16 201025254 The shift register 33 of the drive module 15 can generate a corresponding clock control signal according to the clock signal and the start signal generated by the timing controller. The sample holder 43 is secreted by the shift register 33 to sample the input data signal according to the clock control signal and generate a corresponding sample data signal. The level shifter 53 is spliced to the sample holder 43 to adjust the voltage level of the sampled data signal. The digital analog converter 63 is coupled to the level shifter 53 for converting the sampled data signal into an analog data signal. The operational amplifier 73 is coupled to the digital analog converter 63 to amplify the analog data signal and generate a corresponding wheel data signal. At the same time, after receiving the sampled data signal, the switch control circuit 68 generates a corresponding switch control signal SW according to the most significant bit of the sampled data signal. The output switch 83 is coupled to the operational amplifier 73 and the switch control circuit 68, and can be operated according to the switch control signal sw. When the switch control signal SW is turned on (short-circuited) the output switch 83, the drive module 15 can transmit the data signal from the wheel. To the data line. The charge sharing switch 93 is coupled between the data line 4 and the power supply circuit 95, and can be operated according to the switch control signal sw. When the switch control signal sw turns on the charge sharing switch, the data line is connected to the power supply circuit 95. Corresponding driving voltages are performed to perform charge sharing. Please refer to FIG. 7. FIG. 7 is a timing chart of the source driver 26 in the charge sharing mode according to the second embodiment of the present invention. In Fig. 7, wSTB represents the waveform of the reset signal STB 'DIN_0* Din e represents the waveform of the odd and even pen 17 201025254 input data signals respectively, and wMSB 0 represents the most significant bit MSB of the odd input data signal Din o —〇 waveform, wMSB—E represents the waveform of the MSB_e of the even-numbered input data signal DIN E, and DOUT O′ and D〇ut_e′ represent the waveforms of the odd-numbered and even-numbered output data signals when the charge sharing is not performed, respectively. 'And D0UT-〇 and dout e respectively represent the waveforms of the odd-numbered pen and even-numbered pen output data signals in the present invention. At the time points T1, T3, T5..., the odd-numbered input data signal Din_〇 with positive polarity and the even-numbered input data signal Din_e with negative polarity are raised from low potential to high potential, so the most significant bit MSB 〇 will change from 〇 to 1, and the most significant bit MSB_e will change from 1 to 〇. At this time, the present invention performs charge sharing during the period when the reset signal STB has a high potential, and the odd data lines are transmitted through the charge sharing switch 93. The power supply VDD coupled to the power supply circuit 76 couples the even data lines to the power supply Vcom of the power supply circuit 76 through the charge sharing switch 93, so that the waveform WOUTO and the waveform WUUTE can be pulled to the target standard in advance. At the time point T2, T4..., the odd-numbered input data signal Din_〇 with positive polarity and the even-numbered input data signal Dine with negative polarity are reduced from high potential to low potential, so the most significant bit MSB_o It will change from 1 to 〇, and the most significant bit MSB-e will change from 〇 to 1. At this time, the present invention performs charge sharing during the reset signal STB with a high potential, and transmits an odd number of data lines through the charge sharing switch. The power supply vcom coupled to the power supply circuit 76 couples the even data lines to the power supply VGND of the power supply circuit 76 through the charge sharing switch 93, so that the waveform wOUTO and the waveform WOUTE can be pulled to the target standard in advance. 201025254 The liquid crystal display of the invention can control the charge sharing according to the MSB change of the data signal, and generates the corresponding switch control signal SW through the switch control circuit, thereby avoiding unnecessary charge sharing and reducing the current consumption of the source driving circuit, and Reduce heat dissipation. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the patent scope of the present invention are intended to be within the scope of the present invention. ❹ [Simple description of the drawing] Fig. 1 is a schematic view of a liquid crystal display in the prior art. Figure 2 is a schematic view of a liquid crystal display of the present invention. Fig. 3 is a functional block diagram of a source driver in the first embodiment of the present invention. Figure 4 is a functional block diagram of a switch control circuit in accordance with an embodiment of the present invention. Fig. 5 is a timing chart of the source driver of the first embodiment of the present invention at the time of charge sharing. Figure 6 is a functional block diagram of a source driver in a second embodiment of the present invention. Figure 7 is a timing chart of the source driver of the second embodiment of the present invention during charge sharing. [Main component symbol description] 10, 20 Liquid crystal display 12, 22 Liquid crystal display panel 14, 24 Timing controller 16, 26 Source driver 19 201025254 18, 28 Gate driver 270 or gate 30 to 33 Shift register 41 ~ 43 Sample Holder 51 to 53 Level Shifter 61 to 63 DAC 71 to 73 Operational Amplifier 81 to 83 Output Switch Di_Dm Data Line 〇!-〇η Gate Line P ll_Pmn Display Unit OB Output Buffer 95 Power Supply Circuit 281 ' 282 MSB latch 291 292 D-type flip-flop 68, 300 switch control circuit 90 ' 93 ' CS charge-sharing switch 15, 100, * 200 drive module
2020