TWI528518B - Substrate structure and semiconductor package - Google Patents

Description

Substrate structure and semiconductor package

The present invention relates to a substrate structure and a semiconductor package, and more particularly to a substrate structure and a semiconductor package using a bumper wire direct connection (BOT) technology of a flip chip package.

As the design of electronic products is increasingly moving toward thin, short, versatile and high-frequency performance, circuit boards or package substrates must also be developed in the direction of fine line/fine pitch. At the same time, since the number of pins of the flip-chip semiconductor package is much larger than the number of pins of the wire-type semiconductor package, the flip-chip semiconductor package is gradually replaced by the flip-chip semiconductor package.

FIG. 1 is a schematic plan view showing a flip chip package substrate of one of the prior art. As shown, the package substrate 1 includes a substrate body 10, a plurality of lines 11 and a solder resist layer 12. The wires 11 are formed on the substrate body 10 and have electrical contacts 111 formed at the ends of the wires 11 for connecting external electronic components (such as semiconductor wafers). The solder resist layer 12 is provided. Formed on the surface of the substrate body 10 to cover the lines 11 and expose the electrical contacts 111.

Since the electrical contacts 111 are located at the ends of the lines 11 and the size of the electrical contacts 111 is larger than the size of the lines 11, the wiring density of the lines 11 is often limited by the The size of the electrical contacts 111 is not sufficient to make a thin line width/fine line pitch product. Therefore, in the case where the package substrate 1 has a fixed area, the wiring density of the lines 11 cannot be increased, thereby causing subsequent fabrication of the semiconductor package. The performance of the piece is limited. In order to solve these problems, the industry has developed a flip-chip package substrate using bump-on-trace (BOT) technology, as shown in FIG.

2 is a perspective view showing another flip chip package substrate of the prior art. As shown, the package substrate 2 includes a substrate body 20, a plurality of lines 21, and a plurality of solder balls 22. The circuit 21 is formed on the substrate body 20, and the circuit 21 has a top surface 211 and at least one electrical contact 212 on the top surface 211. The solder ball 22 is formed on the top surface 211. Sexual contact 212. Since the ends of the lines 21 do not need to be provided with the electrical contacts 111 as shown in FIG. 1, the wiring density of the lines 21 is less limited by the size of the electrical contacts, and the number of the lines can be increased. The number of solder balls 22 on line 21.

However, when a semiconductor wafer and a primer are to be formed on the package substrate 2 to fabricate a semiconductor package, and the semiconductor package is subjected to a reliability test, a short circuit may occur between the adjacent two lines 21, such as Figures 3A and 3B show.

3A and 3B are cross-sectional views showing a flip-chip semiconductor package of one of the prior art.

As shown in FIG. 3A, the semiconductor package 3 includes a substrate body 31, two adjacent lines 32, conductive bumps 33, a semiconductor wafer 34, and a primer 35. The two lines 32 are formed on the substrate body 31. The conductive bumps 33 are formed between the top surface 321 of the line 32 and the electrode pads 341 of the semiconductor wafer 34. The primer 35 is formed on the substrate body. 31 is between the semiconductor wafer 34.

Since the solder resist layer 12 as shown in FIG. 1 is not formed on the substrate body 31, and the surface of the substrate body 31 is not very flat, the distance between the two lines 32 is usually small, so that the two lines are The bottom adhesive 35 of the 32 layers cannot be completely adhered to the substrate body 31, so that a gap 351 is formed between the two lines 32.

As shown in FIG. 3B, when the semiconductor package 3 is subjected to, for example, a reliability test, a current applied to the semiconductor package 3 generates heat energy through the two lines 32, and the heat energy melts the portions. The conductive material (such as copper) 352 of the line (such as copper wire) 32 overflows, and the overflow conductive material 352 is formed in the gap 351, thereby causing the two wires 32 to be electrically connected to each other to cause a short circuit.

Therefore, how to overcome the problems of the above-mentioned prior art has become a problem that is currently being solved.

The object of the present invention is to provide a substrate structure and a semiconductor package, which adopts a bumper wire direct connection (BOT) technology of a flip chip package, and can avoid a situation in which two adjacent lines are electrically connected to each other to generate a short circuit.

The present invention provides a substrate structure including: a substrate body, a system Having an opposite first surface and a second surface; respectively formed on the first surface and the second line on the first surface of the substrate body, and the first line and the second line are both electrically connected a top surface of the component; and an isolation structure formed on the first surface of the substrate body and located between the first line and the second line to electrically isolate the first line from the second line Two lines.

The present invention also provides a semiconductor package comprising: a substrate body having opposite first and second surfaces; adjacent first and second lines respectively formed on the first surface of the substrate body, And the first line and the second line each have a top surface; the insulating structure is formed on the first surface of the substrate body and located between the first line and the second line to electrically isolate the structure Isolating the first line and the second line; at least one first conductive bump is formed on a top surface of the first line; at least one second conductive bump is formed on a top surface of the second line And the electronic component is disposed on the first conductive bump and the second conductive bump, and electrically connected to the first line and the second line respectively.

In the above substrate structure and semiconductor package, the isolation structure may be formed by at least one protrusion, and the protrusion is integrally formed with the substrate body or separately formed. The material of the protrusion may be an insulating material, and the height of the protrusion may be smaller than the height of the first line or the height of the second line.

In the above substrate structure and semiconductor package, the isolation structure may be formed by at least one recess, and the recess extends from the first surface of the substrate body to the inside of the substrate body.

In the above semiconductor package, the electronic component may be a semiconductor wafer or a wafer and is flip-chip bonded to the top surface of the first line and the top surface of the second line.

In the above semiconductor package, the electronic component may have an active surface and a first electrode pad and a second electrode pad respectively formed on the active surface, and the first conductive bump may be formed on a top surface of the first line The second conductive bump may be formed between the top surface of the second line and the second electrode pad.

The semiconductor package may include a primer formed between the first surface of the substrate body and the electronic component to encapsulate the first line, the second line, the isolation structure, the first conductive bump, and the second a conductive bump, and the primer can cover the protrusion of the insulating structure or fill the recess of the insulating structure.

As can be seen from the above, in the substrate structure and the semiconductor package of the present invention, the bump wire direct connection (BOT) technology of the flip chip package is mainly used, and the conductive bumps are respectively formed on the top surfaces of the adjacent two lines, and An insulating structure having protrusions or depressions is formed between the two lines.

Therefore, compared with the first embodiment of the prior art, the substrate structure of the present invention can omit the solder resist layer shown in FIG. 1 to form a substrate structure with a fine line width/fine line pitch, and reduce the process and cost of the substrate structure. And increase the number of conductive bumps on the line.

Furthermore, the isolation structure of the semiconductor package of the present invention can be interposed between the formation of the electronic component and the primer after performing the reliability test, for example, in the drawings of FIGS. 2 to 3B of the prior art. Between the two lines, And the two lines are separated or shunted by the conductive material overflowing between the primer and the substrate body, so the circuit of the present invention does not electrically connect to each other according to the circuit of FIG. 3B of the prior art to generate a short circuit. situation.

1, 2‧‧‧ package substrate

10, 20, 31, 41‧‧‧ substrate body

11, 21, 32‧‧‧ lines

111, 212‧‧‧Electrical contacts

12‧‧‧ solder mask

211, 321, 421, 431‧‧‧ top

22‧‧‧ solder balls

3, 40, 40'‧‧‧ semiconductor packages

33‧‧‧Electrical bumps

34‧‧‧Semiconductor wafer

341‧‧‧electrode pads

35, 48‧‧ ‧ primer

351‧‧‧ gap

352‧‧‧Electrical materials

4, 4'‧‧‧ substrate structure

411‧‧‧ first surface

412‧‧‧ second surface

42‧‧‧First line

43‧‧‧second line

44, 44'‧‧‧ Isolated structure

441‧‧‧ protruding parts

442‧‧‧Depression

45‧‧‧Electronic components

450‧‧‧Action surface

451‧‧‧First electrode pad

452‧‧‧Second electrode pad

46‧‧‧First conductive bump

47‧‧‧Second conductive bump

H1, H2, H3‧‧‧ height

1 is a top plan view showing a flip chip package substrate of the prior art; FIG. 2 is a schematic perspective view showing another flip chip package substrate of the prior art; FIGS. 3A and 3B are drawings FIG. 4A is a cross-sectional view showing a first embodiment of a substrate structure of the present invention; FIG. 4B is a cross-sectional view showing a substrate structure according to FIG. 4A; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 5A is a cross-sectional view showing a second embodiment of a substrate structure of the present invention; and FIG. 5B is a substrate structure according to FIG. 5A. A schematic cross-sectional view of a second embodiment of a semiconductor package of the present invention is shown.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings of the present specification are only used in conjunction with the contents disclosed in the specification to familiarize themselves with the art. The understanding and reading of the person is not intended to limit the conditions for the implementation of the present invention, and therefore does not have technical significance. Any modification of the structure, change of the proportional relationship or adjustment of the size may not be affected by the present invention. The efficacies and the achievable objectives should still fall within the scope of the technical content disclosed in the present invention.

At the same time, terms such as "upper", "one", "first", "second", "surface" and "acting surface" as used in this specification are for convenience only and are not intended to be used The scope of the invention can be implemented, and the relative changes or adjustments of the invention are considered to be within the scope of the invention.

Fig. 4A is a schematic cross-sectional view showing the first embodiment of the substrate structure of the present invention. As shown, the substrate structure 4 includes a substrate body 41, adjacent first and second lines 42 and 43 and an isolation structure 44.

The substrate body 41 has a first surface 411 and a second surface 412 opposite to each other. The first line 42 and the second line 43 are respectively formed on the first surface 411 of the substrate body 41, and the first line 42 and the second line 43 respectively have power supply connection external components (such as solder balls) Or the top surface 421 of the conductive bump) and the top surface 431.

The isolation structure 44 is formed on the first surface 411 of the substrate body 41 and located between the first line 42 and the second line 43 to electrically isolate the first line 42 from the isolation structure 44. Second line 43.

The insulating structure 44 is composed of at least one protruding portion 441, and the material of the protruding portion 441 can be an insulating material. The protruding portion 441 and the substrate body 41 may be integrally formed or separately formed, and may be the same material or different materials. quality.

The height H1 of the protruding portion 441 is smaller than the height H2 of the first line 42 or the height H3 of the second line 43. In other embodiments, the height H1 of the protrusion 441 may also be equal to or greater than the height H2 of the first line 42 or the height H3 of the second line 43.

In addition, the number, width or length of the protrusions 441 may also be adjusted according to the distance, width or length between the first line 42 and the second line 43.

4B is a cross-sectional view showing the first embodiment of the semiconductor package of the present invention in accordance with the substrate structure of FIG. 4A. As shown, the semiconductor package 40 includes a substrate body 41, adjacent first and second lines 42 and 43, an isolation structure 44, electronic components 45, at least one first conductive bump 46, and at least one second conductive Bump 47.

The substrate body 41 has a first surface 411 and a second surface 412 opposite to each other. The first line 42 and the second line 43 are respectively formed on the first surface 411 of the substrate body 41, and the first line 42 and the second line 43 respectively have a top surface 421 and a top surface 431.

The isolation structure 44 is formed on the first surface 411 of the substrate body 41 and located between the first line 42 and the second line 43 to electrically isolate the first line 42 from the isolation structure 44. Second line 43.

The insulating structure 44 is composed of at least one protruding portion 441, and the material of the protruding portion 441 can be an insulating material. The protruding portion 441 and the substrate body 41 may be integrally formed or separately formed and made of the same material or different materials.

The height H1 of the protruding portion 441 is smaller than the height of the first line 42 H2 or the height H3 of the second line 43. In other embodiments, the height H1 of the protrusion 441 may also be equal to or greater than the height H2 of the first line 42 or the height H3 of the second line 43.

The first conductive bump 46 is formed on the top surface 421 of the first line 42 , and the second conductive bump 47 is formed on the top surface 431 of the second line 43 . The first conductive bump 46 or the second conductive bump 47 may be a solder ball, a solder or a metal pillar or the like.

The electronic component 45 is disposed on the first conductive bump 46 and the second conductive bump 47 to electrically connect the first conductive bump 46 and the second conductive bump 47 respectively. 42 and the second line 43.

The electronic component 45 can be a semiconductor wafer, a wafer, or the like, and is placed on the top surface 421 of the first line 42 and the top surface 431 of the second line 43 in a flip chip manner. Specifically, the electronic component 45 can have an active surface 450 and a first electrode pad 451 and a second electrode pad 452 respectively formed on the active surface 450. The first conductive bump 46 is formed on the first line 42. Between the top surface 421 and the first electrode pad 451, the second conductive bump 47 is formed between the top surface 431 of the second line 43 and the second electrode pad 452.

The semiconductor package 40 may include a primer 48 formed between the first surface 411 of the substrate body 41 and the active surface 450 of the electronic component 45 to cover the first line 42 and the second line 43. The protrusion 441 of the structure 44, the first conductive bump 46 and the second conductive bump 47.

Fig. 5A is a schematic cross-sectional view showing a second embodiment of the substrate structure of the present invention. The substrate structure 4' of FIG. 5A is substantially the same as the substrate structure 4 of the above FIG. 4A, and the main differences are as follows: In FIG. 5A, the insulating structure 44' may be formed by at least one recessed portion 442 extending from the first surface 411 of the substrate body 41 to the inside of the substrate body 41.

In addition, the number, depth, width or length of the recessed portion 442 may also be adjusted according to the distance, height, width or length between the first line 42 and the second line 43.

FIG. 5B is a cross-sectional view showing a second embodiment of the semiconductor package of the present invention according to the substrate structure of FIG. 5A. The semiconductor package 40' of FIG. 5B is substantially the same as the semiconductor package 40 of the above FIG. 4B, and the main differences are as follows: In FIG. 5B, the insulating structure 44' may be formed by at least one recess 442 extending from the first surface 411 of the substrate body 41 to the inside of the substrate body 41. At the same time, the primer 48 can be filled in the recess 442 of the insulating structure 44'.

As can be seen from the above, in the substrate structure and the semiconductor package of the present invention, the bump wire direct connection (BOT) technology of the flip chip package is mainly used, and the conductive bumps are respectively formed on the top surfaces of the adjacent two lines, and An insulating structure having protrusions or depressions is formed between the two lines.

Therefore, compared with the first embodiment of the prior art, the substrate structure of the present invention can omit the solder resist layer shown in FIG. 1 to form a substrate structure with a fine line width/fine line pitch, and reduce the process and cost of the substrate structure. And increase the number of conductive bumps on the line.

Furthermore, the semiconductor package of the present invention is formed after the electronic component and the primer are formed, as compared with the prior art FIGS. 2 to 3B. In the operation of the reliability test or the like, the insulating structure may be interposed between the two lines, and the conductive material overflowing between the primer and the substrate body may be separated or shunted, so the circuit of the present invention There is no short circuit in which the lines of the prior art figure 3B are electrically connected to each other.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the patent application.

40‧‧‧Semiconductor package

41‧‧‧Substrate body

411‧‧‧ first surface

412‧‧‧ second surface

42‧‧‧First line

421, 431‧‧‧ top

43‧‧‧second line

44‧‧‧Isolated structure

441‧‧‧ protruding parts

45‧‧‧Electronic components

450‧‧‧Action surface

451‧‧‧First electrode pad

452‧‧‧Second electrode pad

46‧‧‧First conductive bump

47‧‧‧Second conductive bump

48‧‧‧Bottom

H1, H2, H3‧‧‧ height

Claims (14)

a substrate structure comprising: a substrate body having opposite first and second surfaces; adjacent first and second lines respectively formed on the first surface of the substrate body, and the first line And the second line has a top surface, wherein at least one first conductive bump and at least one second conductive bump are respectively formed on a top surface of the first line and a top surface of the second line; and an isolation structure And being formed on the first surface of the substrate body and located between the first line and the second line to electrically isolate the first line and the second line by the isolation structure. The substrate structure of claim 1, wherein the insulating structure is formed by at least one protruding portion, and the protruding portion is integrally formed with the substrate body or separately formed. The substrate structure according to claim 2, wherein the material of the protruding portion is an insulating material. The substrate structure of claim 2, wherein the height of the protrusion is less than a height of the first line or a height of the second line. The substrate structure of claim 1, wherein the insulating structure is formed by at least one recessed portion, and the recessed portion extends from the first surface of the substrate body to the inside of the substrate body. A semiconductor package comprising: a substrate body having opposite first and second surfaces; An adjacent first line and a second line respectively formed on the first surface of the substrate body, and the first line and the second line each have a top surface; and the isolation structure is formed on the first substrate body a surface between the first line and the second line to electrically isolate the first line and the second line by the isolation structure; at least one first conductive bump is formed on the first line a top surface of the second conductive bump is formed on the top surface of the second line; and the electronic component is disposed on the first conductive bump and the second conductive bump The first line and the second line are electrically connected respectively. The semiconductor package of claim 6, wherein the insulating structure is formed by at least one protruding portion, and the protruding portion is integrally formed with the substrate body or separately formed. The semiconductor package of claim 7, wherein the material of the protruding portion is an insulating material. The semiconductor package of claim 7, wherein the height of the protrusion is less than a height of the first line or a height of the second line. The semiconductor package of claim 6, wherein the insulating structure is formed by at least one recessed portion, and the recessed portion extends from the first surface of the substrate body to the inside of the substrate body. The semiconductor package of claim 6, wherein the electronic component is a semiconductor wafer or a wafer and is flip-chip mounted on a top surface of the first line and a top surface of the second line. on. The semiconductor package of claim 6, wherein the electronic component has an active surface and a first electrode pad and a second electrode pad respectively formed on the active surface, the first conductive bump being formed on Between the top surface of the first line and the first electrode pad, the second conductive bump is formed between the top surface of the second line and the second electrode pad. The semiconductor package of claim 6, further comprising a primer formed between the first surface of the substrate body and the electronic component to cover the first line, the second line, and the isolation structure. a first conductive bump and a second conductive bump. The semiconductor package of claim 13, wherein the undercoat covers the protrusion of the isolation structure or is filled in the recess of the isolation structure.