TWI393501B - Cutting process of circuit board - Google Patents

Description

Line carrier cutting process

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a cutting process for a line carrier, and more particularly to a cutting process for a line carrier that avoids residual copper wire (burrs) around the area being cut.

With the advancement of technology and the continuous improvement of the quality of life, coupled with the integration and continuous growth of the 3C industry, the application fields of integrated circuits (ICs) are becoming wider and wider. In the IC mounting technology, a copper bump or a Flip Chip bonding copper bump is commonly connected between the line carrier and the wafer, and the wafer is placed on the line. After the wafer is coated on the board with the sealant, the cutting process of the line carrier is performed.

The cutting process of the conventional line carrier is to cut the tool along the circumference of the predetermined cutting area so that the cut area forms a cutting slot. Also, since the cutting slots are respectively arranged in parallel between the package regions of the line carrier, the cutting slots can separate the line carrier into a plurality of package regions, and the respective wafers are respectively disposed on the package regions. However, it is worth noting that before the cutting, the circumference of the predetermined cutting area is completely covered by the copper layer formed by the electroplating process, and once the tool is cut along the circumference of the predetermined cutting area, part of the copper layer is stretched and extended by the cutter, resulting in The so-called copper wire (burr), and the copper wire (burr) remaining on the side wall of the cutting slot must be removed by the blade, otherwise it will affect the electrical reliability of the line carrier. Also, since the cutting process must increase the step of removing the copper wire or the burrs, the time and cost of the process cannot be reduced.

The invention provides a cutting process for a line carrier board, which can reduce the occurrence of burrs after cutting.

The invention provides a cutting process for a line carrier board, comprising the steps of: firstly, providing a line carrier board having a plurality of package areas and a predetermined cutting area connecting the package areas, the circumference of the predetermined cutting area Covered by a conductive layer formed by the electroplating process. Then, a metal layer is formed on a portion of the surface of the conductive layer, and an etching process is performed, wherein the metal layer is etch-resistant, and a portion of the surface of the conductive layer not covered by the metal layer is etched to expose the A portion of the surface of the conductive layer covered by the metal layer is formed around the predetermined dicing area to form a plurality of conductive regions on the package regions. Then, the metal layer is removed to expose the conductive regions, and an electronic component is disposed on the package regions. Thereafter, it is cut along the circumference of the predetermined cutting area to separate the package areas.

In an embodiment of the invention, the above method of forming the metal layer comprises electroplating.

In an embodiment of the invention, before the forming the metal layer, the method further comprises forming a patterned photoresist layer on the conductive layer, and after forming the metal layer, removing the patterned photoresist layer.

In an embodiment of the invention, the electronic component is electrically connected to the conductive region by wire bonding.

In an embodiment of the invention, the electronic component is electrically connected to the conductive region by a flip chip bonded bump.

Based on the above, the present invention can avoid residual copper wire (burr) around the cut area, and improve the electrical reliability of the line carrier. The present invention changes the coverage area of the original conductive layer relative to the conventional problem of generating burrs after cutting. Less, it can reduce the post-processing time and cost of burrs after cutting.

The above described features and advantages of the present invention will be more apparent from the following description.

1A-1E are schematic cross-sectional views showing a cutting process of a line carrier according to an embodiment of the invention. Referring first to FIG. 1A, the line carrier 100 has a plurality of package regions 110 and a predetermined cutting region 120 (shown in phantom) connecting the package regions 110. Refer to Figure 2 for a top view of the predetermined cutting area 120. The periphery of the predetermined cutting region 120 is covered by a conductive layer 112 formed by an electroplating process. Although the perspective view of the line carrier 100 is not shown in this embodiment, it is conceivable that the portion of the periphery of the predetermined cutting area 120 that is connected to the package area 110 is indicated by a solid line in FIG. 1A, and the predetermined cutting area is shown. Portions of the periphery of 120 that are not connected to the package area 110 are indicated by broken lines for convenience of explanation. Reference numeral 114 is an insulating layer of the wiring carrier 100, such as a glass epoxy resin.

In FIG. 1A, the conductive layer 112 is formed on the line carrier 100 by a full additive method. The conductive layer 112 may be made of copper or other metal. In a subsequent process, the conductive layer 112 may be used as a pad, a line or The heat dissipation layer is not limited herein.

Next, referring to FIG. 1B and FIG. 1C, a metal layer 130 is formed on a portion of the surface of the conductive layer 112 by a semi-additive method. The method for forming the metal layer 130 is, for example, electroplating, and the metal layer 130 may be made of nickel or other metal. . At the same time, a patterned photoresist layer 122 is formed on the conductive layer before the metal layer 130 is formed. The patterned photoresist layer 122 may extend from the outer surface of the conductive layer 112 to both sides to cover a portion of the side surface, so that the plated metal layer 130 cannot completely cover the surrounding surface of the conductive layer 112, and thus is not metal in the subsequent process. The conductive layer 112 on the predetermined dicing area 120 covered by the layer 130 will be revealed.

Next, referring to FIG. 2D, after the metal layer 130 is formed, the patterned photoresist layer 122 is removed, and an etching process is performed. In this embodiment, the etching solution used in the etching process can etch the conductive layer 112 (for example, copper), and the material of the metal layer 130 is nickel, which is different from the material of the conductive layer 112, and therefore has corrosion resistance to the etching liquid, and does not Eroded by the etching solution. However, the present invention does not limit the type of the etching liquid as long as the metal layer 130 has corrosion resistance to the etching liquid. A portion of the surface of the conductive layer 112 (which is originally covered with the patterned photoresist layer 122) that is not covered by the metal layer 130 is etched to expose the periphery of the predetermined cut region 120 and is covered by the metal layer 130, affected by the etching. A portion of the surface of the conductive layer 112 is not etched to form a plurality of conductive regions 112a on the package regions 110.

Next, referring to FIG. 1E, the metal layer 130 is removed to expose the conductive regions 112a. The conductive regions 112a are electrically connected to an electronic component 140. The position of the electronic component 140 in the figure is not the same as the position of the conductive region 112a. On the section, it is indicated by a dotted line. The electronic component 140 is, for example, a light emitting diode chip. The electronic component 140 is disposed on the package region 110 of the line carrier 100 and electrically connected to the conductive region 112a. The electronic component 140 is electrically connected to the conductive region 112a, for example, by wire bonding (not shown), or is electrically connected to the conductive region 112a by a bump-bonded bump (not shown).

Referring to FIG. 1E, the circumference of the predetermined cutting area 120 is cut to separate the package areas 110. At this time, FIG. 1E does not show the predetermined cutting area 120, indicating that the predetermined cutting area 120 has been cut. Referring to the top view of FIG. 2, the cut region forms a cut slot 100S on the line carrier 100, so the cut slot 100S can separate the package regions 110 of the line carrier 100 from each other. Also, when the circuit carrier 100 performs the cutting process, the area covered by the conductive layer 112 is partially etched first, so that the residual copper wire or the burr on the sidewall of the cutting slot 100S can be reduced, thereby saving the processing time and cost of subsequently removing the burrs.

In summary, the present invention proposes a cutting process for avoiding the line carrier of residual copper wire (burr) around the cut area, which can improve the electrical reliability of the line carrier, and the problem of burrs due to the conventional cutting. According to the invention, the coverage area of the original conductive layer is reduced, so that the post-processing time and cost of generating burrs after cutting can be reduced.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Line carrier

100S. . . Cutting slot

110. . . Package area

112. . . Conductive layer

112a. . . Conductive zone

114. . . Insulation

120. . . Scheduled cutting area

122. . . Patterned photoresist layer

130. . . Metal layer

140. . . Electronic component

1A to 1E are schematic cross-sectional views showing a cutting process of a line carrier according to an embodiment of the present invention.

2 is a top plan view of a line carrier of an embodiment of the present invention.

100. . . Line carrier

110. . . Package area

112a. . . Conductive zone

120. . . Scheduled cutting area

130. . . Metal layer

Claims (7)

A cutting process for a circuit carrier includes: providing a circuit carrier having a plurality of package regions and a predetermined cutting region connecting the package regions, wherein the periphery of the predetermined cutting region is formed by an electroplating process Covering a conductive layer; forming a metal layer on a portion of the surface of the conductive layer, and performing an etching process, wherein the metal layer is corrosion-resistant, and a portion of the surface of the conductive layer not covered by the metal layer is etched and exposed Excluding the periphery of the predetermined cutting region, and a portion of the surface of the conductive layer covered by the metal layer is not etched to form a plurality of conductive regions on the package regions; the metal layer is removed to expose the conductive regions, The electronic component is electrically connected to the package area; and after the metal layer is removed, the periphery of the predetermined cutting area is cut to separate the package areas. A cutting process for a wiring board as described in claim 1, wherein the method of forming the metal layer comprises electroplating. The cutting process of the line carrier according to claim 1, wherein before forming the metal layer, forming a patterned photoresist layer on the conductive layer, and after forming the metal layer, removing the metal layer Patterned photoresist layer. The cutting process of the line carrier according to claim 1, wherein the conductive layer is a copper layer. The cutting process of the line carrier according to claim 1, wherein the metal layer is a nickel layer. The cutting process of the line carrier according to claim 1, wherein the electronic component is electrically connected to each of the conductive regions by wire bonding. The cutting process of the line carrier according to claim 1, wherein the electronic component is electrically connected to each of the conductive regions by a flip chip bonded bump.