TWI389261B - Buried wordline dram with stacked capacitor structures and fabrication methods for stacked capacitor structures - Google Patents

Description

Stacked capacitor structure and stack of buried gate word line DRAM device Stack capacitor manufacturing method

The present invention relates to a method of fabricating a stacked capacitor structure, and more particularly to a method of fabricating a stacked capacitor structure for a buried gate word line bonded DRAM device.

Buried Wordline DRAM technology, unlike traditional Trench technology, is a trench-based standard stacked capacitor technology that delivers performance, low power and small Features such as size wafers have led to breakthroughs in the field of achieving complete vertical cells.

In the prior art, in the fabrication of a stacked capacitor structure in which a buried gate word line is connected to a DRAM device, it is necessary to cooperate with a process for fabricating a very high aspect ratio capacitor structure. 1A and 1B are schematic views showing a partial process of a conventional stacked capacitor structure. Referring to FIG. 1A, a dielectric layer 2 is formed on a semiconductor substrate 1. A high aspect ratio capacitor opening 5 is then formed in the dielectric layer 2, and a conductive layer 3 (as the lower electrode of the capacitor structure) is deposited on the inner sidewalls of the dielectric layer 2 and the capacitor opening 5. Next, referring to FIG. 1B, the conductive layer 3 on the surface of the dielectric layer 2 is removed by chemical mechanical polishing, and then the dielectric layer 2 is exposed and exposed by a wet etching process, or a die etch. The upper portion of layer 3 forms a partially exposed capacitor cup for subsequent processing.

As the capacitance density of the memory array region increases, the pitch of the capacitor structures is closer. In particular, when performing the above-described steps of forming a capacitor cup, it is often caused by defocusing of the lithography process or by etching the opening. The process results in different local area etch rates, resulting in insufficient etching depth of the capacitor cup, as shown by openings 5' and 5" in Figure 1C. This leads to subsequent processes such as mold etch, capacitor cups. The bottom collapses or peels off due to loss of support, as shown by the capacitor cups 3' and 3" of Figure 1D.

An embodiment of the present invention provides a method of fabricating a stacked capacitor, comprising: providing a substrate having a memory cell array region and a peripheral region, wherein the memory cell array region comprises a plurality of capacitor stacked structures, the peripheral region Having an alignment mark; forming a first dielectric layer on the substrate; forming a stable stacked layer comprising a tantalum nitride layer and a hafnium oxide layer on the first dielectric layer; forming a second dielectric layer On the stable stacking layer; performing a first patterning step to form a plurality of capacitor openings in the memory cell array region and a trench surrounding the alignment mark; compliantly depositing a first electrode layer on the substrate and filling Inserting a plurality of capacitor openings on the inner side surface of the trench; depositing a third dielectric layer on the first electrode layer and covering the entire substrate, filling the capacitor opening and the interior of the trench; planarizing the first a third dielectric layer and removing an excess third dielectric layer on the surface of the second dielectric layer; performing a second patterning step to pattern the second dielectric layer to define a first opening to expose the capacitor opening Surface as well a second opening exposing a region surrounded by the trench; sequentially removing the third dielectric layer exposed by the first and second openings and the yttrium oxide layer portion of the stable stacked layer; compliantly depositing a high a dielectric constant dielectric layer and a second electrode layer on the substrate and filling the inner surfaces of the plurality of capacitor openings and trenches; depositing a metal layer on the substrate and filling the plurality of capacitor openings With the interior of the trench; pattern the metal The layer exposes an opening region of the peripheral region; removing the stable stacked layer and the first dielectric layer under the opening region of the peripheral region, and exposing the alignment mark; and depositing a fifth dielectric layer thereon The open area of the peripheral region is filled in the substrate, and then the fifth dielectric layer is planarized.

Another embodiment of the present invention provides a stacked capacitor structure of a buried gate word line DRAM device, comprising: a substrate having a memory cell array region and a peripheral region, the peripheral region having an alignment mark; a first dielectric layer is disposed on the substrate; a stable stacked layer is disposed on the first dielectric layer; a second dielectric layer is disposed on the stable stacked layer; and a plurality of stacked capacitor structures are disposed on the memory cell array The region and a barrier structure are disposed around the alignment mark in the peripheral region; wherein the alignment mark above the alignment region and the interior of the barrier structure are a transparent third dielectric layer.

In order to make the invention more apparent, the following detailed description of the embodiments and the accompanying drawings are as follows:

The following is a detailed description of the embodiments and examples accompanying the drawings, which are the basis of the present invention. In the drawings or the description of the specification, the same drawing numbers are used for similar or identical parts. In the drawings, the shape or thickness of the embodiment may be expanded and simplified or conveniently indicated. In addition, the components of the drawings will be described separately, and it is noted that the components not shown or described in the drawings are known to those of ordinary skill in the art, and in particular, The examples are merely illustrative of specific ways of using the invention and are not intended to limit the invention.

In order to effectively improve the process margin of the stacked capacitor structure and good At a rate, a stabilizing structure (ST) structure can be added to the dielectric layer, for example, by adding a tantalum nitride/yttria layer to stabilize the structure of the capacitor cup. Moreover, in the process of defining the capacitor opening, the edge of the capacitor opening is protected by a patterned layer of tantalum nitride. When the step of stencil etching is performed, the collapse of the capacitor cup can be avoided.

Figure 2 shows a schematic diagram of avoiding collapse of the stacked capacitor cup structure by the addition of a tantalum nitride/yttria layer. Referring to FIG. 2, a semiconductor substrate 11 is first provided having a memory cell array region 10A and a peripheral region 10P. In the memory cell array region 10A, the active device 15 is electrically connected to an electrical contact 25 corresponding to the position of a stacked capacitor. The electrical contact 25 is formed in the dielectric layer 20 and is formed by a metallization process. A patterned tantalum nitride layer 30 is disposed on the semiconductor substrate 11 to define the locations of the stacked capacitors. The peripheral region 10P has an alignment mark M0 formed by connecting an interconnect layer to the tantalum nitride layer 30.

A first dielectric layer 35 is disposed on the semiconductor substrate 11, and the stabilizing layer structure (ST) including the tantalum nitride layer 40 and the hafnium oxide layer 45 is disposed on the first dielectric layer 35. Next, a patterned capacitor opening process is performed to form an opening corresponding to the position of the electrical contact 25, and a conductive layer 62 is formed on the inner sidewall and the bottom of the opening to fill the dielectric layer 63 at the central portion of the opening. Next, the tantalum nitride layer 50 is used as a hard mask layer having openings 65a and 65b in the array region 10A and the opening 65c in the peripheral region 10P, and then defining a capacitor cup opening, that is, removing portions of the hafnium oxide layer 45a, 45b. And 45c, and continue with the next steps.

However, the tantalum nitride layer is transparent only by increasing the stability layer structure. When the dielectric layer of the poor electrode layer is subjected to the metal plate process (PL) process of the subsequent electrode layer, the tungsten metal (Tungsten) is a non-transmissive layer, which may cause the upper mask to be aligned with the alignment mark M0. difficult. The method of overcoming the alignment alignment marks is to use an indirect alignment method or to remove the stable layer structure above the alignment mark M0. If the indirect alignment method is used, the progressive error will increase. On the other hand, if the stabilizing layer structure above the alignment mark M0 is removed, for example, when the capacitor cup opening is defined, that is, the partial yttrium oxide layers 45a, 45b, and 45c are removed by wet etching, the smoothing can be smoothly performed. The tantalum nitride layer and the tantalum oxide layer 45c over the alignment mark M0 are removed, but the etching liquid enters from the peripheral region 10P as indicated by an arrow E, thereby laterally invading the array region 10A, thereby affecting the device performance.

In order to avoid the etchant from laterally invading the array region from the peripheral region when removing the stabilizing layer structure above the alignment mark M0, the disclosed embodiment provides a barrier structure disposed in the peripheral region and surrounding the alignment mark to be effective The etchant is prevented from laterally invading the array region from the peripheral region.

3A is a plan view showing a buried gate word line bonded DRAM device in accordance with an embodiment of the present invention. In FIG. 3A, the buried gate word line connecting DRAM device 100 wafer includes a plurality of memory cell array regions 100A and a peripheral region 100P (or a peripheral street (Kerf) or a kerf line). The alignment mark M0 is disposed in the peripheral area 100P. In order to remove the stable layer structure above the alignment mark M0, a window (e.g., region R) is formed using a lithography process.

Figures 3B and 3C show schematic diagrams of a partial region R of Figure 3A. According to an embodiment of the present invention, a barrier structure is formed in the peripheral region and surrounds the alignment mark M0. Referring to FIG. 3B, in the step of forming a capacitor opening, At the same time, a groove 80 is formed around the alignment mark M0. The width of the groove 80 is W, the distance from the region R in the X direction is ΔX, and the distance from the region R in the Y direction is ΔY. After forming the same conductive layer structure as the capacitor in the trench 80, the window region 85 is formed by a lithography process, and the stable layer structure in the window is removed, which is effective due to the barrier structure of the conductive layer in the trench 80. The etchant is prevented from laterally invading the array region from the peripheral region.

4A-4J are cross-sectional views showing various steps of a stacked capacitor cup structure in accordance with an embodiment of the present invention. Referring to FIG. 4A, a semiconductor substrate 110 is first provided having a memory cell array region 100A and a peripheral region 100P. The memory cell array region 100A has a plurality of active devices 115, such as MOS field effect transistors, electrically connected to an electrical contact 125, corresponding to the position of the stacked capacitors. Electrical contacts 125 may be formed in dielectric layer 120, such as an inter-metal dielectric layer (IMD), which may be formed by various metallization wiring processes.

A tantalum nitride layer 130 is disposed on the semiconductor substrate 110 to define a location of the stacked capacitors. The peripheral region 100P has an alignment mark M0 on the tantalum nitride layer 130.

A first dielectric layer 135 is disposed on the semiconductor substrate 110, such as a plasma-assisted chemical vapor deposition (PECVD) layer to form a tetraethoxyphthalate (TEOS) layer having a thickness in the range of about 800 ± 100 nm. And the stabilizing layer structure includes a tantalum nitride layer 140 (for example, a SiN layer formed by PECVD having a thickness of about 50±10 nm) and a hafnium oxide layer 145 (for example, a TEOS layer formed by PECVD having a thickness of about 500±100 nm). On the first dielectric layer 135.

Then, performing a patterned capacitor opening process, forming an opening corresponding to the electrical contact position in the memory cell array region, and forming a trench in the peripheral region Surround the alignment mark M0. Referring to FIG. 4B, a first lithography process is performed, including a SiN layer 150 (about 100±10 nm thick) formed by PECVD on the first dielectric layer 135. Next, a carbon hard mask 152 is formed, which is composed of a carbon-hydrgen polymer and a top thin silicon oxide layer (top thin SiON) on the SiN layer 150, wherein the hydrocarbon is hydrogen-hydrogen. The thickness of the polymer ranges from about 2,000 angstroms to 5,000 angstroms, and the thickness of the SiON ranges from about 250 Å to about 1,500 angstroms. Then, an anti-reflective coating (ARC, thickness about 50 nm) 154 is formed on the carbon hard mask layer 152. A patterned photoresist layer 156 is formed on the anti-reflective coating 154, and an opening 155a corresponding to the capacitance position is defined in the memory cell array region 100A and an opening 155b surrounding the trench of the alignment mark M0 to the peripheral region 100P.

The anti-reflective coating 154, the carbon hard mask layer 152 and the SiN layer 150 are defined by the patterned photoresist layer 156 as a mask, and the defined SiN layer 150 is used as a mask, for example, hydrofluoric acid buffer etching (BHF). The solution, the ruthenium oxide layer 145, the tantalum nitride layer 140, the first dielectric layer 135, and the tantalum nitride layer 130 are exposed to expose the underlying substrate structure as shown in FIG. 4C. Thereby, the capacitor opening 160a and the surrounding trench 160b are formed. Since the top end of the capacitor opening 160a is protected by the continuously surrounding patterned SiN layer 150, the capacitor cup opening collapse can be avoided when the capacitor opening is etched.

Referring to FIG. 4D, a conductive layer 162 is conformally formed on the base structure, and a conductive layer 162 is formed on the inner side wall and the bottom of the opening 160a and the trench 160b, for example, titanium nitride is formed by atomic layer deposition (ALD). a TiN) layer (having a thickness of about 26 ± 5 nm), followed by chemical vapor deposition (CVD) to form a layer 164 of ozone-tetraethoxy silicate (O-TEOS, thickness about 330 ± 100 nm) on the substrate structure and The center portion of the opening 160a and the groove 160b is filled.

Next, referring to FIG. 4E, a chemical mechanical polishing (CMP) 210 is applied to the base structure to remove the surface O-TEOS layer 164 to expose the flat SiN layer 150 and the O-TEOS layer 164 surface.

Referring to FIG. 4F, a second lithography process is performed, including forming a carbon hard mask layer (about 200 nm thick) 170 on the SiN layer 150 to form an anti-reflective coating (ARC, nitrogen oxide having a thickness of about 50 nm). The germanium layer 172 is on the carbon hard mask layer 170, and a patterned photoresist layer 174 is formed on the anti-reflective coating layer 172, and an opening 175a corresponding to the capacitance position and an opening 175b above the alignment mark M0 are defined.

Referring to FIG. 4G, the patterned photoresist layer 174 is masked, etched downward through the openings 175a and 175b, for example, by reactive ion etching or plasma etching, and partially etched the partially exposed TiN layer 162 and the SiN layer 150. The patterned photoresist layer 174 and the carbon hard mask layer 170 are removed. Next, a wet etching process is performed to remove the exposed O-TEOS layers 164a and 164b, and the yttrium oxide layers 145a and 145b exposed by the stabilizing layer structure are removed, as shown in FIG. 4H. In one embodiment, a cerium oxide layer of about 400 nm may be removed using a hydrofluoric acid buffered etch (BHF) solution in a first stage, and an oxidation of about 100 nm may be removed in a second stage using a dilute hydrofluoric acid (DHF) solution.矽 layer. It should be understood that, at the peripheral region 100P, the trench surrounding the alignment mark M0 is received by the conductive layer (TiN) 162, so that when the wet etching step is performed, the etching liquid can be prevented from laterally invading the array region from the peripheral region. . More specifically, the conductive layer (TiN) 162 at the peripheral region 100P can be used as a barrier structure for preventing the etching liquid from invading the array region laterally from the peripheral region.

Referring to FIG. 4I, a high-k dielectric layer 182 is conformally formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). A conductive layer (e.g., TiN) 184 is conformally formed on the high-k dielectric layer 182 by chemical vapor deposition (CVD) or atomic layer deposition (ALD) on the substrate structure. A capacitor stack structure is formed by the conductive layer 150, the high-k dielectric layer 182, and the conductive layer 184. Next, a metal layer (e.g., tungsten) 186 is conformally formed by chemical vapor deposition (CVD) on the base structure and filled into the opening and the central portion of the trench.

Next, a photoresist layer 188 is formed on the metal layer (tungsten) 186. The photoresist layer 188 shields the metal layer (tungsten) 186 of the array region 100A from the metal layer (tungsten) 186 exposing the peripheral region 100P to form an alignment mark M0. The upper opening 185.

Referring to FIG. 4J, after removing the photoresist layer 188, a dielectric layer 195 is formed on the substrate structure, for example, by plasma-assisted chemical vapor deposition (PECVD) to form a tetraethoxyphthalate (TEOS) layer. And fill in the opening above the alignment mark M0. Dielectric layer 195 is then planarized to facilitate subsequent processing, such as semiconductor back end processing (BEOL). It should be understood that since the alignment mark M0 is covered by the transparent dielectric layer (TEOS) 195 at this time, for the subsequent process, for example, the metal wire process (PL) process of the upper electrode layer is performed. The process accuracy can be increased by directly aligning the alignment mark M0.

The method for fabricating a stacked capacitor of a dynamic random access memory (DRAM) device disclosed in the present invention has the advantage of providing a stable layer structure to prevent the capacitor cup from falling or collapsing when performing a mold etch. Moreover, for the alignment requirement of the subsequent process, when the opaque stable layer structure above the alignment mark M0 is removed, the surrounding barrier structure is added, and the etching liquid can be effectively prevented from laterally invading the array region from the peripheral region. Moreover, the present invention provides an alignment mark required in a lithography process and a method of fabricating the same Causes the back end of the process (BEOL) or the upper electrode layer (PL) to be misaligned and exposed.

The present invention has been disclosed in the above various embodiments, and is not intended to limit the scope of the present invention. Any one of ordinary skill in the art can make a few changes and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

1‧‧‧Semiconductor substrate

2‧‧‧Dielectric layer

3‧‧‧ Conductive layer

3', 3" ‧ ‧ collapsed, stripped capacitor cup

5‧‧‧ Capacitance opening

5', 5"‧‧‧Exposure out of focus, under-etched capacitor openings

11, 110‧‧‧ semiconductor substrate

10A, 100A‧‧‧ memory cell array area

10P, 100P‧‧‧ surrounding area

15, 115‧‧‧ active components

20, 120‧‧‧ dielectric layer

25, 125‧‧‧Electrical contact

30, 130‧‧‧ tantalum nitride layer

35, 135‧‧‧ first dielectric layer

40, 140‧‧‧ tantalum nitride layer

45, 145‧‧‧ yttrium oxide layer

45a, 45b and 45c‧‧‧ part of the yttrium oxide layer

50, 150‧‧‧ tantalum nitride layer

62‧‧‧ Conductive layer

63‧‧‧ dielectric layer

65a, 65b, 65c‧‧

80‧‧‧ trench

85‧‧‧ window area

100‧‧‧DRAM device

145a and 145b‧‧‧ exposed yttrium oxide layer

152, 170‧‧‧ carbon hard mask

154, 172‧‧‧Anti-reflective coating

156, 174, 188‧‧‧ patterned photoresist layer

155a, 155b‧‧‧ openings

160‧‧‧ dielectric layer

160a‧‧‧ openings

160b‧‧‧ trench

162‧‧‧ Conductive layer (TiN)

164‧‧‧Ozone-tetraethoxy phthalate (O-TEOS) layer

164a and 164b‧‧‧ exposed O-TEOS layer

175a and 175b‧‧‧ openings

182‧‧‧high-k dielectric layer

184‧‧‧ Conductive layer (TiN)

185‧‧‧ Alignment opening above the mark M0

186‧‧‧metal layer (tungsten)

195‧‧‧Dielectric Layer (TEOS)

210‧‧‧Chemical Mechanical Grinding (CMP)

R‧‧‧Local area

M0‧‧‧ alignment mark

E‧‧‧etching liquid intrusion direction

1A and 1B are schematic views showing a part of the process of the conventional stacked capacitor structure; the 1C figure shows the opening corresponding to the 1A figure, the depth of the capacitor opening due to the defocus of the exposure or the etch rate due to the local area. Insufficient schematic diagram; Figure 1D shows a schematic view of the capacitor cup corresponding to Figure 1B, which causes a collapse or peeling of the capacitor cup after stencil etching; Figure 2 shows the increase in tantalum nitride by The help of the ruthenium oxide layer avoids the collapse of the stacked capacitor cup structure. 3A is a plan view showing a buried gate word line-connected DRAM device according to an embodiment of the present invention, and FIGS. 3B and 3C are views showing a partial region R of FIG. 3A; and 4A- 4J shows a cross-sectional view of various steps of a stacked capacitor cup structure in accordance with an embodiment of the present invention.

100A‧‧‧Memory Cell Array Area

100P‧‧‧ surrounding area

110‧‧‧Semiconductor substrate

115‧‧‧Active components

120‧‧‧ dielectric layer

125‧‧‧Electrical contact

130‧‧‧ layer of tantalum nitride

135‧‧‧First dielectric layer

140‧‧‧ nitride layer

145‧‧‧Oxide layer

150‧‧‧矽 nitride layer

162‧‧‧ Conductive layer (TiN)

182‧‧‧high-k dielectric layer

184‧‧‧ Conductive layer (TiN)

186‧‧‧metal layer (tungsten)

195‧‧‧Dielectric Layer (TEOS)

M0‧‧‧ alignment mark

Claims (16)

A method of fabricating a stacked capacitor, comprising: providing a substrate having a memory cell array region and a peripheral region, wherein the memory cell array region comprises a plurality of capacitor stacked structures, the peripheral region having an alignment mark; forming a first dielectric layer is formed on the substrate; a stable stacked layer is formed on the first dielectric layer; and a second dielectric layer is formed on the stable stacked layer; Performing a first patterning step to form a plurality of capacitor openings in the memory cell array region and a trench surrounding the alignment mark; compliantly depositing a first electrode layer on the substrate and filling the plurality of capacitor openings On the inner side surface of the trench; depositing a third dielectric layer on the first electrode layer and covering the entire substrate, filling the capacitor opening and the inside of the trench; planarizing the third dielectric layer and removing An unnecessary third dielectric layer on the surface of the second dielectric layer; performing a second patterning step to pattern the second dielectric layer, defining a first opening to expose the surface of the capacitor opening and a second opening Expose the trench a surrounding region; sequentially removing the third dielectric layer exposed by the first and second openings and the yttrium oxide layer portion of the stable stacked layer; compliantly depositing a high-k dielectric layer and a a second electrode layer on the substrate and filling the inner surfaces of the plurality of capacitor openings and trenches; depositing a metal layer on the substrate and filling the plurality of capacitor openings An interior of the trench; patterning the metal layer to expose an open region of the peripheral region; removing the stable stacked layer and the first dielectric layer under the open region of the peripheral region, and exposing the alignment mark; A fifth dielectric layer is deposited on the substrate and filled into the open region of the peripheral region, and then the fifth dielectric layer is planarized. The method of manufacturing a stacked capacitor according to claim 1, wherein the first dielectric layer comprises a tetraethoxy silicate (TEOS). The method of manufacturing a stacked capacitor according to claim 1, wherein the second dielectric layer comprises a tantalum nitride layer. The method of manufacturing a stacked capacitor according to claim 1, wherein the first patterning step comprises: forming a carbon hard mask layer on the second dielectric layer of the stable stacked layer; forming a primary anti- Reflecting a coating on the carbon hard mask layer; and forming a patterned photoresist layer on the anti-reflective coating layer, thereby defining a plurality of openings corresponding to the capacitance locations in the memory cell array region and surrounding the alignment A groove of the mark is in the peripheral area. The method of manufacturing a stacked capacitor according to claim 1, wherein the first electrode layer and the second electrode layer are a titanium nitride (TiN) layer. The method of manufacturing a stacked capacitor according to claim 1, wherein the third dielectric layer comprises an ozone-tetraethoxy silicate (O-TEOS) layer. The method of manufacturing a stacked capacitor according to claim 1, wherein the second patterning step comprises: Forming a carbon hard mask layer on the second dielectric layer; forming an anti-reflective coating on the carbon hard mask layer; and forming a patterned photoresist layer on the anti-reflective coating layer, thereby defining A first opening corresponding to the position of the capacitor and a second opening above the alignment mark are provided. The method of manufacturing the stacked capacitor of claim 1, wherein sequentially removing the third dielectric layer exposed by the first and second openings and the yttrium oxide layer portion of the stable stacked layer comprises In a first stage, a portion of the ruthenium oxide layer is removed using a hydrofluoric acid buffered etch (BHF) solution, and the remaining portion of the ruthenium oxide layer is removed in a second stage using a dilute hydrofluoric acid (DHF) solution. The method of manufacturing a stacked capacitor according to claim 1, wherein the metal layer comprises metal tungsten. The method of manufacturing a stacked capacitor according to claim 1, wherein the fifth dielectric layer comprises a tetraethoxy phthalate (TEOS) layer. A stacked capacitor structure of a buried gate word line DRAM device includes: a substrate having a memory cell array region and a peripheral region, the peripheral region having an alignment mark; a first dielectric layer disposed on a stable stacked layer disposed on the first dielectric layer; a second dielectric layer on the stable stacked layer; and a plurality of stacked capacitor structures disposed on the memory cell array region and surrounding the barrier structure The alignment mark is disposed on the peripheral region; wherein the alignment mark on the peripheral region and the interior of the barrier structure are a transparent third dielectric layer. The stacked capacitor structure of the buried gate word line DRAM device of claim 11, wherein the first dielectric layer comprises a tetraethoxy phthalate (TEOS) layer. The stacked capacitor structure of the buried gate word line DRAM device according to claim 11, wherein the stable stacked layer comprises a tantalum nitride layer and a tantalum oxide layer. The stacked capacitor structure of the buried gate word line DRAM device according to claim 11, wherein the second dielectric layer comprises a tantalum nitride layer continuously surrounding the stacked capacitor structures. Opening. The stacked capacitor structure of the buried gate word line DRAM device according to claim 11, wherein the stacked capacitor structure comprises a first electrode layer, a high dielectric constant dielectric layer and a first Two electrode layers. The stacked capacitor structure of the buried gate word line DRAM device according to claim 11, wherein the transparent third dielectric layer comprises an ozone-tetraethoxy silicate (O-TEOS). )Floor.