TWI855295B - Method of manufacturing semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device includes: forming a hardmask layer on a semiconductor structure, in which the hardmask layer includes a first hollowed portion and a second hollowed portion; forming a photoresist layer over the hardmask layer and filling the first hollowed portion and the second hollowed portion; forming a first recess and a second recess on a side of the photoresist layer away from the semiconductor structure, in which the first recess and the second recess have different depths; and forming a first trench and a second trench with different depths extending to a conductor layer respectively in a first area and a second area of the semiconductor structure by the photoresist layer having the first recess and the second recess and by the first hollowed portion and the second hollowed portion of the hardmask layer.

Description

Method for manufacturing semiconductor device

The present disclosure relates to a method for manufacturing a semiconductor device.

There are usually several trenches on the top of the DRAM capacitor structure. These trenches are used to be filled with conductive materials in the subsequent process to become contact pillars, so these trenches are also called contact windows. Since the structure of the DRAM capacitor includes an array area and a peripheral area, and the conductor layers at the top of the DRAM capacitor structure are at different heights in the array area and the peripheral area, the depth of these contact windows must have different depths with the conductor layers at different heights. Such a structure is also called a multi-level contact window semiconductor structure.

However, in the current multi-layer contact window process, after a single trench etching step, it is easy to cause the trench with a required shallow depth to be etched too deep and remove a portion of the conductive layer, and the trench with a required deep depth to be etched too shallow and does not reach the conductive layer and consumes too much conductive layer. Such an etching process results in unsatisfactory performance of DRAM capacitors. Although it is possible to etch separately for contact windows with different required depths, for example, the trench with a required deep depth can be etched first, and the trench with a required shallow depth can be etched after adjusting the relevant parameters. However, separating the etching process will prolong the manufacturing process time and affect the production efficiency of semiconductor components.

Therefore, how to propose a method for manufacturing a semiconductor device, especially a method for manufacturing a semiconductor device suitable for a multi-layer contact window, is one of the problems that the industry is eager to invest research and development resources to solve.

In view of this, one purpose of the present disclosure is to provide a method for manufacturing a semiconductor device that can solve the above-mentioned problems.

To achieve the above-mentioned purpose, according to one embodiment of the present disclosure, a method for manufacturing a semiconductor element includes: forming a hard mask layer on a semiconductor structure, wherein the hard mask layer has a first hollow portion and a second hollow portion, the semiconductor structure includes a dielectric layer, a conductor layer and a stacked structure stacked in sequence, the semiconductor structure has a first region and a second region respectively located below the first hollow portion and the second hollow portion, and the portion of the conductor layer in the first region and the portion in the second region are opposite to each other. The distances of the hard mask layer are different; a photoresist layer is formed above the hard mask layer and fills the first hollow portion and the second hollow portion; a first recess and a second recess are formed on a side of the photoresist layer far away from the semiconductor structure, wherein the first recess and the second recess have different depths; and a first trench and a second trench with different depths are formed in a first area and a second area respectively by using the photoresist layer with the first recess and the second recess and the first hollow portion and the second hollow portion of the hard mask layer to extend to the conductor layer.

In one or more embodiments of the present disclosure, the step of forming a hard mask layer on the semiconductor structure is to form the hard mask layer on the dielectric layer.

In one or more embodiments of the present disclosure, in the step of forming a hard mask layer on the semiconductor structure, a distance between a portion of the conductive layer in the first region and the hard mask layer is greater than a distance between a portion of the conductive layer in the second region and the hard mask layer.

In one or more embodiments of the present disclosure, the step of forming a photoresist layer on the hard mask layer and filling the first hollow portion and the second hollow portion utilizes a coating process.

In one or more embodiments of the present disclosure, the step of forming the first recess and the second recess on the side of the photoresist layer away from the semiconductor structure is to completely remove the photoresist layer in the first hollow portion.

In one or more embodiments of the present disclosure, the step of forming the first recess and the second recess on the side of the photoresist layer away from the semiconductor structure utilizes an exposure process and a development process.

In one or more embodiments of the present disclosure, a first trench and a second trench having different depths are formed in a first area and a second area respectively by using a photoresist layer having a first recess and a second recess and a first hollow portion and a second hollow portion of a hard mask layer, and the steps of extending to a conductive layer are performed so that the first recess has a first depth and the second recess has a second depth, the first trench has a third depth and the second trench has a fourth depth.

In one or more embodiments of the present disclosure, the first depth is greater than the second depth, and the third depth is greater than the fourth depth, so that in the step of using the first hollow portion and the second hollow portion of the photoresist layer having the first recess and the second recess and the hard mask layer to form the first trench and the second trench with different depths in the first area and the second area respectively, extending to the conductor layer, the first trench and the second trench substantially expose the conductor layer at the same time.

In one or more embodiments of the present disclosure, the step of forming first trenches and second trenches with different depths in the first area and the second area respectively by using the photoresist layer having the first recess and the second recess and the first hollow portion and the second hollow portion of the hard mask layer to extend to the conductor layer is to expose the conductor layer.

In one or more embodiments of the present disclosure, the step of using a photoresist layer having a first recess and a first recess and a second recess of a hard mask layer to form a first trench and a second trench with different depths in a first area and a second area respectively, extending to a conductive layer, is performed by an etching process.

In summary, in the manufacturing method of the semiconductor device disclosed in the present invention, since the portions of the photoresist layer above the first region, the second region, and the third region are exposed and developed with different doses, the photoresist layer can have first recesses, second recesses, and third recesses of different depths above the first region, the second region, and the third region, respectively. In addition, in the manufacturing method of the semiconductor device disclosed in the present invention, since the photoresist layer having first recesses, second recesses, and third recesses of different depths is formed on the hard mask layer above the semiconductor structure, respectively, the first trenches, second trenches, and third trenches of different depths can be etched simultaneously in the first region, the second region, and the third region of the semiconductor structure during the subsequent etching process, and the first trenches, the second trenches, and the third trenches are formed to reach the conductive layer at the same time. By executing the manufacturing method of the semiconductor element disclosed in the present invention, not only can a semiconductor element with a better quality contact window be manufactured, but it also saves more time than the previous technology, thereby improving the production efficiency of the semiconductor element.

The above description is only used to explain the problem to be solved by the present disclosure, the technical means for solving the problem, and the effects produced, etc. The specific details of the present disclosure will be introduced in detail in the following implementation methods and related drawings.

The following will disclose multiple embodiments of the present disclosure with drawings. For the purpose of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. In other words, in some embodiments of the present disclosure, these practical details are not necessary. In addition, in order to simplify the drawings, some commonly used structures and components will be depicted in the drawings in a simple schematic manner. The same reference numerals will be used to represent the same or similar components in all drawings.

Spatially relative terms (e.g., "below," "beneath," "beneath," "above," "on," and related terms) are used herein to simply describe the relationship of an element or feature as shown in the figure to another element or feature. These spatially relative terms encompass different orientations of the device in use or operation in addition to the orientation shown in the figure. Furthermore, these devices may be rotated (90 degrees or other angles), and the spatially relative descriptors used herein may be interpreted accordingly. In addition, the term "made of" may mean "comprising" or "consisting of."

Please refer to FIG. 1, which is a flow chart of a method M for manufacturing a semiconductor device according to an embodiment of the present disclosure. As shown in FIG. 1, the method M for manufacturing a semiconductor device includes step S10, step S12, step S14, and step S16. When describing step S10, step S12, step S14, and step S16 in FIG. 1 in detail, please refer to FIGS. 2 to 6 at the same time.

Before describing the manufacturing method M of the semiconductor device in detail, please refer to FIG. 2. FIG. 2 provides a semiconductor structure 100. The semiconductor structure 100 includes a stacking structure 110, a conductive layer 120A, a conductive layer 120B, and a conductive layer 120C disposed on the stacking structure 110, and a dielectric layer 130A, a dielectric layer 130B, and a dielectric layer 130C disposed on the conductive layer 120A, the conductive layer 120B, and the conductive layer 120C. In more detail, the semiconductor structure 100 includes a first region A1, a second region A2, and a third region A3. In the first region A1, the dielectric layer 130A is located above the conductive layer 120A. In the second area A2, the conductor layer 120B is located above the stacked structure 110, and the dielectric layer 130B is located above the conductor layer 120B. In the third area A3, the conductor layer 120C is located above the stacked structure 110, and the dielectric layer 130C is located above the conductor layer 120C. In this embodiment, the tops of the dielectric layer 130A, the dielectric layer 130B, and the dielectric layer 130C are coplanar.

It should be noted that, in the present embodiment, the stacking structure 110 is included below the conductive layer 120A in the first area A1. However, for the sake of simplicity, the stacking structure 110 is omitted in the first area A1 shown in FIGS. 2 to 6. In addition, in the present embodiment, the conductive layer 120A, the conductive layer 120B, and the conductive layer 120C are portions of one conductive layer in the first area A1, the second area A2, and the third area A3, respectively, so the conductive layer 120A, the conductive layer 120B, and the conductive layer 120C actually belong to the same conductive layer. In addition, in the present embodiment, the dielectric layer 130A, the dielectric layer 130B, and the dielectric layer 130C are portions of a dielectric layer in the first area A1, the second area A2, and the third area A3, respectively. Therefore, the dielectric layer 130A, the dielectric layer 130B, and the dielectric layer 130C actually belong to the same dielectric layer.

In this embodiment, as shown in FIG. 2 , the stack structure 110 has different heights in the first area A1, the second area A2, and the third area A3, so that the conductive layer 120A, the conductive layer 120B, and the conductive layer 120C are not on the same horizontal plane in the first area A1, the second area A2, and the third area A3.

In some embodiments, the stacked structure 110 may be, for example, a semiconductor structure used to form a dynamic random access memory (DRAM), but the present disclosure is not limited thereto. In some embodiments, the stacked structure 110 may be any semiconductor stacked structure including one or more conductive materials, one or more dielectric materials, or a combination thereof.

In some embodiments, the materials of the conductive layer 120A, the conductive layer 120B, and the conductive layer 120C may be tungsten, polysilicon, or any other suitable material. The present disclosure is not intended to limit the materials of the conductive layer 120A, the conductive layer 120B, and the conductive layer 120C.

In some embodiments, the conductive layer 120A, the conductive layer 120B, and the conductive layer 120C may be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, etc. The present disclosure is not intended to limit the method of forming the conductive layer 120A, the conductive layer 120B, and the conductive layer 120C.

In some embodiments, the materials of the dielectric layer 130A, the dielectric layer 130B, and the dielectric layer 130C may be oxides, low-k materials, or any other suitable materials. The present disclosure is not intended to limit the materials of the conductive layer dielectric layer 130A, the dielectric layer 130B, and the dielectric layer 130C.

In some embodiments, the dielectric layer 130A, the dielectric layer 130B, and the dielectric layer 130C may be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, etc. The present disclosure is not intended to limit the method of forming the dielectric layer 130A, the dielectric layer 130B, and the dielectric layer 130C.

In some embodiments, the tops of dielectric layer 130A, dielectric layer 130B, and dielectric layer 130C may be made coplanar by, for example, chemical mechanical planarization (CMP). Alternatively, in some embodiments, the tops of dielectric layer 130A, dielectric layer 130B, and dielectric layer 130C may be made coplanar by etching or any suitable method. The present disclosure is not intended to limit the method of making the tops of dielectric layer 130A, dielectric layer 130B, and dielectric layer 130C coplanar.

The operations of step S10, step S12, step S14 and step S16 are described in detail below.

First, step S10 is performed: forming a hard mask layer HM on the semiconductor structure 100.

Referring to FIG. 3 , the hard mask layer HM is formed on the first area A1, the second area A2, and the third area A3 of the semiconductor structure 100. More specifically, the hard mask layer HM is located on the dielectric layer 130A, the dielectric layer 130B, and the dielectric layer 130C. As shown in FIG. 3 , the hard mask layer HM has a hollow portion O1, a hollow portion O2, and a hollow portion O3. The hollow portion O1, the hollow portion O2, and the hollow portion O3 are respectively located on the first area A1, the second area A2, and the third area A3 and correspond to the conductive layer 120A, the conductive layer 120B, and the conductive layer 120C, respectively. In other words, the hard mask layer HM disclosed in the present invention is a patterned hard mask layer HM.

In some implementations, the hard mask layer HM may be a material such as polysilicon, silicon nitride ( _SixNy ), silicon oxide ( _SixOy ), or silicon nitride ( _TiN ). The present disclosure is not intended to limit the material of the hard mask layer _HM .

In some embodiments, the hard mask layer HM can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, etc. The present disclosure is not intended to limit the method of forming the hard mask layer HM.

In some implementations, as shown in FIG. 3 , the hollow portion O1, the hollow portion O2, and the hollow portion O3 are located directly above the conductive layer 120A, the conductive layer 120B, and the conductive layer 120C, respectively.

In some implementations, the hollow portions O1, O2, and O3 may be formed by, for example, lithography or other possible etching methods. The present disclosure is not intended to limit the method of patterning the hard mask layer HM.

In some implementations, the hollow portion O1, the hollow portion O2, and the hollow portion O3 have the same critical dimension (CD). The critical dimension here can be simply understood as the width of the hollow portion O1, the hollow portion O2, and the hollow portion O3.

In some embodiments, as shown in FIG. 3 , the number of each of the hollow portion O1, the hollow portion O2, and the hollow portion O3 is one, which is for the sake of simplicity. In fact, the number of the hollow portion O1, the hollow portion O2, and the hollow portion O3 can be plural. Therefore, the present disclosure is not intended to limit the number of the hollow portion O1, the hollow portion O2, and the hollow portion O3.

Next, step S12 is performed: forming a photoresist layer PR on the hard mask layer HM and filling the hollow portions O1, O2 and O3.

4 , the photoresist layer PR is formed on the hard mask layer HM and crosses the first area A1, the second area A2, and the third area A3 of the semiconductor structure 100. In some embodiments, the photoresist layer PR completely covers the hard mask layer HM. In some embodiments, the photoresist layer PR covers the hard mask layer HM so that the photoresist layer PR completely fills the hollow portions O1, the hollow portions O2, and the hollow portions O3 of the hard mask layer HM.

In some embodiments, as shown in FIG. 4 , the photoresist layer PR has the same thickness over the first area A1, the second area A2, and the third area A3. Specifically, the side of the photoresist layer PR away from the hard mask layer HM is flat. However, the present disclosure is not intended to limit the thickness of the photoresist layer PR over the first area A1, the second area A2, and the third area A3.

In some embodiments, the photoresist layer PR is formed on the hard mask layer HM by a coating process and fills the hollow portions O1, O2, and O3, but the present disclosure is not limited thereto. In some embodiments, the photoresist layer PR can be formed on the hard mask layer HM by other suitable methods and fills the hollow portions O1, O2, and O3.

Next, step S14 is performed: a first recess R1, a second recess R2 and a third recess R3 are formed on a side of the photoresist layer PR away from the semiconductor structure 100.

Referring to FIG. 5 , the photoresist layer PR is removed above the first area A1, the second area A2, and the third area A3. More specifically, as shown in FIG. 5 , the photoresist layer PR is removed to form a first recess R1, a second recess R2, and a third recess R3 above the first area A1, the second area A2, and the third area A3, respectively. The first recess R1 has a first depth da, the second recess R2 has a second depth db, and the third recess R3 has a third depth dc.

In some embodiments, the photoresist layer PR is removed by an exposure process and a development process at a side away from the semiconductor structure 100. More specifically, the photoresist layer PR is removed by an exposure process and a development process to form a first recess R1, a second recess R2, and a third recess R3 on the first area A1, the second area A2, and the third area A3. For example, the portions of the photoresist layer PR located above the first area A1, the second area A2, and the third area A3 may be exposed with different doses, respectively, wherein the dose used in the portion of the photoresist layer PR located above the first area A1 is greater than the dose used in the portion of the photoresist layer PR located above the second area A2, and the dose used in the portion of the photoresist layer PR located above the second area A2 is greater than the dose used in the portion of the photoresist layer PR located above the third area A3.

Next, for example, the portions of the photoresist layer PR located above the first area A1, the second area A2, and the third area A3 are developed respectively to form a first recess R1, a second recess R2, and a third recess R3 on the photoresist layer PR respectively.

The above is only an example for simple explanation, and the present disclosure is not intended to limit the method of forming the first recess R1, the second recess R2 and the third recess R3 on the side of the photoresist layer PR away from the semiconductor structure 100.

In some implementations, the first depth da is greater than the second depth db, and the second depth db is greater than the third depth dc.

In some embodiments, as shown in FIG. 5 , the photoresist layer PR forms a first recess R1 above the first region A1 , so that the photoresist layer PR in the hollow portion O1 is completely removed. However, the present disclosure is not intended to be limited thereto.

In some embodiments, as shown in FIG. 5 , the photoresist layer PR forms a second recess R2 above the second area A2, so that the hollow portion O2 is partially filled with the photoresist layer PR. However, the present disclosure is not intended to be limited thereto.

In some embodiments, as shown in FIG. 5 , the photoresist layer PR forms a third recess R3 above the third area A3 , so that the hollow portion O3 is still completely filled with the photoresist layer PR. However, the present disclosure is not intended to be limited thereto.

Next, perform step S16: use the hollow portions O1, O2 and O3 of the photoresist layer PR and the hard mask layer HM having the first recess R1, the second recess R2 and the third recess R3 to respectively form the first trench T1, the second trench T2 and the third trench T3 with different depths in the first area A1, the second area A2 and the third area A3, extending to the conductive layer 120A, the conductive layer 120B and the conductive layer 120C.

Referring to FIG. 6 , the semiconductor structure 100 includes a first trench T1, a second trench T2, and a third trench T3. As shown in FIG. 6 , the first trench T1, the second trench T2, and the third trench T3 of the semiconductor structure 100 pass through the dielectric layer 130A, the dielectric layer 130B, and the dielectric layer 130C and are connected to the conductive layer 120A, the conductive layer 120B, and the conductive layer 120C, respectively.

In step S16, as shown in FIG. 6, the photoresist layer PR having the first recess R1, the second recess R2 and the third recess R3 is used to completely remove the photoresist layer PR in the hollow portion O1, the hollow portion O2 and the hollow portion O3. Then, the hollow portion O1, the hollow portion O2 and the hollow portion O3 are used to form the first trench T1, the second trench T2 and the third trench T3 in the dielectric layer 130A, the dielectric layer 130B and the dielectric layer 130C, respectively. In addition, as shown in FIG. 6, step S16 is performed so that the first trench T1, the second trench T2 and the third trench T3 have a fourth depth dd, a fifth depth de and a sixth depth df, respectively. The fourth depth dd, the fifth depth de, and the sixth depth df are the depths of the first trench T1, the second trench T2, and the third trench T3 in the dielectric layer 130A, the dielectric layer 130B, and the dielectric layer 130C, respectively. In the present embodiment, the fourth depth dd, the fifth depth de, and the sixth depth df are defined as the distances from the top surfaces of the dielectric layer 130A, the dielectric layer 130B, and the dielectric layer 130C to the top surfaces of the conductive layer 120A, the conductive layer 120B, and the conductive layer 120C, respectively.

In this embodiment, the first trench T1, the second trench T2 and the third trench T3 can be formed in the first area A1, the second area A2 and the third area A3 respectively by an etching process using the hollow portions O1, O2 and O3 of the photoresist layer PR having the first recess R1, the second recess R2 and the third recess R3 and the hard mask layer HM.

In some implementations, as shown in FIG. 6 , the etching process completely removes the photoresist layer PR in the hollow portion O1, the hollow portion O2, and the hollow portion O3, and simultaneously removes a portion of the photoresist layer PR on the top surface of the hard mask layer HM.

In some embodiments, as shown in FIG. 6 , the etching process simultaneously etches the dielectric layer 130A, the dielectric layer 130B, and the dielectric layer 130C through the patterned hard mask layer HM to simultaneously form the first trench T1, the second trench T2, and the third trench T3. More specifically, the first trench T1, the second trench T2, and the third trench T3 formed by the etching process simultaneously reach the conductive layer 120A, the conductive layer 120B, and the conductive layer 120C and simultaneously expose the conductive layer 120A, the conductive layer 120B, and the conductive layer 120C. It should be particularly noted that the etching is performed to expose the conductive layer 120A, the conductive layer 120B, and the conductive layer 120C at the same time so that no part of the conductive layer 120A, the conductive layer 120B, and the conductive layer 120C is removed in step S16 and remains intact.

In the present embodiment, the first trench T1, the second trench T2, and the third trench T3 may be formed by anisotropic etching (e.g., dry etching) or other etching methods, but the present disclosure is not limited thereto. In some embodiments, the first trench T1, the second trench T2, and the third trench T3 may be formed by isotropic etching (e.g., wet etching) or other etching methods. The present disclosure is not intended to limit the formation method of the first trench T1, the second trench T2, and the third trench T3.

In some embodiments, step S16 can be performed by first performing a chemical mechanical planarization process and then performing an etching process to form the first trench T1, the second trench T2, and the third trench T3. For example, the chemical mechanical planarization process can be used to simultaneously remove the photoresist layer PR located above the first area A1, the second area A2, and the third area A3 on the top surface of the hard mask layer HM. Then, the etching process is used to completely remove the photoresist layer PR in the hollow portion O1, the hollow portion O2, and the hollow portion O3. Then, the etching process is continued to form the first trench T1, the second trench T2 and the third trench T3 in the dielectric layer 130A, the dielectric layer 130B and the dielectric layer 130C through the hollow portion O1, the hollow portion O2 and the hollow portion O3 respectively, and extend to the conductive layer 120A, the conductive layer 120B and the conductive layer 120C.

It should be noted that the above is only an example, and the present disclosure is not intended to limit the number and sequence of the method or process for executing step S16.

By executing the above steps S10, S12, S14 and S16, the manufacturer can use the semiconductor device manufacturing method M to manufacture the semiconductor device of the semiconductor structure 100 disclosed herein having the first trench T1, the second trench T2 and the third trench T3 of different depths.

From the above detailed description of the specific implementation method of the present disclosure, it can be clearly seen that in the manufacturing method of the semiconductor element disclosed in the present disclosure, since the portions of the photoresist layer above the first area, the second area and the third area are exposed and developed with different doses, the photoresist layer can have first recesses, second recesses and third recesses of different depths above the first area, the second area and the third area, respectively. In addition, in the manufacturing method of the semiconductor element disclosed in the present invention, since the photoresist layer with the first recess, the second recess and the third recess of different depths are formed on the hard mask layer located above the semiconductor structure, the first trench, the second trench and the third trench with different depths can be etched in the first area, the second area and the third area of the semiconductor structure at the same time when the etching process is performed later, and the first trench, the second trench and the third trench are formed to reach the conductive layer at the same time. By performing the manufacturing method of the semiconductor element disclosed in the present invention, not only can a semiconductor element with a better quality contact window be manufactured, but it can also save more time compared to the previous technology, thereby improving the production efficiency of the semiconductor element.

The above content summarizes the features of several implementation methods so that those familiar with this technology can better understand the state of this case. Those familiar with this technology should understand that without departing from the spirit and scope of this case, the above content can be easily used as a basis for designing or modifying other changes to implement the same purpose and/or achieve the same advantages of the implementation methods introduced in this article. The above content should be understood as an example of this disclosure, and its protection scope should be based on the scope of the patent application.

100: semiconductor structure 110: stacked structure 120A, 120B, 120C: conductor layer 130A, 130B, 130C: dielectric layer A1: first region A2: second region A3: third region da: first depth db: second depth dc: third depth dd: fourth depth de: fifth depth df: sixth depth HM: hard mask layer M: method O1, O2, O3: hollow part P: grinding part PR: photoresist layer R1: first recess R2: second recess R3: third recess S10, S12, S14, S16: steps T1: first trench T2: second trench T3: third trench

In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more clearly understandable, the attached drawings are described as follows: FIG. 1 is a flow chart showing a method for manufacturing a semiconductor element according to an embodiment of the present disclosure. FIG. 2 is a schematic diagram showing a manufacturing stage of a method for manufacturing a semiconductor element according to an embodiment of the present disclosure. FIG. 3 is a schematic diagram showing a manufacturing stage of a method for manufacturing a semiconductor element according to an embodiment of the present disclosure. FIG. 4 is a schematic diagram showing a manufacturing stage of a method for manufacturing a semiconductor element according to an embodiment of the present disclosure. FIG. 5 is a schematic diagram showing a manufacturing stage of a method for manufacturing a semiconductor element according to an embodiment of the present disclosure. FIG. 6 is a schematic diagram showing a manufacturing stage of a method for manufacturing a semiconductor element according to an embodiment of the present disclosure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

M: Manufacturing method of semiconductor element

S10, S12, S14, S16: Steps

Claims (8)

A method for manufacturing a semiconductor element comprises: forming a hard mask layer on a semiconductor structure, wherein the hard mask layer has a first hollow portion and a second hollow portion, the semiconductor structure comprises a dielectric layer, a conductor layer and a stacked structure stacked in sequence, the semiconductor structure has a first region and a second region respectively located below the first hollow portion and the second hollow portion, and the position of the conductor layer in the first region and the position of the conductor layer in the second region are at different distances from the hard mask layer; forming a photoresist layer above the hard mask layer and filling the first hollow portion and the second hollow portion; utilizing an exposure process and a The developing process forms a first recess and a second recess on a side of the photoresist layer away from the semiconductor structure, wherein the exposure process exposes the portions of the photoresist layer located above the first region and the second region with different doses, so that the first recess and the second recess have different depths; and an etching process is performed, using the photoresist layer having the first recess and the second recess and the first hollow portion and the second hollow portion of the hard mask layer to form a first trench and a second trench with different depths at different portions of the first region and the second region of the dielectric layer, respectively, and simultaneously expose a top surface of the conductor layer. The method as described in claim 1, wherein the step of forming the hard mask layer on the semiconductor structure is to form the hard mask layer on the dielectric layer. The method as described in claim 1, wherein in the step of forming the hard mask layer on the semiconductor structure, the distance between the portion of the conductive layer in the first region and the hard mask layer is greater than the distance between the portion of the conductive layer in the second region and the hard mask layer. The method as described in claim 1, wherein the step of forming the photoresist layer above the hard mask layer and filling the first hollow portion and the second hollow portion utilizes a coating process. The method as described in claim 1, wherein the step of forming the first recess and the second recess on the side of the photoresist layer away from the semiconductor structure is to completely remove the photoresist layer in the first hollow portion. The method as described in claim 1, wherein the step of using the photoresist layer having the first recess and the second recess and the first hollow portion and the second hollow portion of the hard mask layer to form the first trench with different depths in the first region and the second region respectively and the second trench extending to the conductor layer makes the first recess have a first depth and the second recess have a second depth, the first trench has a third depth and the second trench has a fourth depth. The method as described in claim 6, wherein the first depth is greater than the second depth, and the third depth is greater than the fourth depth, so that in the step of using the photoresist layer having the first recess and the second recess and the first hollow portion and the second hollow portion of the hard mask layer to form the first trench and the second trench with different depths in the first region and the second region respectively, extending to the conductor layer, the first trench and the second trench substantially expose the conductor layer at the same time. The method as described in claim 1, wherein the step of using the photoresist layer having the first recess and the second recess and the first hollow portion and the second hollow portion of the hard mask layer to form the first trench and the second trench having different depths in the first region and the second region respectively extending to the conductor layer is to expose the conductor layer.

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