TWI375320B - Image sensor and manufacturing method thereof - Google Patents

Description

1375320 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device for converting an optical image into an electrical signal, and more particularly to an image sensor. The image sensor is roughly classified into a charge coupled device (CCD) image sensor or a complementary metal oxide semiconductor (CMOS) image CMOS image sensor (CIS). [Prior Art] Generally, the photodiode system of the image sensor is formed by ion implantation on a substrate having a readout circuit. However, in order to increase the number of pixels and not to increase the size of the wafer, the size of the photodiode is reduced more and more, and the area of the light receiving portion is also reduced, so that the image quality is lowered. Further, since the stack height is not as much as that of the area of the light receiving portion, the number of photons incident on the light receiving portion is also reduced by the light scattering called an airy disk. As an alternative to overcome this limitation, the industry has attempted to form a photodiode using amorphous silicon (Si), or to form a readout circuit in a Shih-hsien substrate and to use, for example, a j- (wafer t〇wafer) The bonding method forms a photodiode on the sell circuit (referred to as a three-dimensional (3D) image sensor). The photodiode is connected to the readout circuit through a metal wire. According to the prior art, the device isolation between the elements is not fully realized. The image sensor of the technology is likely to generate leakage current due to peripheral factors such as line and temperature, which may cause dark current. Further, according to the conventional technique, since the source and the difficulty of transferring the transistor are largely doped with N-type impurities, the charge sharing ((4)e-η8) shown in Fig. 19 appears. #充分享县出麟, lose (4) the image is reduced and can produce image errors. Further, according to the prior art, since photocharge does not rapidly move between the photodiode and the readout circuit, dark current is generated, or saturation and sensitivity are lowered. SUMMARY OF THE INVENTION The present invention is a method for producing a solid paste. The embodiment provides an image sensor, which may include: a first substrate including a pixel portion for providing an output circuit and a peripheral portion for providing a peripheral circuit; and a dielectric layer on the first substrate, and the interlayer is connected Age (4) (2) Connect (4) the first road - the line and the sound. Ray < a line; a crystalline semiconductor layer, located in a portion of the corresponding layer of the m-pole and the second photodiode, located in the crystalline semiconductor Γ first =: body and the second first dipole through the device isolation trench Slot: The body and the first light and one pole are respectively connected to a 1 isolation layer, which is located on the side of the package (4). The dragon on the device is mounted on the crystalline semiconductor layer, such as the connection of the shirt-light: 1 layer of the upper layer of the layer The exposed portion selectively exposes a region above the first photodiode, and a purification layer; a first substrate upper body 1375320 on which the exposed portion is provided. In another embodiment, the dummy element can be supplied to the wafer. The edge of the ministry - at the office. This virtual element can be used for testing. In addition, a method for manufacturing an image sensor includes: forming a readout circuit on a pixel of a first substrate and a peripheral circuit on a peripheral portion of the first substrate; forming an interlayer dielectric layer on the first substrate; The dielectric layer comprises a first connection to the readout circuit: * a second line connecting the circuit and the chopped line; forming a second substrate comprising the crystalline semiconductor layer; forming a photodiode layer in the crystalline semiconductor layer; bonding the first Substrate and a second substrate comprising: a crystalline semiconductor layer; removing a portion of the first substrate to expose a light body on the first substrate; forming a device isolation trench in the crystalline semiconductor layer, separating an area of the photodiode layer Forming a first photodiode and a second photodiode respectively connected to the first line; forming a device isolation layer on the crystalline semiconductor layer including the device isolation trench; forming an upper electrode layer on the device isolation layer, such that the upper electrode Connecting a portion of the first photodiode; removing a portion of the upper electrode layer to form an exposed portion, selectively exposing an upper portion of the first photodiode; and forming a blunt • layer is formed on the exposed portion of the dielectric layer of the interlayer. The details of one or more of the embodiments are illustrated in the drawings and the description below. Other features will be apparent from the embodiments, drawings, and claims. [Embodiment] Embodiments of a method of manufacturing an image sensor will now be described with reference to the accompanying drawings. Fig. 16 is a cross-sectional view showing the image sensor of the embodiment. The image sensor may include: a first substrate 100 including a pixel portion A' having a readout circuit 9 1375320 (10) and a peripheral portion b having a cap formed with a peripheral circuit; an interlayer dielectric layer 160 formed on On the first substrate 1 ,, the line 15 〇 is connected to the readout circuit and the line 170 is connected to the peripheral circuit; the crystalline semiconductor layer is located on a portion of the interlayer dielectric layer (10) corresponding to the pixel portion A; the first photodiode 2 The 〇5 and the second photodiode 20 are formed in the crystalline semiconductor layer, and are separated from the mother-early opacity by the device isolation region (refer to "8th figure"), and are connected to the lines (9) and 15 respectively.装置a; a device isolation layer 250 is formed on the germanium-like semiconductor layer 200 including the device isolation region 235; the upper electrode layer 26〇 penetrates the device isolation layer 25〇 to connect a portion of the H-th apology portion 265, formed in The upper electrode layer ·t selectively exposes the upper portion of the second body 2〇5; and the purification layer 27〇' is formed on the first substrate 1〇〇 and is included in the exposed portion 265. The first photodiode 205 can be a main pixel, and is electrically connected to the upper electrode layer 26G through the first through hole 2 to perform a substantial operation. The second photodiode can be a dummy element that is not connected to the upper electrode layer. Since the second photodiode 2^5a used as a dummy pixel can exclude the leakage factor of the upper electrode layer, it can be used as a reference element for measuring the fine current. For example, the nth (four) 5a is provided in the edge region of the wafer. The first passivation layer 270 and the second passivation layer 28 may be placed on the first substrate, and the upper electrode layer 26 is formed on the first substrate. The first passivation layer is formed on the device isolation layer 25A through the first exposed portion 265 of the upper electrode layer 260. A device isolation layer 250 may be formed in the crystalline semiconductor layer 2 to isolate the first photodiode 205 of each single 1375320 element. In addition, the first passivation layer 270 and the second passivation layer 280 may be formed on the interlayer dielectric layer 160 on which the crystalline semiconductor layer 20 is formed to protect the lines of the first photodiode 205 and the peripheral portion B. 170. Reference numerals not explained in Fig. 16 are explained in the following manufacturing methods. The following is a combination of "1st", "2nd", "3rd", "4th", "5th", "6th", "7th", "8th", "Picture 9", "1", "1", "12", "13", "14", "15" and "16" A method of fabricating an image sensor of an embodiment is described. Referring to "Fig. 1", the readout circuits and lines 150 and 150a can be formed on the pixel portion A of the first substrate 100. The first substrate 100 may be a single crystal or polycrystalline substrate, and may be a substrate doped with p-type impurities or n-impurities. The device isolation region 110 may be formed in the first substrate 100 to define an active region. A readout circuit 12 of a transistor including each unit pixel can be formed in the active region. The readout circuit 12A and the line 15A are described in detail in conjunction with "Fig. 2". Referring to "FIG. 2", the readout circuit 12A may include a transfer transistor Tx 121, a reset transistor Rx 123, a drive transistor Dx 125, and a selection transistor Sx 127. After forming the gate of the transistor, an ion implantation region including the floating diffusion regions 171) 131 and the source/drain regions 133, 135, and 137 of the respective transistors can be formed. Meanwhile, in different embodiments, the readout circuit 120 can be a three-transistor (3Tr), a four-electrode 11 1375320 body (four turns and five transistors (where _, wherein the three transistors comprise a reset transistor Rx, Driving the transistor Dx and selecting the transistor Sx, the five transistors include the transfer transistor Tx, the reset transistor Rx, the drive transistor Dx, the selection transistor & and the address read transistor. (10) The base includes an alkali electrical junction region 140 in the first substrate lion, and a first conductive type connection region 147 forming a connection line (9) on the electrical junction region 14A. For example, the electrical junction region 140 can be a pN connection. For example, the electrical junction region 140 may include a __ conductivity type ion implant layer 143 formed on the second conductive type i4i (or the second conductive type worm layer), and formed The second conductive f-ion implant layer 45 on the first conductive flip implant layer 143, for example, the PN junction, may be the second conductive type ion implantation layer 145 (PO) shown in FIG. A conductive type ion implantation layer 143 (Ν·) / second conductivity type well 141 (Ρ-) junction, but is not limited thereto. In one embodiment, the first substrate 100 may be doped with impurities of the second conductivity type. According to an embodiment, the device is designed to transfer the source and the drain of the transistor There is a potential difference between them so that the photocharge can be completely dumped. Therefore, since the photocharge generated by the photodiode is completely dumped to the floating diffusion region, the sensitivity of the output image can be increased. That is, according to an embodiment, electrical The junction region 140 is formed on the first substrate towel formed with the readout circuit 120 to allow the source and the secret α of the side surface 12 of the transfer transistor Txm to be subjected to a check, so that the money shot is completely dumped. The photocharge dump structure of the embodiment Q The node of the floating diffusion region FD 131 is an N+ junction, and the difference between the PNp and the faceplate is that the Wei junction area is not completely transmitted to this, PNP P/N The /P junction is clamped when the voltage is dare. This voltage is called the stop voltage - ge) 'depends on the second conductivity type ion implantation layer i45 (p〇 region) and the first conductivity type lion implant layer 143 (N Rhyme) When the power transfer crystal 121 is turned on, the electronic machine to electrical junction region 14 () (the junction) generated by the first photodiode 2〇5 is transferred to the node of the floating diffusion layer FD 131 and converted into a voltage. Because the maximum voltage value of the electrical junction area 140 (P_/p_ junction) becomes the clamping voltage ['the maximum voltage value of the node of the floating diffusion FD 131 becomes the threshold voltage Vth of the reset transistor Rx 123, such as As shown in Fig. 18, by transferring the potential difference between the sides of the transistor τ χ 121, electrons generated by the first photodiode 2 〇 5 in the upper portion of the wafer can be completely dumped to the node of the floating diffusion FD 131, Charge sharing will occur. That is, according to an embodiment, during a reset operation of a four-transistor (4_Tr) active pixel sensor (APS), the ρ〇/Ν /ρ well junction is not a Ν+/Ρ-well A junction is formed in the first substrate to allow a + voltage to be applied to the first conductivity type ion implant layer 143 (N_region) of the well interface, and to allow a ground voltage to be applied to the second conductivity type ion implantation layer 145 (p〇) and the second conductivity type well 141 (P-well)' are clamped at a predetermined voltage and are generated at the P0/N-/P-well double junction 13 1375320 face 'or more in the double carrier In the structure of a bipolar junction transistoi (.BJT). This is called the pinch voltage. Therefore, during the turn-on/off operation of the transfer transistor Tx, a potential difference is generated between the source and the drain of the transfer transistor Tx 121, and all of the photocharge from the Ν-well is transferred to the floating diffusion through the transfer transistor. FD 131, thereby suppressing charge sharing. * Therefore, the example in which the 二+ junction is simply connected to the photodiode in the prior art does not have the limitation of, for example, saturation reduction and sensitivity reduction. • The next 'first conductivity type connection region 147 can be formed between the photodiode and the readout circuitry to provide a fast path of motion of the photocharge such that the source of dark current is minimized' reduced saturation and reduced sensitivity can be suppressed. To this end, according to an embodiment, an n+ disturbing region such as the first conductive type connection region 147 for ohmic contact may be formed on the electrical junction region 14 (Ρ0/Ν-/Ρ-junction). The first conductive type connection region 147 may be formed to penetrate the second conductive type ion implantation layer 145 (?0) to contact the first conductive type ion implantation layer 143 (Ν-region). • In the meantime, in order to suppress the first conductive type connection region 147 from becoming a leak source, the width of the first conductive type connection region 147 can be minimized. To this end, in one embodiment, a plug implant can be completed after a through hole is first created for the first metal contact 151a. In another embodiment, an ion implantation pattern (not shown) can be formed. Then the first conductivity type connection region 147 can be formed using an ion implantation pattern as an ion implantation mask. 14 1375320 That is to say, this implementation uses N-type impurities locally and in large quantities to only disturb the formation of the ohmic contact of the contact formation portion, _ minimizing the dark signal. In the case of a large number of well-known transfer transistors (sources) of the prior art, the dark signal can be increased by swaying the surface of the crucible. The interlayer dielectric layer 160 and the wiring 150 may be formed on the first substrate 1A. The line 150 may be a first metal contact 151a, a first metal (5) 'second metal (5), a first metal 153, and a fourth metal contact 154, but the embodiment is not limited thereto. The line 150 may be formed for each unit cell to connect the photo-diode 205 and the --out circuit 120' to transfer the photo-charge of the photo-diode 2〇5. When the line 150 to which the readout is connected is formed, the line 170 connecting the peripheral portion B can also be formed into lines 15A and 17B which can be formed of a plurality of conductive materials including metal, alloy or stone. The line 15 formed in the element A is formed for each unit element.

The photo-charge of the light-pole is transferred to the readout circuit iL, and the first line 1SG of the unit A is connected to the unit cell of the sewing operation, and the second line is connected to the dummy pixel. In the process of forming the third metal 153 of the line 150, the crucible (10) may be formed in the peripheral portion 3. P-system, reference "Fig. 3" "The second substrate comprising the crystalline semiconductor layer is employed as a single crystal or polycrystalline substrate and may be $^ impurity or & A substrate of type impurities. The crystalline semiconductor layer 200 is formed by being formed on the second substrate 2 through a process. 15 Referring to Fig. 4, the photodiode layer 201 can be formed in the crystalline semiconductor layer 2A. The photodiode layer 201 can be formed by ion implantation to form the n-type first impurity region 22 and the P· type second impurity region 230 in the crystalline semiconductor layer 200. Therefore, the pN junction can be formed on the crystalline semiconductor layer 200. in. Further, the ohmic contact layer 210 can be formed by implanting a high concentration type impurity into the surface of the first impurity region 220. According to an embodiment, since the first impurity region 220 is formed thicker than the second impurity region 23, the charge storage capacity may be increased, that is, the Ν layer is formed thicker to extend the consuming region, so that light can be accommodated The capacity of the charge can be increased. Although not shown in the drawing, a hydrogen ion layer may be formed between the crystalline semiconductor layer 2 and the second substrate 20. Alternatively, the dielectric layer is buried between the crystalline semiconductor layer 2 and the second substrate 20. After the second substrate 2 is removed, the dielectric layer can be removed by a wet etch process. The secret layer and dielectric are formed to separate the second substrate from the crystalline semiconductor layer 200. Referring to Fig. 5, the first substrate 1A and the second substrate 20 including the crystalline semiconductor layer 2'' are bonded to each other. The surface of the ohmic contact layer 21 can be placed on the interlayer "electric layer 160" and then the bonding is completed, wherein the interlayer dielectric layer is detached to the surface of the first substrate 100. Then, the lower line 15 and the ohmic contact layer are 〇 is electrically connected. The second substrate 2 can be removed to expose the photodiode layer 201. When the first substrate 2 is removed, the thin crystalline semiconductor layer 2 (8) 1375320 remains on the first substrate. 100. For example, using a hydrogen ion layer (not shown) of a germanium dielectric layer (not shown) as a reference, the second substrate 20 can be removed using a blade or chemical mechanical polishing (CMP) process. Please refer to "Fig. 7" ' | The isolation pattern 24 〇 can be formed on the crystalline semiconductor layer 2 。. The device isolation pattern 240 is formed by forming a dielectric layer such as an oxide layer on the photodiode layer 2〇1 and then patterning it so that it selectively exposes the fineness of the crystalline semiconductor layer. Further, the device isolation pattern 24 () may expose a portion of the crystalline semiconductor layer 2 corresponding to the peripheral portion b. The device isolation trench 235 may be formed in the crystalline semiconductor layer 200 as a mask by using a device isolation pattern, and the device isolation trench 235 may be formed through a selectively-crystalline semiconductor layer. By thus ΐ.;!! 201 ^ ▲, the line 150 is separated for the mother-cell pixel. The unit photo element 5, the first photodiode 205 of the remote connection line 150 can be a substantial operation, and the H pole body can be a dummy pixel. When formed, the groove is separated from the groove: 9^ can be used, for example, on a transparent dielectric plate of oxygen cut: on the plate (8). Device isolation layers 250 are formed. Since the device isolation layer 250 is formed on the interlayer dielectric layer 160 while filling the inside of the device isolation trench 235, the first photodiode 205 and the second photodiode 205a can be isolated from each other. In addition, since the device isolation layer 250 is formed over the entire surface of the interlayer dielectric layer 160, it can protect the first photodiode 205 and the second photodiode 205a and the peripheral line B of the line 170. Referring to "Fig. 10", a first through hole 255 and a second through hole 257 may be formed in the device isolation layer 250. The first through hole 255 and the second through hole 257 may be formed through the clearing portion device isolation layer 250, and may expose a partial surface of the first photodiode 205 and the line 17A, respectively. Please refer to "FIG. 11". The upper electrode layer 260 may be formed on the device isolation layer 250 including the first via 255 and the second via 257. The upper electrode layer 260 can be formed by depositing a conductive material on the device isolation layer 250 including the first via 255 and the second via 257. For example, the upper electrode layer 260 may be formed of an opaque metal layer such as titanium, aluminum, copper, and town. The upper electrode layer 260 is electrically connected to the first photodiode 205 isolated for each cell through the first via 255. Further, the upper electrode layer 260 can be electrically connected to the line 170 of the peripheral portion b through the second through hole 257. The upper electrode layer 260 extends from the first through hole 255 to the second through hole 257 to shield the upper surface of the second photodiode 2〇5a. Therefore, the light guided to the second photodiode 205a can be blocked by the upper electrode layer 260. The upper electrode layer 260 is only connected to the first photodiode 205 (instead of the second photodiode 205a), so that the first photodiode 205 performs a substantial operation. In addition, since the upper layer 18 1375320 electrode layer 260 is not electrically connected to the second photodiode 2〇5a, the second photodiode 2〇5& can be used as a dummy element. Usually, during the measurement of the leakage current, the leakage current factor may be caused by the lower line and the _L line. According to the embodiment in which the leakage current of the line 15G is not generated, the linear dummy pixel is not connected to the upper electrode layer, so that the leakage current factor of the reset line can be eliminated, so that accurate measurement of the current can be performed. The second photodiode 2 〇 1 2 3 4a can be used as a dark reference for the sputum.

In addition, since the upper electrode layer 260 functions as a barrier layer for the second photodiode 2〇5a, the difference between the internal and external signals due to temperature is compared, so that the associated output image of the thermal element can be improved. The month-exposure portion 265 may be formed in the upper electrode layer 260 to expose the light-receiving region of the photodiode 2() 5 formed for each unit cell. The first exposed portion 265 can ensure the light receiving region of the first photodiode 205 by removing a portion of the upper electrode layer which is still corresponding to the first photodiode 2 formed for each unit pixel. Further, when the S-exposed portion is formed, the second exposed portion 267 exposing a portion of the device isolation layer 250 corresponding to the pad 18A can be formed. Referring to FIG. 13 in January, the first passivation layer 27 and the second passivation layer 28 can be formed on the interlayer dielectric layer 16, wherein the first exposed portion and the second exposed portion are formed by The interlayer dielectric layer 16 is on top. The first passivation layer 27 〇 passes through the first exposed portion of the contact device _ 25G1. In some embodiments, the first passivation layer may be an oxide layer 1375320 or a nitride layer. In addition, the second passivation layer 280 may be a nitride layer or an oxide layer. Referring to "Fig. 14", a pad 285 that exposes the pad 18 of the peripheral portion B can be formed. The pad holes 285 may expose the pads 18 by removing portions of the interlayer dielectric layer 16, the device isolation layer 250, the first passivation layer 270, and the second passivation layer 280 corresponding to the pads 180.

Referring to "Fig. 15", the pad passivation layer 29 can be formed on the interlayer dielectric layer 16G on which the via holes 285 are formed. During subsequent processing of the filament color filter 3 (8) and the microlens (not shown), the pad passivation layer 290 detects the suppression pad 18 from contamination. For example, the passivation layer 290 can be a layer of tetra ethyl ortho silicate (TEOS) having a thickness of about 10,000 Å. Printed with reference to "Fig. 16", a color filter, a light sheet 3 (8), and a microlens (not shown) may be formed on the partial light-emitting layer 290 corresponding to the first photodiode 205 and the second photodiode. A color filter 3〇〇 may be formed for each unit of the element to separate the color from the incident light.

For the detailed description of the image sensor of another embodiment, please refer to the "nth diagram". The image sensor may include: a readout circuit (10) is formed = - apologize _15 〇 , a form factor - a new dirty, (4) an output circuit 12 〇; and a photodiode (not shown) electrically connected to the green line 150 and formed in the crystalline semiconductor layer on the first substrate 100. This embodiment can use "2nd picture", "3rd picture", "4th picture", "6th picture", "7th picture", "8th picture", "9th picture", "1st" Technical features of the embodiments described in the drawings, "2: 20 1^/5320", "12", "13", "14", "15" and "16" . For example, each of the first photodiodes 2〇5 can be isolated by the device isolation trench 235 and the device isolation layer 250 (iv) unit cell. Further, a passivation layer may be formed on the interlayer dielectric layer 16 on which the photo-diode 205 is formed to protect the photodiode 205 and other skirts. Further, the second photodiode is applied as a dummy element, and the upper electrode layer 260' is not connected. The second photodiode can be formed to measure the leakage current. In the meantime, unlike the above embodiment, the embodiment shown in Fig. 17 shows that the first conductive type connection region 148 is formed on the side of the electrical junction region 14A. The first conductive type connection region 148 (Ν + connection region) for ohmic contact according to the embodiment can be formed on the electrical junction region (10) (p·# junction). In the case of the device, the device is applied to the formation process of the reverse contact 'the first conductive type connection region 148 (the connection region) and the first metal contact 1 被 applied to the t gas junction region i4Q (the biliary junction). Provide a source of leakage, so the electric field (el* leg; EF) can be generated in the county. During the contact formation process, crystal defects generated inside the electric field serve as a source of leakage. Further, in the example in which the first conductive type connection region 148 (10) connection region is formed on the surface of the electrical junction region 丨40 (Ρ〇/Ν·/Ρ·junction), the electric field is 148 (Ν+ junction). The second conductivity type ion implantation layer 145 (Ρ0) is added. This electric field is also used as a source of leakage. 1375320 Accordingly, this embodiment proposes a layout in which the first metal contact 151a is formed in the active region of the undoped p〇 layer but including the first conductive type connection region 148 (N+ connection region). Then, the first metal contact 151a is connected to the first conductive type ion implantation layer 143 (N. junction) through the first conductive type connection region 148 (N + connection region). According to the example, the electric field is not generated on the surface of the stone, which can help reduce the dark current of the three-dimensional integrated metal oxide semiconductor image sensor. In the present specification, an embodiment, an embodiment, an embodiment, and the like, are not related to the specific features, structures, or characteristics described in the embodiment included in at least one embodiment of the present invention. The terms appearing in different places in the specification are not necessarily all referring to the same thing. In addition, when the features, structures, or characteristics are combined with any real-described description, those skilled in the art may affect the combination of other embodiments. These features, structures or characteristics. Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the spirit and scope of the present invention that the modifications and retouchings are within the scope of the present invention. In particular, various changes and modifications may be made in the present invention, the drawings, and the combinations of the subject combinations within the scope of the invention. Other methods of use will be apparent to those skilled in the art, in addition to variations and modifications in the component parts and/or arrangements. — [Simple description of the drawings] Fig. 1 to Fig. 16 show the view of the manufacturing of the image sensor of the embodiment 22 1375320; Fig. 17 shows the partial details of the image sensor of the embodiment BRIEF DESCRIPTION OF THE DRAWINGS Fig. 18 is a view showing the photocharge dump structure of the readout circuit of the embodiment; and Fig. 19 is a view showing the readout photocharge dump structure of the prior art. [Main component symbol description]

20 second substrate 100 first substrate 110 device isolation layer 120 readout circuit 121 transfer transistor Tx 123 reset transistor Rx 125 drive transistor Dx 127 select transistor Sx 130 ion implantation region 131 floating diffusion region FD 133 source / drain region 135 source and polar region 137 source / drain region 140 electrical junction region 141 second conductivity type well 23 1375320

143 First conductivity type ion implantation layer 145 Second conductivity type ion implantation layer 147 First conductivity type connection region 148 First conductivity type connection region 150 Line 150a Line 151 First metal 151a First metal contact 152 Second metal 153 Third metal 154a fourth metal contact 160 interlayer dielectric layer 170 line 180 pad 200 crystalline semiconductor layer 201 photodiode layer 205 first photodiode 205a second photodiode 210 ohmic contact layer 220 first impurity region 230 second Impurity area 24 1375320

235 device isolation trench 240 device isolation pattern 250 device isolation layer 255 first via 257 second via 260 upper electrode layer 265 first exposed portion 270 first purification layer 280 second passivation layer 285 pad hole 290 塾 passivation layer 300 Color filter, light sheet A, peripheral part B

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Claims (1)

Patent application scope: - an image sensor comprising: - a first substrate comprising: providing a readout circuit and providing a peripheral portion of the peripheral circuit; - an interlayer dielectric layer - located at the first On the substrate, the interlayer dielectric layer includes a first line connecting the readout circuit and a second line connecting the peripheral circuit; a crystalline semiconductor layer on a portion of the interlayer dielectric layer corresponding to the pixel portion; a first photodiode and a second photodiode are disposed in the crystalline semiconductor layer 'the first photodiode and the second photodiode are separated by a device isolation trench' H is connected to the line of the first line; 1 - the device isolation layer is located on the crystalline semiconductor layer containing the device_trench; and the upper layer is passed through the device on the crystalline casting layer The isolation layer is connected to the portion of the first photodiode; the exposed portion is located in the upper electrode layer, the wire exposed portion selectively exposes an upper region of the first photodiode; and a passivation layer; The exposed portion On the first substrate. The image sensor of claim 1, wherein a portion of the device isolation layer on the crystalline semiconductor layer comprises a first pass hole of a violent-first photodiode, and wherein the average electrode material is The image sensor of claim i, wherein the first photodiode comprises a main pixel connected to the upper electrode layer to complete - the essence is #, the first The dichroic diode includes a dummy pixel that is not connected to the upper electrode layer. 4. The image sensor of claim i, wherein the readout circuit comprises an electrical junction region in the first substrate, wherein the f gas junction _ comprises: " a first conductivity type ion implant Into the area on the first substrate +. and . A second conductivity type ion implantation region is on the first conductivity type ion implantation region. 5. The image sensor according to claim 4, further comprising the first line on the junction area of the electrical connection type. 6. In the case of claim 4, Hiroshi Satoshi, the money is connected to the junction. 7. The image sensor of item i, wherein the readout circuit comprises a potential difference generated between a source and a drain of a transistor. 8. The image sensor according to claim 7, wherein the electro-crystal system is a transfer transistor = '= and _ the hetero-ion is lower than the pole of the transistor - the floating diffusion region One ion implantation; agricultural degree. 9. The image sensor described above further includes a first-conducting type connection region 'electrically connecting the electrical junction region-side of the first line. The tree device according to the item 9 of the present invention, wherein the first conductive type connection region is between the device-isolated region and the device isolation region and 27 of the electrical junction region, and the first substrate is thinned The device is separated from the hybrid domain and the electrical domain. u.—Method of manufacturing an image sensor ” The method comprises: forming a read-out circuit on a substrate of the first substrate and a peripheral circuit on a peripheral portion of the substrate; Forming an interlayer dielectric layer on the first substrate, the interlayer dielectric layer including a first line connecting the readout circuit and a second line connecting the peripheral lines; forming a second semiconductor layer including a crystalline semiconductor layer Forming a photodiode layer in the crystalline semiconductor layer; bonding the first substrate to the second substrate including the crystalline semiconductor layer; removing a portion of the second substrate to expose the photodiode Separating the photodiode from the first substrate forming device isolation trench a region of the layer to form a first photodiode and a second photodiode; and a device isolation layer on the crystalline semiconductor layer including the device isolation trench; An electrode layer is disposed on the isolation layer, such that the upper electrode layer is connected to a portion of the first photodiode; and a portion of the upper electrode layer is removed to form an exposed portion, and the first photodiode is selectively exposed An upper region; and 28 1375320 forming a passivation layer on the interlayer dielectric layer, the exposed portion being formed on the interlayer dielectric layer. 12. The method of manufacturing an image sensor according to claim η, wherein during the forming of the device isolation trench, a portion of the crystalline semiconductor corresponding to the peripheral portion is removed] such that a line in the peripheral portion is exposed . 13. The method of fabricating the image device of claim 11, wherein forming the upper electrode layer comprises: forming a first via hole in a portion of the device isolation layer on the crystalline semiconductor layer to expose the a partial surface of the first photodiode; and forming a metal layer on the device isolation layer including the first via. 14. The method of manufacturing image reduction according to claim 13, further comprising forming a second through hole formed in the first through hole, a shaft exposed-line, and a second through hole in the periphery: The second through hole electrically connects the line of the peripheral portion. 15. The method according to claim η, wherein the step of forming the readout circuit on the first substrate comprises forming a coin junction region in the first substrate to form the electrical junction region The step of the first substrate includes: forming a -first conductive ion implantation region in the first substrate; and forming a second conductive type ion implant region on the first conductive type ion implantation region. !6 ‘The manufacturing method of the image _· as described in claim 5, further includes forming a connection 29 ! 1375320 The line-the-lead-connection area of the line is on the electrical junction area. 17. The method of fabricating an image sensor according to claim 16, wherein the forming the first conductive type access area is completed after completing the one of the first lines. The manufacturing method of the image sensor described in -15 further includes a flat-shaped two-line-the-first-conducting type connection. the area is in the electrical junction area= 19. The manufacturing apparatus of Fig. 18, as described in claim 18, == formed in the electrical connection area of the first substrate. The split isolation region contacting the first substrate and the 30