KR101163817B1 - Image Sensor and Method for Manufacturing Thereof - Google Patents

Abstract

The image sensor according to the embodiment includes a readout circuitry formed on the first substrate; An interlayer insulating layer having a wire including metal and metal contacts formed on the lead-out circuit; And an image sensing device formed on the interlayer insulating layer including the wirings, wherein the metal contact includes a first metal film pattern, a dielectric film pattern, and a second metal film pattern.

A method of manufacturing an image sensor according to an embodiment may include forming a readout circuitry on a first substrate; Forming an interlayer insulating film including a metal on the readout circuit; Forming a via hole in the interlayer insulating layer; Forming a metal contact including a first metal layer pattern, a dielectric layer pattern, and a second metal layer pattern in the via hole; And forming an image sensing device on the interlayer insulating layer including the metal contact, wherein the first metal layer pattern is formed between the interlayer insulating layer and the dielectric layer pattern. The dielectric film pattern may include one formed between the first metal film pattern and the second metal film pattern.

Image sensor

Description

Image sensor and method for manufacturing thereof

Embodiments relate to an image sensor and a method of manufacturing the same.

An image sensor is a semiconductor device that converts an optical image into an electrical signal, and is classified into a charge coupled device (CCD) image sensor and a CMOS image sensor (CIS). .

In the prior art, a photodiode is formed on a substrate by ion implantation. However, as the size of the photodiode gradually decreases for the purpose of increasing the number of pixels without increasing the chip size, the image quality decreases due to the reduction of the area of the light receiver.

In addition, since the stack height is not reduced as much as the area of the light receiving unit is reduced, the number of photons incident on the light receiving unit is also decreased due to diffraction of light called an airy disk.

One alternative to overcome this is to deposit photodiodes with amorphous Si, or read-out circuitry using wafer-to-wafer bonding such as silicon substrates. Attempts have been made to form photodiodes on top of the lead-out circuit (hereinafter referred to as "three-dimensional image sensor"). The photodiode and lead-out circuit are connected via a metal line.

On the other hand, according to the prior art, the photodiode is disposed above the readout circuit, so that a signal loss due to a contact occurs during signal transmission.

In addition, since both the source and the drain of the transfer transistor are doped in a high concentration N-type (Charge Sharing) is a problem that occurs. When charge sharing occurs, the sensitivity of the output image is lowered and image errors may occur.

In addition, according to the related art, a dark current is generated between the photodiode and the lead-out circuit and the photocharge is not smoothly moved, and saturation and sensitivity are decreased.

Embodiments provide a method of manufacturing an image sensor capable of minimizing loss of a signal between a photodiode and a circuit when forming a vertical photodiode.

In addition, the embodiment is to provide a method of manufacturing an image sensor in which charge sharing may not occur while increasing the fill factor.

In addition, the embodiment of the present invention manufactures an image sensor capable of minimizing dark current sources and preventing saturation and degradation of sensitivity by creating a smooth movement path of photo charge between the photodiode and the lead-out circuit. To provide a method.

The image sensor according to the embodiment includes a readout circuitry formed on the first substrate; An interlayer insulating layer having a wire including metal and metal contacts formed on the lead-out circuit; And an image sensing device formed on the interlayer insulating layer including the wirings, wherein the metal contact includes a first metal film pattern, a dielectric film pattern, and a second metal film pattern.

A method of manufacturing an image sensor according to an embodiment may include forming a readout circuitry on a first substrate; Forming an interlayer insulating film including a metal on the readout circuit; Forming a via hole in the interlayer insulating layer; Forming a metal contact including a first metal layer pattern, a dielectric layer pattern, and a second metal layer pattern in the via hole; And forming an image sensing device on the interlayer insulating layer including the metal contact, wherein the first metal layer pattern is formed between the interlayer insulating layer and the dielectric layer pattern. The dielectric film pattern may include one formed between the first metal film pattern and the second metal film pattern.

An image sensor and a method of manufacturing the same according to the embodiment may be formed of a first metal pattern, a dielectric layer pattern, and a second metal pattern when forming a contact, thereby minimizing a loss of a signal.

In addition, according to the embodiment, the device may be designed such that there is a potential difference between the source and the drain across the transfer transistor Tx, thereby enabling full dumping of the photo charge.

In addition, according to the embodiment, the charge connection region is formed between the photodiode and the lead-out circuit to create a smooth movement path of the photo charge, thereby minimizing the dark current source, and reducing saturation and sensitivity. You can prevent it.

Hereinafter, an image sensor and a method of manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where it is described as being formed "on / under" of each layer, the top / bottom is formed directly and through another layer. It includes everything.

The present invention is not limited to the CMOS image sensor, and can be applied to an image sensor requiring a photodiode.

(First embodiment)

A method of manufacturing the image sensor according to the first embodiment will be described with reference to FIGS. 1 to 7. FIG. 1A is a schematic diagram of the first substrate 100 on which the wiring 150 is formed, and FIG. 1B will be described with reference to FIG. 1B as a detailed view thereof.

First, as shown in FIG. 1B, the first substrate 100 having the wiring 150 and the readout circuit 120 is prepared. For example, the isolation layer 110 is formed on the second conductive first substrate 100 to define an active region, and a readout circuit 120 including a transistor is formed in the active region. For example, the readout circuit 120 may include a transfer transistor (Tx) 121, a reset transistor (Rx) 123, a drive transistor (Dx) 125, and a select transistor (Sx) 127. can do. Thereafter, an ion implantation region 130 including a floating diffusion region (FD) 131 and source / drain regions 133, 135, and 137 for each transistor may be formed. In addition, according to the embodiment, the noise can be improved by adding a noise removing circuit (not shown).

The forming of the lead-out circuit 120 on the first substrate 100 may include forming an electrical junction region 140 on the first substrate 100 and forming an interconnection on the electrical junction region 140. And forming a first conductivity type connection region 147 connected to 150.

For example, the electrical junction region 140 may be a PN junction 140, but is not limited thereto. For example, the electrical junction region 140 may include a first conductive ion implantation layer 143 and a first conductive ion implantation layer (143) formed on the second conductive well 141 or the second conductive epitaxial layer. 143 may include a second conductivity type ion implantation layer 145. For example, the PN junction 140 may be a P0 145 / N- 143 / P-141 junction as shown in FIG. 2, but is not limited thereto. The first substrate 100 may be conductive in a second conductivity type, but is not limited thereto.

According to the embodiment, the device can be designed such that there is a voltage difference between the source / drain across the transfer transistor Tx, thereby enabling full dumping of the photo charge. Accordingly, as the photo charge generated in the photodiode is dumped into the floating diffusion region, the output image sensitivity may be increased.

That is, the embodiment forms the electrical junction region 140 on the first substrate 100 on which the readout circuit 120 is formed as shown in FIG. 1B such that there is a voltage difference between the sources / drains across the transfer transistor (Tx) 121. This allows full dumping of the photocharge.

Hereinafter, the dumping structure of the photocharge of the embodiment will be described in detail.

Unlike the floating diffusion (FD) 131 node, which is an N + function in the embodiment, the P / N / P section 140, which is an electrical junction region 140, does not transmit all of the applied voltage and pinches at a constant voltage. It is off (Pinch-off). This voltage is called a pinning voltage and the pinning voltage depends on the P0 145 and N- (143) doping concentrations.

Specifically, the electrons generated by the photodiode 210 are moved to the PNP caption 140 and are transferred to the FD 131 node when the transfer transistor (Tx) 121 is turned on to be converted into a voltage.

Since the maximum voltage value of the P0 / N- / P- caption 140 becomes pinning voltage and the maximum voltage value of the FD (131) node becomes Vdd-Rx Vth, the charge sharing is performed due to the potential difference between both ends of the Tx (131). Electrons generated from the photodiode 210 above the chip may be fully dumped to the FD 131 node.

That is, in the embodiment, the reason why the P0 / N- / P-well junction, not the N + / P-well junction, is formed in the silicon sub, which is the first substrate 100, is P0 during the 4-Tr APS Reset operation. In / N- / P-well junction, + voltage is applied to N- (143) and ground voltage is applied to P0 (145) and P-well (141), so P0 / N- / P-well Double above a certain voltage Junction is Pinch-Off as in BJT structure. This is called pinning voltage. Therefore, a voltage difference is generated in the source / drain at both ends of the Tx 121, and thus the photocharge is completely dumped from the N-well to the FD through the Tx at the Tx On / Off operation to prevent the charge sharing phenomenon.

Therefore, unlike the case where the photodiode is simply connected by N + junction as in the prior art, the embodiment can avoid problems such as degradation of saturation and degradation of sensitivity.

Next, according to the embodiment, the first conductive connection region 147 is formed between the photodiode and the lead-out circuit to make a smooth movement path of the photo charge, thereby minimizing the dark current source and saturation. It is possible to prevent degradation of saturation and degradation of sensitivity.

To this end, the embodiment may form an n + doped region as the first conductive connection region 147 for ohmic contact on the surface of the P0 / N− / P− junction 140. The N + region 147 may be formed to contact the N− 143 through the P0 145.

Meanwhile, in order to minimize the first conductive connection region 147 from becoming a leakage source, the width of the first conductive connection region 147 may be minimized. To this end, the embodiment may proceed with a plug implant after etching the first metal contact 151a, but is not limited thereto. For example, as another example, an ion implantation pattern (not shown) may be formed and the first conductive connection region 147 may be formed using the ion implantation mask as an ion implantation mask.

That is, as in the first embodiment, the reason for locally N + doping only to the contact forming part is to facilitate the formation of ohmic contact while minimizing the dark signal. As in the prior art, when N + Doping the entire Tx Source part, the dark signal may increase due to the substrate surface dangling bond.

Next, the interlayer insulating layer 160 may be formed on the first substrate 100, and the wiring 150 may be formed. The wiring 150 may include a first metal contact 151a, a first metal 151, a second metal contact 152a, a second metal 152, a third metal contact 153a, and a third metal 153. And a fourth metal contact 154a, but is not limited thereto.

In this case, the fourth metal contact 154a may be formed by the method illustrated in FIGS. 1C to 1F.

As shown in FIG. 1C, after the interlayer insulating layer 160 is formed on the first substrate 100 on which the third metal 153 is formed, the interlayer insulating layer is exposed so that the third metal 153 is exposed. The via hole 5 is formed at 160.

As shown in FIG. 1D, the first metal layer 10 and the dielectric layer 20 are formed on the interlayer insulating layer 160 on which the via holes 5 are formed.

The first metal layer 10 may be formed of a material such as Al, and the dielectric layer 20 may be formed of a material such as USG (Undoped Silicate Glass) or SiN.

Subsequently, as shown in FIG. 1E, anisotropic etching is performed on the first metal layer 10 and the dielectric layer 20, and the first metal pattern 15 and the dielectric layer pattern ( 25).

The first metal layer 10 and the dielectric layer 20 exposed on the bottom surface of the via hole 5 and the upper portion of the interlayer insulating layer 160 are removed by the anisotropic etching process, and the sidewalls of the via hole 5 are removed. Only the first metal pattern 15 and the dielectric layer pattern 25 remain on the substrate.

In this case, the third metal 153 is exposed on the bottom surface of the via hole 5.

1F, the second metal pattern 35 is buried in the via hole 5.

The second metal pattern 35 may be formed by forming a second metal layer on the interlayer insulating layer 160 on which the first metal pattern 15 and the dielectric layer pattern 25 are formed, and then performing a planarization process. have.

The second metal pattern 35 may be formed of a material such as Al and Cu.

Accordingly, the fourth metal contact 154a including the first metal pattern 15, the dielectric layer pattern 25, and the second metal pattern 35 is formed on the third metal 153.

The fourth metal contact 154a includes the first metal pattern 15, the dielectric layer pattern 25, and the second metal pattern 35, thereby minimizing the loss of a signal.

In the present embodiment, only the formation process of the fourth metal contact 154a is described, but the present invention is not limited thereto, and the first metal contact 151a, the second metal contact 152a, and the third metal contact 153a are also described above. It may be formed in the same manner as the fourth metal contact 154a.

Next, as shown in FIG. 2, a crystalline semiconductor layer 210a is formed on the second substrate 200. In the first embodiment, the photodiode 210 is formed on a crystalline semiconductor layer. Thus, according to the embodiment, it is possible to prevent defects in the image sensing unit by forming the image sensing unit in the crystalline semiconductor layer while increasing the fill factor by employing a three-dimensional image sensor positioned above the readout circuit. .

For example, the crystalline semiconductor layer 210a is formed on the second substrate 200 by epitaxial. Thereafter, hydrogen ions are implanted into the boundary region of the second substrate 200 and the crystalline semiconductor layer 210a to form the hydrogen ion implantation layer 207a. The implantation of the hydrogen ions may be performed after ion implantation for forming the photodiode 210.

Next, as shown in FIG. 3, the photodiode 210 is formed by ion implantation into the crystalline semiconductor layer 210a. For example, a second conductivity type conductive layer 216 is formed under the crystalline semiconductor layer 210a. For example, a high concentration P-type conductive layer 216 may be formed by implanting ions into the entire surface of the second substrate 200 with a blanket under the crystalline semiconductor layer 210a without a mask. For example, the second conductivity type conductive layer 216 may be formed with a junction depth within about 0.5 μm.

Thereafter, a first conductivity type conductive layer 214 is formed on the second conductivity type conductive layer 216. For example, a low concentration N-type conductive layer 214 may be formed by implanting ions onto the entire surface of the second substrate 200 without a mask on the second conductive conductive layer 216. For example, the low concentration first conductivity type conductive layer 214 may be formed with a junction depth of about 1.0-2.0 μm.

According to the embodiment, the thickness of the first conductivity type conductive layer 214 is formed to be thicker than the thickness of the second conductivity type conductive layer 216, thereby increasing the charge storage capacity. That is, by forming the N-layer 214 thicker to expand the area, it is possible to improve the capacity (capacity) that may contain the optoelectronic.

Thereafter, the first embodiment may further include forming a high concentration of the first conductivity type conductive layer 212 on the first conductivity type conductive layer 214. For example, the high concentration first conductive type layer 212 may be formed with a junction depth of about 0.05 to 0.2 μm. For example, an ion implantation may be performed on the entire surface of the second substrate 200 without a mask on the first conductive type conductive layer 214 to form a high concentration N + type conductive layer 212, thereby contributing to ohmic contact.

Next, as illustrated in FIG. 4, the first substrate 100 and the second substrate 200 are bonded.

Thereafter, as illustrated in FIG. 5, the hydrogen ion implantation layer 207a may be changed into the hydrogen gas layer 207 through heat treatment on the second substrate 200.

6, the photodiode 210 may be exposed by leaving a photodiode 210 based on the hydrogen gas layer and removing a portion of the second substrate 200 using a blade or the like.

Thereafter, as illustrated in FIG. 7, an etching process of separating the photodiode 210 for each pixel may be performed to form an inter-pixel separation layer (not shown). Thereafter, processes such as a ground process (not shown) and a color filter (not shown) may be performed.

(2nd Example)

8 is a cross-sectional view of the image sensor according to the second embodiment, which is a detailed view of the first substrate on which the wiring 150 is formed.

The second embodiment can employ the technical features of the first embodiment.

Meanwhile, unlike the first embodiment, the second embodiment is an example in which the first conductive connection region 148 is formed on one side of the electrical bonding region 140.

According to an embodiment, an N + connection region 148 for ohmic contacts may be formed in the P0 / N− / P− junction 140, in which case the N + connection region 148 and the M1C contact 151a are formed in the process. A source may occur. This is because the electric field EF may be generated on the Si surface of the substrate because the reverse bias is applied to the P0 / N− / P− junction 140. The crystal defects generated during the contact forming process in the electric field become a liquid source.

In addition, when the N + connection region 148 is formed on the surface of the P0 / N- / P- junction 140, an E-field by the N + / P0 junction 148/145 is added, which may also be a leakage source. .

Accordingly, in the second embodiment, the first contact plug 151a is formed in an active region formed of the N + connection region 148 without being doped with a P0 layer, and a layout for connecting the first contact plug 151a with the N-junction 143 is provided. present.

According to the second embodiment, the E-Field of the Si surface does not occur, which may contribute to the reduction of dark current of the 3-D integrated CIS.

The present invention is not limited to the described embodiments and drawings, and various other embodiments are possible within the scope of the claims.

1 to 8 are cross-sectional views illustrating a manufacturing process of an image sensor according to an embodiment.

Claims (13)

A readout circuitry formed on the first substrate; An interlayer insulating layer having a wire including metal and metal contacts formed on the lead-out circuit; And And an image sensing unit formed on the interlayer insulating layer including the wires. The metal contact may include a first metal layer pattern formed only on a sidewall of a via hole formed in the interlayer insulating layer, a dielectric layer pattern formed on the first metal layer pattern, and a first metal layer pattern embedded in the via hole in which the first metal layer pattern and the dielectric layer pattern are formed. 2 metal film pattern, The first substrate includes an electrical junction region including a PN junction, and the electrical junction region is electrically connected to the wiring. The method of claim 1, The first metal film pattern is an image sensor comprising one formed of Al. The method of claim 1, The dielectric film pattern includes an image sensor formed of USG (Undoped Silicate Glass) or SiN. The method of claim 1, The first metal film pattern is formed between the interlayer insulating layer and the dielectric film pattern, The dielectric film pattern may include one formed between the first metal film pattern and the second metal film pattern. The method of claim 1, The second metal film pattern is formed of Al or Cu. Forming an electrical junction region including a PN junction on the first substrate; Forming a readout circuitry on the first substrate; Forming an interlayer insulating layer including a metal on the readout circuit; Forming a via hole in the interlayer insulating layer; Forming a first metal layer pattern formed only on sidewalls of the via hole and a dielectric layer pattern formed on the first metal layer pattern; Forming a metal contact including the first metal layer pattern, the dielectric layer pattern, and the second metal layer pattern by forming a second metal layer pattern embedded in the via hole in which the dielectric layer pattern is formed; And And forming an image sensing device on the interlayer insulating layer including the metal contact. The method of claim 6, And forming the via hole in the interlayer insulating layer, wherein the metal is exposed through the via hole. delete The method of claim 6, Forming the first metal film pattern and the dielectric film pattern on the sidewalls of the via hole, Forming a first metal film on the interlayer insulating layer including the via hole; Forming a dielectric film on the first metal film; And Performing an anisotropic etching process on the first metal layer and the dielectric layer to leave the first metal layer pattern and the dielectric layer pattern only on sidewalls of the via hole. 10. The method of claim 9, The first metal layer and the dielectric layer formed on the interlayer insulating layer and the bottom surface of the via hole by the anisotropic etching process to remove the first metal layer and the dielectric layer pattern in the via hole. Manufacturing method. The method of claim 6, The forming of the second metal film pattern in the via hole may include: Forming a second metal layer on the interlayer insulating layer including the first metal layer pattern and the dielectric layer pattern formed on sidewalls of the via hole; And And removing the second metal film formed on the interlayer insulating layer to form the second metal film pattern inside the via hole. The method of claim 6, The first metal film pattern is a method of manufacturing an image sensor comprising an Al. The method of claim 6, The dielectric layer pattern may be formed of USG (Undoped Silicate Glass) or SiN.

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