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TWI375283B - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
TWI375283B
TWI375283B TW098115402A TW98115402A TWI375283B TW I375283 B TWI375283 B TW I375283B TW 098115402 A TW098115402 A TW 098115402A TW 98115402 A TW98115402 A TW 98115402A TW I375283 B TWI375283 B TW I375283B
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fin
layer
forming
condensed
condensation
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TW098115402A
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TW201023275A (en
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Chenghung Chang
Yurung Hsu
Chenyi Lee
Shihting Hung
Chennan Yeh
Chenhua Yu
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Taiwan Semiconductor Mfg
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6211—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H10P14/20—
    • H10P14/2905—
    • H10P14/3211—
    • H10P14/3411—

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

1375283 六、發明說明： 【相關申請案之交互參照】 本申請案係與公元2008年5月6日所提出且名稱為 「設有介電衝穿阻止層之鍺鰭式場效電晶體（FinFETs Having Dielectric Punch-Through Stoppers)」之美國專利申 請案12/116,074有關，在此將其整體内容一併列入作為參 考。 【發明所屬之技術領域】 本發明一般是有關於一種半導體裝置，且特別是有關 於一種錯奈米線(Nano-Wires)以及設有錯鰭片之場效電晶 體（Fin Field-Effect Transistors ; FinFETs)之結構與形成方 法。 【先前技術】 鍺是一種習知之半導體材料。鍺之電子遷移率 (Electron Mobility)與電洞遷移率（Hole Mobility)大於石夕，因 此使得鍺成為形成積體電路之良好的材料。然而，在過去， 由於矽之氧化物（氧化矽）可輕易地使用於金屬氧化半導體 (MOS)電晶體的閘極介電層中，因此矽獲得較多的歡迎。 MOS電晶體的閘極介電層可利用矽基材之熱氧化而方便 形成。另一方面，鍺之氧化物可溶於水中，因此並不適合 用於閘極介電層的製作。 隨著MOS電晶體的閘極介電層中高介電係數(High_K) 4 1375283 之介電材料的使用，氧化矽所提供之便利性將不再是一個 大優勢，因此重新檢視鍺於積體電路上的應用。聚焦在錯 奈米線之鍺的最新研究已經被提出，其中鍺奈米線係使用 於鰭式場效電晶體中。 半導體工業所面對的一個挑戰是降低MOS電晶體的 漏電流（Leakage) ’且增加鍺鰭式場效電晶體的驅動電流 (Drive Currents) ’亦即需形成絕緣層上覆鍺 (Germanium-On-Insulator ; GOI)結構。然而，GOI 基材[以 及絕緣層上覆應變鍺（Strained GOI; SGOI)基材]之價格高 於矽基材價格好幾倍，且購買GOI基材或SGOI基材對於 晶圓代工廠而言並不實用。 在主體矽(Bulk Silicon)上形成鍺層的方法亦已被探討 過。例如，使用二維（Two-Dimensional ; 2D)或三維 (Three-Dimensional; 3D)縮合法(Condensati〇ns)在主體矽上 形成鍺層或奈米線之方法已被提出過。有二種形成鍺層的 方法。種係在主體梦基材上形成梦鍺層。此方法帶來較 少的成本。然而，由於二維或三維縮合法需要較高的溫度 (例如：1000°c或以上）來將矽移動至矽鍺層的表面，鍺原 子將牙透至主體石夕基材中。其導致之結果為：在主體石夕基 材中鍺濃度為漸次變化，且無法形成純鍺層。 另一方面，假如二維及/或三維縮合法係由包括矽鍺 (SiGe)層於埋藏氧化層（Burie(j 〇xide Layer; Β〇χ)之基材 (其中埋藏氧化層更位於矽基材上）開始執行，則鍺的向下 移動可能會受阻於埋藏氧化層，且將會形成實質純鍺奈米 線。然而，具有SiGe/BOX/矽基材結構之基材非常昂貴， 5 1375283 故此方法在積體電路之量產上依然不實用。 . 然而，在此技術領域所需的是，在不帶來高成本的同 時，結合鍺以利用其高電子遷移率及電洞遷移率之特點之 ψ 優勢的結構與形成方法。 【發明内容】 本發明之目的就是在提供一種形成半導體結構的方 法，在兼顧成本的先決條件下，將鍺之高電子遷移率及電 籲 洞遷移率的特點應用鰭式場效電晶體中。 根據本發明之一觀點，提供一種形成半導體結構的方 法。此方法包括提供複合基材，其中複合基材包括有主體 石夕基材與緊鄰於主體石夕基材之上的石夕錄層。對石夕錄層執行 第一縮合以形成縮合矽鍺層，藉以使得縮合矽鍺層具有實 質均勻的鍺濃度。蝕刻縮合矽鍺層與主體矽基材的頂端部 份以形成複合鰭片，其中複合鰭片包括矽鰭片與位在矽鰭 片上的縮合矽鍺鰭片。此方法更包括氧化矽鰭片的一部 • 份，以及對縮合矽鍺鰭片執行第二縮合。 根據本發明之另一觀點，提供一種形成半導體結構的 方法。此方法包括提供主體矽基材；磊晶成長矽鍺層於主 體矽基上；以及在實質介於825°C至880°C之間的溫度下對 矽鍺層執行第一縮合以形成縮合矽鍺層。 根據本發明之又一觀點，提供一種形成半導體結構的 方法。此方法包括提供主體發基材以及蠢晶成長梦錯層於 J 主體矽基上。對矽鍺層執行第一縮合以形成縮合矽鍺層， 其中第一縮合係執行於一高溫(Elevated Temperature)中。# 1375283 刻縮合補層與主财基材之頂端部份卿成凹陷部以及 •位在凹陷部的複合鰭片，其中複合籍片包括㈣ •在石夕鰭片上之縮合石夕錯鰭片。此方法更包括填充第—介電 材料於凹陷部中钱刻第-介電材料直到暴露出縮合石夕錯 韓片’ ·形成遮罩以覆蓋縮合石夕鍺鰭片的頂表面與側壁；凹 陷第-介電材料以暴露出石夕縛片之一部份的侧壁；氧化上 述石夕鰭片的-部份以形成絕緣體；以及填充第二介電材料 於第-介電材料上。第二介電材料的頂表面係實質與絕緣 • 體的頂表面等高。對縮合石夕錯鰭片執行第二縮合以形成實 質純化之鍺鰭片。 根據本發明之又-觀點，提供一種半導體結構。此結 構包括半導體基材、位在半導體基材上的錯縛片以及絕緣 體。絕緣體包括直接緊鄰於鍺鰭片之下的第一部份以及緊 鄰於第-部份的第二部份，其中第一部份具有第一底部表 面。第二部份並未直接位在錯鰭片之下 第-底部表面不等高之第二底部表面。 · _本發明之再-觀點，提供_種半導體結構。此結 構包括具有頂表面的石夕基材、緊鄰在石夕基材上的補片以 及緊鄰在石夕基材之頂表面與石夕鰭片上的絕緣體。絕緣體包 括緊鄰於石夕縛片相對二側的第一部份，以及緊鄰於矽鰭片 之上的第二部份。此半導體結構更包括緊鄰於矽鰭片之上 的鍺鰭片》 Λ· 本發明具有優勢之特徵包括降低鰭式場效電晶體中之 ’衝穿電流(Punch-Thr〇ugh Currents)，改善鰭式場效電晶體 通道中之載子遷移率，以及降低製造成本。 1375283 【實施方式】 本說明所採用之較佳實施例的產生與應用詳細討# I :然而，應該理解的是，本發明提供了許多可在二^如 定背景中實施之可應用的發明概念。以卞所討論之特—特 施例係僅用以教示產生和應用本發明的特定方式，而=實 用以限定本發明之範圍。边# 在此提供一種積體電路的形成步驟，其中包括可 於形成鰭式場效電晶體[FinFET，亦稱之為多重用 (Multi-Gate)電晶體]之鍺鰭片的形成。製造本發明之〜二核 實施例的中間階段介紹如下。而此較隹實施例之各種^隹 亦討論如下。在本發明之各個圖式和說明實施例中，化 參考被碼用以命名相同元件。 目同 本發明之實施例係有關於半導體結構以及形 於基材上的製造方法。將矽鍺層縮合以提供一具有^層
鍺濃度的縮合矽鍺層。提供縮合矽鍺層以形成―;二之 電晶體的鍺鰭片。 ^琢效 請參照第1圖，提供半導體基材2G。軸亦 他之半導體材料’但在較佳實施例中，半導體基材係^ 主體矽基材（故以下可稱之為矽基材2〇)。 ” 中，半導體基材20具有超過一層之複合結構，；:=丨 含有-石夕I。石夕錯（SiGe)層22係以例如為 = 於矽基材20上。矽鍺層22可用Sii xGh來表八^ _ ^^^^^^^tb(At〇micPercentage)^r^ " X係實質介於0.15與〇.45之間。更佳的a 貫施例中’ 門1佳的疋，X係約為0.25 8 或25% 此外’薄遮蔽層24係選擇性地形成於矽鍺 f:薄遮蔽層24可為氧化發。遮蔽層24可心實= 1奈米至10奈米之間的厚度。然而，要留意的？實，於 全文中提及之尺寸僅為範例，且 書 :成時，上述之尺寸亦可隨之而改變。遮 == 之縮合步驟中具有避免鍺氧化的優點。 胃在後、·貝 接著’如第2圖所示，執行二維(2D) 以 蝻合之矽鍺層26以及位在縮合 去以產生 28。為了簡化起見，遮蔽層2 合」上的氧化石夕層 層Μ可利用類似於氧化石夕層^二會二於其中，因為遮蔽 至氧切層28巾。二_合 執’並融合 之含氧環境巾，並配合實減订於包含如氧氣(〇2) 較佳之溫度是實質介二 係約85(TC。在二維縮合的_ C之間’而更佳之溫度 向上移動，並與氧氣反應 ，⑦鍺層22中的石夕原子 合之時間的進行，氧化♦層成氧化石夕層28。隨著二維縮 隨著由於氧化作用而減少^^厚度隨之增加。同時，伴 鍺層26中的鍺原子被縮人，夕鍺層U之石夕原子的數目，矽 隨著時間的推移而增加。口，且矽鍺層26中鍺原子百分比 由本發明之發明者所 _ 示於第3圖中之意料外的結：之實驗顯示了如概略性地繪 中的熱效應，矽鍺層22中° 。一般認為，由於二維縮合 20。因此預期會形成一鍺之鍺原子將向下擴散至矽基材 且矽基材20 t靠近於欲杜哳次變化輪廓於矽基材20中， 、鍺層22之區域的鍺濃度大於矽基 9 1375283 材20中遠離矽鍺層22之區域的鍺濃户。 又。然而，實驗駐一 在一特定之溫度區間内，亦即實質介於825。〇至赞。顯不 間，無法觀察到此一效應。第3圖顚+处 880 C之 26 ^ ^ * ,,J ^ ^ ^ 2； 之間的介面係標示為零微米之深度）。在第2圖中可找^ /木度以及負/朱度的思義。在上述特定之溫度區間中，可p 觀察到鍺原子具有非常小或實質為零之向下移動量。= 果’鍺原子縮合至一實質均勻的原子百分比，例如約Μ。〆 在具有50。/。錯之石夕鍺的縮合層底下，發生有急劇的變°化 (Sharp Transition)，且鍺之原子百分比（在一微小的變化區 間）快速地下降至約25%，此為矽鍺層22中原來的鍺百二 比（參照第1圖）。上述顯示非常少量之向下鍺擴散產生分 否則，將可觀察到漸次變化之鍺輪廓。再者，甚至卷縮八 時間很長時(例如9小時或更長的時間），此一不具備錯= 下移動量的縮合亦會發生。此外，在矽基材2〇與矽鍺^ 22的介面，受到觀察到之鍺亦不具備有實質向下移動量:
在二維縮合開始時’當其他部份仍未縮合，發錯層U 之一部份被縮合以形成縮合之矽鍺層26,如第3圖;線 30〜1所示。當二維縮合時間增加時，縮合之矽鍺層與 ，化矽層28的厚度增加，此時未縮合之矽鍺層22之剩^ 部份之厚度減少，如第3圖中線30一2所示。請留意，由於 =3圖中之水平基準(Level With;深度=〇微米）係位在矽鍺 曰22與縮合之矽鍺層26的介面，隨著時間的推移， 基準（深度=〇微米）向下移動，且矽鍺層22與縮合之7平 26之結合厚度減少。假如二維縮合時間夠長(例如· 層 •超過約 1375283
26’如第3圖中線30_3所示 θ 整個夫〇〇 較佳的是，在二維縮合後， 】轉換成縮合之碎鍺層26，而沒 後，剩餘之結齡括有縮合中1二維縮合 鍺層26底下的未縮合^H層26以及位在縮合之發 ^第4圖，薄化氧切層 5 2圖):另外，可完全地移除氧切· 層32可做為㈣終止層祕刻後續形成之 ”、a 34。在第5圖中，遮罩層34係形成於焊墊層32之 上、在較佳實施例中，遮罩層34係由利用低壓化學氣相沈 積法（L〇W-Pressure Chemical Vap〇r Dep〇siti〇I1 ; LPCVD)形 成之氮化矽所組成。在其他實施例中，遮罩層34係以經熱 氮化反應（Thermal Nitridation)之矽、或使用氮氫之電漿辅 助化學氣相沈積法（Plasma Enhanced Chemical Vapor Deposition ; PECVD)或電漿陽極氮化反應（Plasma Anodic
Nitridation)所形成α遮罩層34可具有實質介於60奈米至 120奈米之間的厚度。 請參照第6圖，光阻劑36形成於遮罩層34上，接著 將其圖案化，以形成光阻劑36中之開口 38。然後透過開 口 38蝕刻遮罩層34與焊墊層32，以暴露出其底下縮合之 矽鍺層26。接著，蝕刻縮合之矽鍺層26與矽基材20，使 得開口 38延伸至縮合之矽鍺層26與矽基材20之中。然後 移除光阻劑36。在一例示性實施例中，凹陷深度D1係實 質介於100奈米至300奈米之間。由於凹陷之故，形成一 11 1375283 鰭片100，其中包括有矽鰭片以及位在矽鰭片上之縮合矽 鍺鰭片。鰭片1〇〇之寬度W1可實質介於10奈米至80奈 米之間，如後續段落即將討論之内容，雖然較大或較小之 寬度均可使用，寬度係取決鍺鰭片之較佳寬度。 在較佳之實施例中，如第7圖所示，以介電材料39填 充開口 38(參照第6圖）’其中較佳之介電材料39係以次大 氣壓化學氣相沈積法（Sub-Atmospheric Chemical Vapor Deposition ; SA-CVD)所形成之氧化矽。在其他實施例中，
介電材料39係使用高密度電漿化學氣相沈積法 (High-Density Plasma Chemical Vapor Deposition ； HDP-CVD)或玻璃上旋轉法（Spin-〇n_Glass ; SOG)所形成。 然後執行化學機械研磨（Chemical Meehaiiieal Polish ; CMP) 來平整化晶圓的表面，而形成淺溝渠隔離（Shall〇w Trench Isolation，STI)區域40，以及如第8圖所示之最終結構。 遮罩層34用來做為化學機械研磨終止層。 請參照第9圖，使得暴露出之淺溝渠隔離區域4〇產生 凹陷。凹陷距離D2與縮合之補層26的厚度有關。在凹 之步驟後，淺溝渠隔離區域4〇之上表面42可與介於矽 錯層26以及鰭片切w部份之間的介面等高或較低 於此介面。接著’在-含氫之環境中執行退火。 在第1〇圖’執行氧化反應，且形成緩衝氧化物(氧化 矽)46於黯片100的側壁。緩衝氧化物&可具有實質介於 ^奈米至6奈米之間的厚度。接著，如第 形成 硬遮罩(HardMa拳，硬遮罩48亦可錢切來形成。在 一例示性實關中，硬遮罩48具有實f介於a奈米至％ 12 1375283
奈米之間的厚度。例示性之形成方法包括低壓化學氣相沈 積法、電漿輔助化學氣相沈積法以及類似之方法。形成之 溫度可實質介於400°C至90〇。〇之間。 接著，如第12圖所示，執行乾蝕刻（Dry砑仏)以移除 硬遮罩48之水平部份。至少部份之硬遮罩48的垂直部份 保留而不加以姓刻。藉由硬遮罩48之剩餘部份來暴露出淺 溝渠隔離區域40。請參考帛13目，執行等向性飯刻較 佳係渴姓刻。硬_罩48之剩餘部份係、實質未似，卜由於等 向性韻刻，凹陷部50延伸至硬遮148之剩餘部份的下方， 且暴露出鰭片100中矽鰭片的側壁。 隹弟14圖中 命丨 切1”迫一芡之氧化反應，且鰭片1〇〇 j ^之部份被氧化而形成氧化區域&要留意的是氧化疫 #。隔離區域4〇之材料類似或不_ 希望氧化反應僅發生於鰭片1〇〇之矽鰭 的部份。，的是，形成於鰭片100相對㈣ 片1〇〇的上面在—起，使得包含㈣鍺部份之南 Μ 1ΛΛ4 卩伤元全與矽基材20隔離。另外，形虚於翻 的氧化區域5如 .糸實質完整地(儘管並不完全)將鰭片100的i 終氧：區5材20隔離。由於氧化作用’故體積增加:畢 匚域52之寬度W2可實質介於鰭片10〇之 } ^W2 離_之4::=:== 比例係實質介…至3.0之間。由於具有阻土 13 阻止^<衝穿電流的功能’氧化區域52亦可稱之為衝穿 如第14圖所示，鰭片1〇〇的底 4〇的頂:處是’甚至假如環繞鰭片_ = =溝渠隔離區域4〇之頂表;片之高度(獨立 致淺溝渠隔離區域40之頂表面高二二固定的’且其 致最f騎效顧料衫敎·;^數’㈣果將導 %參照第15圖，氧化物56填 化々Π %的頂表面高過於硬遮罩層34二3中二 形使咖r優異之間隙填充能力的= 氣相沈積法?相沈積法以及高密度電漿化學 填充能例中，則因為其優異之間隙 研磨以玻璃上旋轉法氧化物。織執行化學機械 罩48，it過里之氧化物56 ’直到暴露出遮罩層34/硬遮 的紙止声、^罩層⑽硬料48可时做為化學機械研磨 ，、、止層。最終之結構係如第16周所示。 軔佔Ϊ? Π圖中’執行一蝕刻使得氧化物56產生凹陷。 ，疋，韻刻終止於與氧化區域52之頂表面等高之位 之頂1終i於氧化區域52之頂表面上且距離氧化區域52 r熱面實f小於20奈米之任意位置。在第18圖中，移 除剩餘的遮罩層34/硬遮罩48部份。 可從轉示三維縮合法，此命名之由來係、因為縮合 介「面與側壁開始產生。較佳的是，在實質 ' 至880 C之間的溫度下執行三維縮合法。三維縮 1375283 合法導致㈣子朝外移動，因此形錢切 鰭片100的頂部（包含有縮合之矽鍺）更一 9 。原來之 實質純化之鍺鰭片200,其中鍺鰭片2〇〇 ;=縮合以形成 片100之剩餘部份的寬度W1。再者，鍺見度％3小於鰭 部份重疊於鰭片100的中心部份，鰭片2 200僅垂直地 方向上延伸超越了鍺鰭片2〇〇的邊^ 在所有的侧面 r，純錯鰭請的底部表面可邊能= t的錯原子百分比可實質高於9G%，且可 ^ ^ _ 鍺）。然後如第20圖所示，移除緩$ 、100%(純 丄Γ7 抄降緩衝氧化物46盘氧介石々爲 6〇。在最終的結财，㈣渠祕區域40、氧it 52 以及氧化物56等介電區域互相接合在-起以形成一域Λ2 絕緣體，其中複合絕緣體區域包# 形成一设& 的第-部份(氧化區域52射==:片，上 ,,,λ* 乂及位在鰭片100相對兩 侧的第二部份（包括淺溝渠隔離區域4G以及氧化物並 中第二部份可具有低於第—部份的底部。 〃 接著’如第21圖之透視圖所示，可形成包括有閘極介 電層（GateDieleCtriC)64 以及閘極電極(GateElectrode)66 的 閑極堆疊(⑽3滅）’以形成鰭式場效電晶體。如此技術 湏域所熟知’ ▼使用前閑極(Gate_First)法或後閘極 CGate-Last，來形成閘極堆叠。使用前閘極或後閘極法來 形成閘極堆s的過程已在美國專利中請號l2/116，Q74的專 利案中討論過，在此將其―併私作為參考，因此不再於 此加以討論。 本發明之實施_❹個具有優勢之特徵 。鍺奈米線 與最終之料場效電晶體可在不使科貴之絕緣層上覆鍺 15 1375283 或絕緣層上覆矽鍺（SiGe-〇n_insulator)基材狀況下加以形 成。由於鍺較高電子遷移率與電洞遷移率，可改盖鰭式場 效電晶體的驅動電流。由於衝穿阻止層的形成，^用本發 明之實施例所形成之鰭式場效電晶體已經降低，且可能已 經實質消除衝穿電流，其中衝穿阻止層將縛式場效電晶體 之源極與汲極區域完全隔離於可能之衝穿電流路徑之外。 此外，通道區域不需要高雜質（井）濃度，且續片高度不需 要隨著淺溝渠隔離區域之頂表面位置不同而變化。 φ 雖然本發明及其優點已經詳述如上，可理解的是，在 不脫離後述請求項所定義之本發明範圍和精神内，當可做 各種的更動、替代和满飾。此外，本發明之範圍並非欲限 制在本說明書所述之製程、機器、製造以及物質、方式、 方法和步驟之組成㈣定實_巾。此技術領域中具有通 *技藝者將可從本發明之揭露輕易地理解到：前述之製 程、機器、製造以及物質、方式、方法或步驟’不論是已 &存在或後續將發展的，只要能夠如本說明相對應之實施 # 例一般執行實質相同功能或達到實質相同之結果，均包括 在本發明之範圍内。因此’所附申請專利範圍意欲將這類 的製程、機H、製造、物質㉟成、方式、方法齡驟包含 於其範圍中。 【圖式簡單說明】 為了能夠對本發明及其優勢有更完整之理解，請參照 ，上述之詳細說明並配合相應<圖式，其中圖式内容說明如、 下0 1375283 第1、2、以及4至20圖係繪示製造本發明之第一實 施例之中間階段的剖面示意圖，其中包括鍺鰭片的形成； 第3圖係概略性地繪示主體矽基材、矽鍺層以及上覆 氧化矽層中鍺原子百分比的示意圖。 第21圖係繪示使用第1、2、以及4至20圖中所示之 步驟製造之鰭式場效電晶體的立體示意圖。
半導體基材(矽基材） 22 :矽鍺層 【主要元件符號說明】 20 24 :遮蔽層 28 :氧化矽層2 30_2 :線 32 :焊墊層 36 :光阻劑 39 :介電材料 42 :上表面 48 :硬遮罩 52 :氧化區域 60 :氧化矽層 66 :閘極電極 200 :鍺鰭片 D2 :凹陷距離 H2 :高度 W2 :寬度 26 :碎錄層 30_1 :線 30_3 :線 34 :遮罩層 38 :開口 40 :淺溝渠隔離區域 46 :缓衝氧化物 50 :凹陷部 56 :氧化物 64 :閘極介電層 100 :鰭片 D1 :凹陷深度 H1 :高度 W1 :寬度 W3 :寬度 17

Claims (1)

1375283 七、申請專利範園： . 1.一種形成半導體結構之方法，包括： 提供一複合基材，包括一主體矽基材與緊鄰於該主體 矽基材之上的一石夕鍺層； 對該碎錄層執行一第一縮合，以形成一縮合碎鍺層， 其中該縮合矽鍺層具有一實質均勻之鍺濃度； 蝕刻該縮合矽鍺層與該主體矽基材之一頂端部份，以 形成一複合鰭片，其中該複合鰭片包括一矽鰭片與位在該 φ 矽鰭片上之一縮合矽鍺鰭片； 氧化該矽鰭片之一部份；以及 對該縮合矽鍺鰭片執行一第二縮合。 2.如請求項1所述之形成半導體結構之方法，其中該 第一縮合係在實質介於825°C至880°C之間之一溫度下執 行。 3.如請求項1所述之形成半導體結構之方法，其中該 第二縮合係在實質介於825°C至880°C之間之一溫度下執 行0 4. 如請求項1所述之形成半導體結構之方法，其中該 第一縮合係實質轉換整個該矽鍺層成該縮合矽鍺層。 5. 如請求項1所述之形成半導體結構之方法，其中該 1375283 氧化該矽鰭片之該部份之步驟包括： . 填充一介電材料，以在該矽鰭片嵌入一底部部份； 形成一遮罩，以覆蓋該縮合矽鍺鰭片之一頂表面與複 數個側壁，其中該矽鰭片之該部份被暴露出；以及 執行一氧化反應，以氧化該矽鰭片之該部份，並形成 一氧化區。 6. 如請求項5所述之形成半導體結構之方法，更包括 φ 在執行該第二縮合之步驟前，形成一額外介電材料至與該 氧化區域之一頂表面實質等高之一高度。 7. 如請求項1所述之形成半導體結構之方法，更包括： 在執行該第二縮合之步驟前，形成一氧化層覆蓋該縮 合矽鍺鰭片； 在執行該第二縮合之步驟後，移除該氧化層以及由該 第二縮合所形成之一額外氧化層； ® 形成一閘極介電層於該縮合矽鍺鰭片上；以及 形成一閘極電極於該閘極介電層上。 8. —種形成半導體結構之方法，包括： 提供一主體矽基材； . 磊晶成長一矽鍺層於該主體矽基上；以及 , 在實質介於825°C至880°C之間之一溫度下，對該矽鍺 層執行一第一縮合，以形成一縮合石夕鍺層。 19 1375283 . 9.如請求項8所述之形成半導體結構之方法，其中執 行該第一縮合直到整個該矽鍺層縮合，以及整個該縮合矽 ' 鍺層具有實質均勻之一原子百分比。 10. 如請求項8所述之形成半導體結構之方法，更包括： 蝕刻該縮合矽鍺層與該主體矽基材之一頂端部份以形 成一複合鰭片，其中該複合鰭片包括一矽鰭片與位在該矽 φ 鰭片上之一縮合矽鍺鰭片； 氧化該矽鰭片之一較高部份，其中該縮合矽鍺鰭片並 未被氧化；以及 對該縮合矽鍺鰭片執行一第二縮合，以形成一實質純 化之錯籍片。 11. 如請求項8所述之形成半導體結構之方法，更包括 在執行該第一縮合之步驟前，形成一遮蔽層於該矽鍺層。 12. —種形成半導體結構之方法，包括： 提供一主體矽基材； 磊晶成長一矽鍺層於該主體矽基； 對該石夕錯層執行一第一縮合，以形成一縮合石夕鍺層， , 其中該第一縮合係執行於一高溫中； . 蝕刻該縮合矽鍺層與該主體矽基材之一頂端部份，以 形成一凹陷部以及位在該凹陷部的一複合鰭片，其中該複 20 1375283 合鰭片包括一矽鰭片與位在該矽鰭片上之一縮合矽鍺鰭 . 片； 填充一第一介電材料至該凹陷部中； 蝕刻該第一介電材料直到該縮合矽鍺鰭片被暴露出； 形成一遮罩覆蓋該縮合矽鍺鰭片之一頂表面與複數個 側壁； 凹陷該第一介電材料以暴露出該矽鰭片之:一部份的複 數個側壁；. • 氧化該矽鰭片之該部份以形成一絕緣體； 填充一第二介電材料於該第一介電材料上，其中該第 二介電材料之一頂表面係實質與該絕緣體之一頂表面等 高；以及 對該縮合矽鍺鰭片執行一第二縮合，以形成一實質純 化之鍺鰭片。 13. 如請求項12所述之形成半導體結構之方法，其中 • 在氧化該矽鰭片之該部份之步驟後，該矽鰭片之一較低部 份未被氧化。 14. 如請求項12所述之形成半導體結構之方法，其中 該高溫包括實質介於825°C至880°C之間之一溫度。 , 15.如請求項12所述之形成半導體結構之方法，其中 執行該第一縮合之步驟係在實質介於825°C至880°C之間 21 1375283 之一溫度下執行。 16.如請求項12所述之形成半導體結構之方法，其中 該絕緣體由該矽鰭片之一側邊穿透至該矽鰭片之一相對侧 邊。 17. 如請求項12所述之形成半導體結構之方法，其中 在凹陷該第一介電材料以暴露出該矽鰭片之談部份之該些 • 侧壁之步驟後，該第一介電材料之一頂表面並未高於該縮 合石夕鍺縛片之一底部表面。 18. 如請求項12所述之形成半導體結構之方法，其中 該實質純化之鍺鰭片具有實質大於90%的一鍺原子百分 比。
22
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US8048723B2 (en) 2011-11-01
TW201023275A (en) 2010-06-16
US8957477B2 (en) 2015-02-17
US20120025313A1 (en) 2012-02-02
CN101752258B (zh) 2011-09-07
US20100144121A1 (en) 2010-06-10

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