1375041 九、發明說明： 【發明所屬之技術領域】 本發明係有關於-種脈波產生的_，尤指依據—輸人時脈之 一週期來產生一脈波的裝置與其方法。 【先前技術】 隨著電子電路的發展，電路系統也越來越複雜。該電路系統内 包含有許多子電路’每一子電路的操作頻率均有可能會互相不 同1且該子電路麵統操作的過程巾村能倾料、統的要求而 j變其操作解；因此鮮偵測輯扮演的⑽也齡越重要。另 :方面’在追求電路祕越來越高的操作鮮下，解偵測器所 f貞測的頻率的解析度也提高了，使得在習知技術中的頻率偵測 為亦越複雜。而且，一般上’習知技術尚無法用一簡單結構的頻 率偵測器來提供-較高解析度的頻率_，且關單結構的頻率 偵測器僅能區分輸人頻率為高頻或低頻而無法偵測出其頻率值。 因此，為了不提高電路系統的負擔，—較簡單結構且較寬頻之頻 率偵測器勢必成為一發展趨勢。 為了更清楚描述出習知技術所面臨的問題，在此以一雙倍逮隨 機存取記《 (DDRRAM)作_，細本發狀顧並不以此 為限。一般而言，當微處理器欲存取一記憶體時，該微處理器會 1375041 發一項取峨麵記髓的控制電路，其憎讀取卿 部時脈同步，此時，習知記憶體控制電路會具有一延遷計數器 (yc_㈣’其係提供一延遲時間(延遲週期數)於該讀取訊 唬使得該„己億體具有足夠的時間來存取該特定位址。然而 該憶體的操作時脈之鮮細極寬，使得延遲計數ϋ在高頻和低 頻的鱗下需提供不_的延_縫，即在高頻下的延遲週期 數較多，而在低頻下的延遲週期數較少。但是由於電路本旦 有其内部鱗遲，因此在高頻下當_路⑽的輯和該高頻時 ^虎的梅_，f喊棚侧她冑取訊號和 ^ #時脈具錢妨同辦_舰的延剌贿，使 =!到錯誤的訊號。因此，若可提供-具有頻率偵二 。，时细搶記龍之操㈣脈_率，並依據該頻 t測器的侧結絲輕該延遲計數⑽延遲時間，將得以解 决上述問題。 【發明内容】 種脈波產生器與其 因此本發明的主要目的之—係在於提供一 方法以解決以上所述之問題。 ί |] 8 1375041 用來於該輸入時脈的每一週期產生一脈衝訊號；一啟動裝置，搞 接於該週期脈衝產生單元，用來依據該重置訊號以啟動該脈波產 生器並依據έ亥脈衝§凡號產生一第一訊號與一第二訊號；一觸發訊 號產生裝置，耦接於該啟動裴置，用來依據該第一、第二訊號分 別產生一第一觸發訊號與一第二觸發訊號，其中該第一、第二觸 發訊號之時間差距為該輸入時脈之一週期；以及一拴鎖(丨的也)裝 置，耦接於該觸發訊號產生裝置，用來依據該第一、第二觸發訊 號拾鎖住一脈波。 本發明之另一實施例提供一種脈波產生方法，用來產生具有 輸入時脈之一週期之一脈波，包含有··於該輸入時脈的每一週 期頻率產生一脈衝訊號；依據一重置訊號以及該脈衝訊號產生一 第一汛唬與一第二訊號；依據該第一、第二訊號分別產生一第一 觸發㈣與-第二觸發訊號，其中該第…第二觸發訊號之時間 差距為該輸人時脈之—週_率；以及依卿帛…第二觸發訊 號拴鎖住該脈波。 【實施方式】 月 > 考第1圖’第1圖所示為本發明頻率偵測裝置100之一 貫化例的不思圖。頻率4貞測裝置函係用來偵測一輸入時脈Vdk (例如記憶__輸）之-鮮U。本實關中，頻率偵測 1375041 裝置100包含有：一脈波產生器1〇2、一數位訊號產生裝置丨04 . 以及一解碼裝置106 ’其中脈波產生器102耦接於輸入時脈Vlv，1375041 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a type of pulse wave generation, and more particularly to a device and method for generating a pulse wave based on a period of the input clock. [Prior Art] With the development of electronic circuits, circuit systems have become more and more complicated. The circuit system includes a plurality of sub-circuits 'the operating frequency of each sub-circuit may be different from each other 1 and the process of the sub-circuit operation of the sub-circuit can be turned over, and the operation is changed; The more important the (10) role played by the detection series is. In addition: in the pursuit of higher and higher operation of the circuit, the resolution of the frequency of the detector is also improved, making the frequency detection in the prior art more complicated. Moreover, in general, the conventional technology cannot be provided with a simple structure of the frequency detector - the higher resolution frequency _, and the frequency detector of the single structure can only distinguish the input frequency from high frequency or low frequency. It is impossible to detect its frequency value. Therefore, in order not to increase the burden on the circuit system, a frequency detector having a simpler structure and a wider frequency is bound to become a development trend. In order to more clearly describe the problems faced by the prior art, it is not limited to this with a double access random access record (DDRRAM). Generally speaking, when the microprocessor wants to access a memory, the microprocessor sends a control circuit for the 1375041 to take care of the clock, and then reads the clock synchronization of the Qing Dynasty. At this time, the conventional memory The body control circuit will have an extension counter (yc_(four)' which provides a delay time (the number of delay cycles) to the read signal so that the hexagram has sufficient time to access the particular address. The operation clock of the body is extremely wide and wide, so that the delay count ϋ needs to provide a delay slot at the high frequency and low frequency scale, that is, the number of delay cycles at high frequencies is large, and the delay at low frequencies The number of cycles is small. However, since the circuit has its internal scales late, when the high frequency is used, the _ road (10) and the high frequency, the tiger's plum _, f shouted the shed side when she took the signal and ^ #脉 钱 钱 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The side knot of the detector is lighter than the delay count (10) delay time, which will solve the above problem. The main purpose of the present invention is to provide a method for solving the above problems. ί |] 8 1375041 is used to generate a pulse signal every cycle of the input clock; The pulse generating unit is configured to activate the pulse wave generator according to the reset signal and generate a first signal and a second signal according to the 脉冲 脉冲 pulse number; a trigger signal generating device coupled to the pulse signal generating unit The first trigger signal and the second trigger signal are respectively generated according to the first and second signals, wherein a time difference between the first and second trigger signals is one cycle of the input clock; A shackle device is coupled to the trigger signal generating device for latching a pulse according to the first and second trigger signals. Another embodiment of the present invention provides a pulse wave generating method. And generating a pulse wave having one cycle of the input clock, comprising: generating a pulse signal at each cycle frequency of the input clock; generating a first according to a reset signal and the pulse signal And a second signal; generating a first trigger (four) and a second trigger signal according to the first and second signals, wherein the time difference between the second trigger signal is the time of the input clock _ rate; and the second trigger signal 拴 lock the pulse wave. [Embodiment] Month > Test 1 FIG. 1 is a consistent example of the frequency detecting device 100 of the present invention. The frequency 4 detection device function is used to detect an input clock Vdk (such as memory __transmission) - fresh U. In this real off, frequency detection 1375041 device 100 includes: a pulse generator 1 〇2, a digital signal generating device 丨04. and a decoding device 106', wherein the pulse generator 102 is coupled to the input clock Vlv,
CIK 用來擷取輸入時脈Vcik之單一週期T以產生一脈波vpulse;數位訊 號產生裝置104耦接於脈波產生器1〇2，用來將脈波Vpuise轉換成 複數個邏輯值，如圖所示，數位訊號產生裝置1〇4包含有 延遲模組1042耦接於脈波vpulse，用來依據複數個延遲單元 1042a〜l〇42n (本實施例中，每—延遲單元1〇42&〜1〇4211均提供一 • 單位延遲量U延遲脈波Vpulse以分別產生複數個延遲後脈波 Vpuise ⑴〜Vpuise ⑻， 此外，數位訊號產生裝置1〇4另包含一取樣模組 1044耦接於延遲模組1042，用來分別依據複數個延遲後脈波 VpuMU〜Vpulse⑻取樣脈波vpulse以產生複數個邏輯值Di〜Dn。解碼裝 置106係耦接於數位訊號產生裝置1〇4，用來依據複數個邏輯值 D广Dn解碼出輸入時脈Vdk之頻率。 釀言青注意’本實施例中，數位訊號產生裝置1〇4中的延遲模組 麗包含有複數個延遲單元1042a〜顺2n ’其以串接方式前後連 . 接’每—延遲單元麗a〜1042η均有-輸出端來產生每—延遲後 脈波Vpulse⑴〜VPuMn)。取樣模組1044包含有複數個暫存元件(例如 正反器)H)44a〜1G44n，其係依據複數個延遲後脈波 的觸發來讀取脈波Vp*以產生複數個邏輯值Dl〜Dn。然而，第1 圖所示僅為本發明之-實施例，並非用來作為本發明的限制，舉 丄375041 .例來說，暫存元件馳〜顯並非-定要用正反器來加以實作。 3方面’本發明頻率偵測裝置100之脈波產生器102另轉 接至-重置(reset)訊號&，其中若脈波產生器川2收到重置訊號 Sr則脈波產生益1()2|被重置以重新進行娜輸入時脈4之一 週期的操作。如圖所示’脈波產生器1〇2包含有：一週期脈衝 (impulse)產生單凡1022輕接至輸入時脈乂出，用來於輸入時脈4 •的每-週期產生-脈衝訊號Si; 一啟動裝置刪粞接於週期脈衝 產生早7L 1022,用來依據重置訊號Sr以啟動脈波產生器1〇2並依 據脈衝訊號&產生-第-訊號V]與一第二訊號％ ; 一觸發訊號 產生裝置1026搞接於啟動裝置1024，用來依據第…第二訊號 Vi、V2分別產生-第一觸發訊号虎％與一第二觸發訊號&，其中 第一、第二觸發船虎stl、st2之時間差距為輸入時脈Vdk之一週期 T;以及一拴鎖(latch)裝置1〇28耦接於觸發訊號產生裝置腦， # 用來依據第-、第二觸發訊號stl、Sts拾鎖出所要的脈波V*， 且重置訊號Sr之反相訊號亦耦接至栓鎖裝置1〇28。在本發明中， 週期脈衝產生單元1022包含有：一反相延遲器1031，用來反向輸 入時脈vdk以產生一反向輸入時脈vclkbar;以及一及閘1〇32耦接 於反相延遲1031與輸入時脈Vclk，用來依據輸入時脈v他與反 向輸入時脈Vcikbar產生脈衝訊號Si。啟動裝置1024包含有.一第 一正反器1033，其資料端D耦接於一供應電壓Vdd而固定接收一 參考邏輯值”1”，其非反向輸_係輸料—職Vi; 一第二 正反器刪，其資料端叫接於供應電壓Vdd而固定地接收參考 邏輯值”1”，其歧向輸_⑽輸料二峨H 一及閉 1035 ’其兩輸人料、接於第—正反H刪之反向輸 出端Qbar#脈衝訊號Si ’其輸出端係輕接於第一正反器觀之時 脈端CLK;以及-第二及閘1〇36，其兩輸入端％,分職接 於脈衝訊號S,與第-訊號Vl，其輸出端細接於第二正反器· 之時脈端CLK。觸發訊號產生裝置1()26則包含有：—第一反相延 遲器1037補於第-訊號Vi ’用來反向第—訊號％以產生一第 lbar -反向訊號V‘以及-第—反及閘_雜於第—反相延遲器 1037與第-峨Vl ’时依鮮—職％與第—反向訊號乂 產生第-觸發訊號Stl ; 一第二反相延遲器咖輕接於第二訊號 V2，用來反向第二訊號v2以產生—第二反向訊號V—;以及一第 二反及閘1041耗接於第二反相延遲器咖與第二訊號^，用來 依據第二訊號v2與第二反向訊號V2W產生第二觸發訊號Sti。請 注意，本發日种之反相延遲器不僅提供輸出輸入訊號之反相功 能’並提供一延遲量於該輸出訊號。 為了更請楚地描述本發明之精神所在，本實施例以輸入時脈 vclk之頻率^⑴為1GHz來說明。請同時參考第1圖與第2圖，第 2圖所示為第丨騎示之頻率制裝置⑽的操作時相。從第2The CIK is used to capture a single period T of the input clock Vcik to generate a pulse vpulse; the digital signal generating device 104 is coupled to the pulse generator 1〇2 for converting the pulse Vpuise into a plurality of logical values, such as As shown in the figure, the digital signal generating device 1〇4 includes a delay module 1042 coupled to a pulse wave vpulse for use in accordance with a plurality of delay units 1042a~1〇42n (in this embodiment, each delay unit 1〇42& 〜1〇4211 provides a unit delay amount U delay pulse Vpulse to generate a plurality of delayed pulse waves Vpuise (1) ~ Vpuise (8), respectively, in addition, the digital signal generating device 1 〇 4 further includes a sampling module 1044 coupled to The delay module 1042 is configured to generate a plurality of logic values Di to Dn according to the plurality of delayed pulse waves VpuMU to Vpulse (8), respectively. The decoding device 106 is coupled to the digital signal generating device 1〇4 for The plurality of logic values D wide Dn decodes the frequency of the input clock Vdk. In the present embodiment, the delay module in the digital signal generating device 1〇4 includes a plurality of delay units 1042a~shun 2n' Concatenated Before and after connection 'each - Li a~1042η have delay unit - to produce an output terminal of each - delayed pulse Vpulse⑴~VPuMn). The sampling module 1044 includes a plurality of temporary storage elements (such as flip-flops) H) 44a~1G44n, which read the pulse wave Vp* according to the trigger of the plurality of delayed pulse waves to generate a plurality of logic values D1~Dn . However, the first embodiment is merely an embodiment of the present invention, and is not intended to be a limitation of the present invention, for example, 375041. For example, the temporary storage component is not necessarily determined to be implemented by a flip-flop. Work. In the third aspect, the pulse wave generator 102 of the frequency detecting device 100 of the present invention is further switched to a reset signal & wherein if the pulse wave generator 2 receives the reset signal Sr, the pulse wave generates a benefit 1 () 2| is reset to re-enter the operation of the input clock one cycle. As shown in the figure, the pulse generator 1〇2 includes: a periodic pulse (impulse) generated by the single 1022 to the input clock pulse output, used to generate the pulse signal every clock cycle of the input clock 4 • Si; a start device is connected to the periodic pulse to generate 7L 1022 early, used to start the pulse generator 1〇2 according to the reset signal Sr and generate a -first signal V and a second signal according to the pulse signal & A trigger signal generating device 1026 is connected to the starting device 1024 for generating a first trigger signal tiger % and a second trigger signal & respectively, according to the second signal Vi, V2, wherein the first and the first The time difference between the triggering ship tigers st1 and st2 is one cycle T of the input clock Vdk; and a latch device 1〇28 is coupled to the trigger signal generating device brain, # is used according to the first and second triggers The signal stt, Sts picks up the desired pulse wave V*, and the inverted signal of the reset signal Sr is also coupled to the latching device 1〇28. In the present invention, the periodic pulse generating unit 1022 includes: an inverting delay 1031 for inverting the clock vdk to generate a reverse input clock vclkbar; and a gate 1 〇 32 coupled to the inversion The delay 1031 and the input clock Vclk are used to generate a pulse signal Si according to the input clock v and the reverse input clock Vcikbar. The starting device 1024 includes a first flip-flop 1033, and the data terminal D is coupled to a supply voltage Vdd and fixedly receives a reference logic value "1", which is non-reversely transmitted. The second flip-flop is deleted, and the data terminal is connected to the supply voltage Vdd to receive the reference logic value "1" fixedly, and the differential transmission_(10) is sent to the second and the lower 1035. In the reverse output terminal of the first-positive-reverse H-cut Qbar# pulse signal Si', its output is lightly connected to the clock terminal CLK of the first flip-flop; and - the second gate 1〇36, its two inputs The terminal % is connected to the pulse signal S, and the first signal V1, and the output end thereof is connected to the clock terminal CLK of the second flip-flop. The trigger signal generating device 1 () 26 includes: - the first inverting delay 1037 is supplemented by the first signal Vi ' to reverse the first signal % to generate a lbar - reverse signal V' and - - The anti-gate _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The second signal V2 is used to reverse the second signal v2 to generate a second reverse signal V-; and a second reverse gate 1041 is connected to the second inverted delay device and the second signal ^, The second trigger signal Sti is generated according to the second signal v2 and the second reverse signal V2W. Please note that this type of inverting retarder not only provides the inverting function of the output input signal' and provides a delay amount to the output signal. In order to further describe the spirit of the present invention, the present embodiment is described by the frequency ^(1) of the input clock vclk being 1 GHz. Please refer to Fig. 1 and Fig. 2 at the same time. Figure 2 shows the operating phase of the frequency system (10) of the first ride. From the second
12 丄375041 圖可以得知，在初始的狀態下(即重置訊號sr為低電壓準位），第 、第二訊號Vi、V2均處於高電壓準位，脈波vpulse處於低電壓 準位的狀態，然而脈衝訊號Si卻不斷地在輸入時脈Vclk的每一周 期T產生(如第2圖所示）。當重置訊號sr在時間^輸入一脈波時， 第、弟一號V!、V2會切換至低電壓狀態，第一及閘ίο%之 輸出端會在時間tl之一訊號Va(於時脈端CLK)會使得非反向輸出 端Q之輸出第一訊號v!會切換成高電壓準位(參考邏輯值Vdd)。 此時，高電壓準位的第一訊號Vl會使得第二及閘1〇36的輸出端 會在時間b產生一訊號Vb於時脈端CLK，這時非反向輸出端q 之輸出第二訊號V2會切換成高電壓準位(亦即供應電壓Vdd)。可以 传知第—訊號Vi和第二訊號v2的切換時間差為輸人時脈4之 週期T，亦即Ins。請注意，本發明週期脈衝產生單元1〇22之 反向器咖不僅對反向輸入時脈Vdk提供反向輸入_ ， 更對反向輸入時脈vdkbar提供了-時間差At於輸入時脈4，然 而本發明之設計會使得該時間差At遠小於輸入時脈V他之週期 T(lnS)而不影響本實施例之正常操作。 請接著參考第2圖，當高電壓準位的第—訊號％和高電壓準 位的第二訊鮮2先後通酬發贼產絲置職時，第一觸發 為虎stl和第二觸發訊號St2會分別在時間&和q被產生，同樣地， W k間相差lnS。由於觸發訊號產缝置刪的操作相同於 13 1375041 週期脈衝產生單元1022,因此不多加贅述。由於拴鎖裝置ι〇28 之輸出端N,3的初始值為低電壓準位，因此根據拴鎖裝置翻之 操作原理(為業界所習知，故不另於此贅述），高賴準位的第一訊 號Vi在時間t；j時將輸出端Nn從低電壓準位拴鎖至高電壓準位， 二:後π電壓準位的第二訊號％在時間t時將輸出端Να從該高電 壓準位拾鎖回低電壓準位。因此，具有輸入時脈^之一週期τ 之脈波Vpulse就被產生了 (如第2圖所示）。 請同時參考第1圖、第2圖與第3圖，第3圖所示為第㈣ 所示之頻率偵測裝置卿對脈波v㈣進行取樣的操作時序圖。當 所產生之脈波u傳送至後續的數位訊號產生裝置刚以及解 碼裝置106時’在理想的情況下，每-暫存元件1044a〜1044η的 資料端(D)會同時在時間*3接收到脈波Vpulse，然而，由於延遲單元 1042a〜1042η的存在使得每一暫存元件谢如〜⑴他的時脈端 ^ t3+D^ ^ ^ ^ t3+n，Du〇it#^ 騎遲舰波νριι1_〜ν_φ)。目此，延料㈣似〜浦n就會 t3+Dunit ' t3+2Dunit、···、t3+u皮觸發，然而由於脈 波Vpulse只有在週期τ的時間才會是高電壓準位，即每一暫存元件 職〜雜„的資料端⑼只有在t3至柯的時間財是輸出高電 [準位j亦即摘值η,因此只有在^至柯的時間内被觸發 、遲單一才s輸出同電壓準位的邏輯值，其他則為邏輯值，，『。 1375041 接者，所有的_值Dl〜Dn會被輸人解碼裝請，最後解碼 _會依據所接收之所有邏輯值Di〜Dn_應的數值來決定出輸 入_4之醉由於解碼裝置對邏輯值㈣。進行 碼的操作__σ，因此在此_述。独上所揭露的内 容可以得知，每-賴單元的單位延輕Dunit__^ 進饤偵測的解析度，且延遲模組1〇4所提供的總延遲量洲 得小於輸入時脈Vdk之週期τ以便正確地雜輸人時脈^的 頻羊U，以本實施例之輪人時脈^之頻率f⑽為咖為例時， 則n*Dunit必須大於lnS。 ☆凊參考“圖，第4 _本發·率偵測方法之—實施例的 4圖。本發_率偵測方法係應用於第1圖所示之頻率偵測裝 置觸，_象_ I其爛單地歸納如 下. 步驟402 : 於輸入時脈Vdk的單_週期產生一脈衝訊號§ . 步驟依據脈衝訊號s，產生—第—訊號％與―第^ ’ 步驟406:依據第―、第二訊號％ …2 2刀另彳產生—第一觸發訊號 U與-第二觸發訊號St2，其中第—、第二觸發訊號 .Stl、St2之時縣距為輸人時脈Velk之-週期τ; 步驟408 .依據第一、第二觸發訊號％、St2拾鎖出—脈波V〆 1375041 步驟410 .使用複數個單位延遲量延遲脈波v_卩分別產生 複數個延遲後脈波vP_)〜W 步驟412 .分別依據複數個延if後脈波Vp㈣⑴〜Vp⑽⑻取樣脈波12 丄375041 The figure shows that in the initial state (ie, the reset signal sr is a low voltage level), the second and second signals Vi and V2 are at a high voltage level, and the pulse vpulse is at a low voltage level. State, however, the pulse signal Si is continuously generated every cycle T of the input clock Vclk (as shown in FIG. 2). When the reset signal sr inputs a pulse at time ^, the first and second V!, V2 will switch to the low voltage state, and the output of the first and gate ίο% will be at the time t1, the signal Va (at time) The pulse terminal CLK) causes the output of the non-inverted output terminal Q, the first signal v!, to switch to a high voltage level (reference logic value Vdd). At this time, the first signal V1 of the high voltage level causes the output of the second AND gate 1〇36 to generate a signal Vb at the clock end CLK at time b, at which time the second signal of the non-inverting output terminal q is output. V2 will switch to a high voltage level (ie, supply voltage Vdd). It can be known that the switching time difference between the first signal Vi and the second signal v2 is the period T of the input clock 4, that is, Ins. Please note that the inverter of the periodic pulse generating unit 1〇22 of the present invention not only provides an inverse input _ to the reverse input clock Vdk, but also provides a time difference At the input clock 10 to the reverse input clock vdkbar. However, the design of the present invention causes the time difference At to be much smaller than the period T (lnS) of the input clock V without affecting the normal operation of the embodiment. Please refer to FIG. 2 again. When the first signal of the high voltage level and the second signal of the high voltage level are issued, the first trigger is the tiger stl and the second trigger signal. St2 will be generated at time & and q, respectively, and Wk will differ by lnS. Since the operation of triggering the signal production is the same as the 13 1375041 periodic pulse generating unit 1022, no further description is provided. Since the initial value of the output terminals N, 3 of the 拴 lock device 〇 28 is a low voltage level, according to the operating principle of the shackle device (which is known in the industry, it is not described here), the high level The first signal Vi locks the output terminal Nn from the low voltage level to the high voltage level at time t; j, and the second signal % of the post-π voltage level at time t takes the output terminal Να from the high The voltage level is latched back to the low voltage level. Therefore, a pulse Vpulse having a period τ of the input clock ^ is generated (as shown in Fig. 2). Please refer to FIG. 1 , FIG. 2 and FIG. 3 at the same time. FIG. 3 is an operation timing chart of sampling the pulse wave v (four) by the frequency detecting device shown in the fourth (four). When the generated pulse wave u is transmitted to the subsequent digital signal generating device and the decoding device 106, 'in an ideal case, the data terminal (D) of each of the temporary storage elements 1044a to 1044n is simultaneously received at time *3. Pulse wave Vpulse, however, due to the existence of delay units 1042a~1042n, each temporary storage element is like ~(1) his clock terminal ^ t3+D^ ^ ^ ^ t3+n, Du〇it#^ riding late ship wave Νριι1_~ν_φ). Therefore, the extension (4) like ~ Pu will t3 + Dunit ' t3 + 2Dunit, ···, t3+u skin trigger, however, because the pulse Vpulse will only be at the high voltage level during the period τ, ie The data end (9) of each temporary component is only available at t3 to Ke. The time is high. [The level j is the value of η, so it is only triggered in the time of ^ to Ke. s output the logic value of the same voltage level, the other is the logic value, ". 1375041 Receiver, all _ values Dl ~ Dn will be decoded by the input device, the final decoding _ will be based on all the received logic values Di ~Dn_ should be the value of the input to determine the input _4 drunk due to the decoding device to the logical value (4). The operation of the code __σ, so here _. The content disclosed alone can be known, each unit The unit delays the resolution of the Dunit__^ detection, and the total delay provided by the delay module 1〇4 is less than the period τ of the input clock Vdk in order to correctly mismatch the frequency of the clock. When the frequency f(10) of the wheel clock of the present embodiment is taken as an example, the n*Dunit must be greater than lnS. ☆ 凊 Refer to "Figure, 4th" _ This is a rate detection method - Figure 4 of the embodiment. The detection method of the present invention is applied to the frequency detecting device shown in FIG. 1, and the _I_I is summarized as follows. Step 402: Generate a pulse signal in the single_cycle of the input clock Vdk § The step according to the pulse signal s, generating - the first signal % and the "the second step 406: according to the first -, second signal % ... 2 2 knife generated - the first trigger signal U and - the second trigger signal St2, Wherein the first and second trigger signals. St1 and St2 are the time interval of the input clock Velk-cycle τ; Step 408. According to the first and second trigger signals %, St2, the lock-out pulse-V〆1375041 Step 410: Using a plurality of unit delay amount delay pulse waves v_卩 respectively generate a plurality of delayed pulse waves vP_)~W Step 412. Sample pulse waves are respectively determined according to a plurality of delayed if/after pulse waves Vp(4)(1)~Vp(10)(8)
Vpulse以產生複數個邏輯值&〜队；以及 步驟414 :依據複數個邏輯值Di〜d^碼出輸入時脈^之頻率 f〇ut ° 以上所述鶴本㈣之較佳實關，膽本發明_請專利範 圍所做之鱗變化娜飾，皆闕本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為本發明頻率偵測裝置之—實施例的示意圖。 第2圖為第1圖所示之解侧裝置的操作時序圖。 第3圖為第1圖所示之頻率偵測裝置對脈波進行取樣的操作時序 圖。 外 第圖為本發明頻率偵測方法之一實施例的流程圖。 【主要元件符號說明】Vpulse to generate a plurality of logical values & ~ team; and step 414: according to a plurality of logical values Di ~ d ^ code input frequency pulse ^ frequency f 〇 ut ° above said Heben (four) of the better real, timid Inventions _ The scales made by the scope of the patent are all covered by the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing an embodiment of a frequency detecting device of the present invention. Fig. 2 is a timing chart showing the operation of the unloading device shown in Fig. 1. Fig. 3 is a timing chart showing the operation of sampling the pulse wave by the frequency detecting means shown in Fig. 1. The external figure is a flow chart of an embodiment of the frequency detecting method of the present invention. [Main component symbol description]
頻率偵測裝置 脈波產生器 數位訊號產生裝置 ikSl 16 1375041Frequency detecting device Pulse generator Digital signal generating device ikSl 16 1375041
106 解碼裝置 1022 週期脈衝產生單元 1024 啟動裝置 1026 觸發訊號產生裝置 1028 栓鎖裝置 1031 、 1037 、 1039 反相延遲器 1032 、 1035 、 1036 及閘 1033 、 1034 正反器 1038 、 1041 反及閘 1042 延遲模組 1042a〜1042η 延遲單元 1044 取樣模組 1044a〜1044η 暫存元件 17106 decoding device 1022 periodic pulse generating unit 1024 starting device 1026 trigger signal generating device 1028 latching device 1031, 1037, 1039 inverting retarder 1032, 1035, 1036 and gate 1033, 1034 flip-flop 1038, 1041 inverse gate 1042 delay Modules 1042a to 1042n delay unit 1044 sampling modules 1044a to 1044n temporary storage elements 17