CN103812472B - The triggering device of anti-single particle transient state effect - Google Patents

Abstract

A trigger against single event transient effect relates to the field of integrated circuits. It solves the problem that the occurrence probability of single event transient effect in integrated circuit design is getting higher and higher, and its pulse interference signal is captured by the storage unit in the integrated circuit system, resulting in a higher and higher probability of soft error in the circuit. The initial signal is sent to the third pulse latch after being inverted by the first inverter and output to the XOR gate xor1 and the second inverter. The output signal of the XOR gate xor1 is inverted by the third inverter and simultaneously Send to the first pulse latch and the second pulse latch, the output signals of the first pulse latch and the second pulse latch are sent to the NAND gate, and the output signal of the NAND gate is inverted by the fourth The output signal of the third pulse latch is sent to the fourth pulse latch after being inverted by the second inverter, and the output signal of the fourth pulse latch is passed through the fifth The inverter inverts and sends to the exclusive OR gate xor2, and the output signal of the exclusive OR gate xor2 is the output signal of the flip-flop. The invention is suitable for eliminating single event transient effects.

Description

Trigger against single event transient effects

technical field

The invention relates to the field of integrated circuits, in particular to the field of triggers against single-event transient radiation effects in digital circuit systems.

Background technique

The single event transient effect (SingleEventTransient, SET) is a kind of single event effect in the circuit induced by the impact of high-energy particle beams such as alpha particle beams and neutrons. The main performance is to cause pulse interference signals on the combinational logic nodes in the circuit system. This signal is transmitted through the logic path and may be captured by storage units such as latches or flip-flops, thus causing soft errors in the digital circuit system.

With the continuous reduction of integrated circuit design size, node capacitance and characteristic voltage continue to decrease, and the clock frequency of digital IC system continues to increase. Some data show that, relatively speaking, the probability of SET effect is getting higher and higher, and its pulse The probability of interference signals being captured by memory cells in IC systems and causing soft errors in circuits is also increasing.

Contents of the invention

In order to solve the problem that in integrated circuit design, due to the higher and higher occurrence probability of single event transient effects, the pulse interference signal is captured by the storage unit in the integrated circuit system, resulting in a higher and higher probability of circuit soft errors, and proposes triggers against single event transient effects.

The flip-flops against single event transient effects include a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, an exclusive OR gate xor1, an exclusive OR gate xor2, The NAND gate, the first pulse latch, the second pulse latch, the third pulse latch and the fourth pulse latch, the initial signal D is sent to the exclusive OR gate xor1 and the first inverter at the same time, the initial The signal D is sent to the third pulse latch after being inverted by the first inverter, and the output signal of the third pulse latch is sent to the exclusive OR gate xor1 and the second inverter at the same time, and the output signal of the exclusive OR gate xor1 P is sent to the first pulse latch and the second pulse latch at the same time after being inverted by the third inverter, and the output signal of the first pulse latch and the output signal of the second pulse latch are both sent to the Not gate, the output signal check of the NAND gate is sent to the XOR gate xor2 after being inverted by the fourth inverter, and the output signal of the third pulse latch is sent to the fourth pulse lock after being inverted by the second inverter The output signal of the fourth pulse latch is inverted by the fifth inverter and then sent to the exclusive OR gate xor2, the output signal Q of the exclusive OR gate xor2 is the output signal of the flip-flop that is resistant to single event transient effects.

The circuit structures of the first pulse latch, the third pulse latch and the fourth pulse latch are the same, and the first pulse latch includes a first CMOS transmission gate, a second CMOS transmission gate, a sixth inverting device and the seventh inverter, the signal input end of the first CMOS transmission gate is used as the signal input end of the first pulse latch to receive an external input signal, the second CMOS transmission gate, the sixth inverter and the seventh inverter Connect sequentially to form a closed loop, the signal input end of the second CMOS transmission gate receives the output signal of the first CMOS transmission gate as the signal input end of the closed loop loop, and the signal output end of the sixth inverter is used as the signal of the closed loop loop output terminal, and the output signal of the closed-loop loop is sent to the NAND gate, and the clock signal clk_g1 and the clock signal clk_g1_n are both sent to the clock signal input terminals of the first CMOS transmission gate and the second CMOS transmission gate for detecting and sampling the first The transparent level control of the pulse latch, and the clock signal clk_g1 and the clock signal clk_g1_n are inverted, that is, clk_g1=~clk_g1_n.

The second pulse latch includes a third CMOS transmission gate, a fourth CMOS transmission gate, an eighth inverter and a first NOR gate, and the signal input terminal of the third CMOS transmission gate is used as the signal input of the second pulse latch terminal to receive an external input signal, the fourth CMOS transmission gate, the eighth inverter and the first NOR gate are sequentially connected to form a closed-loop loop, and the signal input terminal of the fourth CMOS transmission gate is used as the signal input terminal of the closed-loop loop to receive the third The output signal of the CMOS transmission gate, the signal input terminal of the first NOR gate is used as the signal output terminal of the closed-loop loop, and the output signal of the closed-loop loop is sent to the NAND gate, and the clock signal clk_g2 and the clock signal clk_g2_n are both sent to The clock signal input terminals of the third CMOS transmission gate and the fourth CMOS transmission gate are used to detect and sample the transparent level control of the second pulse latch, and the clock signal clk_g2 and the clock signal clk_g2_n are inverted, that is, clk_g2=~clk_g2_n , the clock signal clk_re is sent to an input terminal of the first NOR gate for providing high-level reset control for the second pulse latch.

The flip-flop resistant to single event transient effects further includes a local clock management unit including a ninth inverter, a second NOR gate, a first delay circuit, a second delay circuit, a first pulse generation logic circuit and the second pulse generation logic circuit,

The clock signal clk is sent to the ninth inverter and the first delay circuit at the same time, the output signal of the clock signal clk after being inverted by the ninth inverter is the clock signal clk_n, the clock signal clk_n is sent to the second NOR gate, the first The delay circuit delays the clock signal clk to output the clock signal clk_1, and the clock signal clk_1 is sent to the second delay circuit and the first pulse generation logic circuit at the same time, and the first pulse generation logic circuit performs pulse generation processing on the clock signal clk_1 and then outputs The clock signal clk_g1 and the clock signal clk_g1_n, the second delay circuit delays the clock signal clk_1 and then outputs the clock signal clk_2, the clock signal clk_2 is sent to the second NOR gate and the second pulse generation logic circuit at the same time, the second pulse generation logic The circuit performs pulse generation processing on the clock signal clk_2 to output the clock signal clk_g2 and the clock signal clk_g2_n, and the clock signal clk_n and the clock signal clk_2 are calculated by the second NOR gate to output the clock signal clk_re, that is, clk_re=clk_n⊕clk_2.

The first pulse generation logic circuit and the second pulse generation logic circuit have the same circuit structure, and the first pulse generation logic circuit includes a PMOS transistor, an NMOS transistor, an AND gate, a tenth inverter and an eleventh inverter, and the clock The signal is sent to the AND gate and the PMOS tube at the same time, the output signal of the PMOS tube is sent to the AND gate and the NMOS tube at the same time, and the output signal of the AND gate is inverted by the tenth inverter and the eleventh inverter in turn and then combined with the NMOS tube The output signals of are aggregated and output clock signal clk_g2 and clock signal clk_g2_n.

Beneficial effects: the anti-single event transient effect flip-flop proposed by the present invention effectively reduces or even eliminates the influence of the single event transient effect on the digital integrated circuit system, and at the same time, the extra area consumption is small, the timing requirement is simple, and it is beneficial to digital integration. The impact on the performance of the circuit system is small; the inversion signal of the input signal required by the XOR gates xor1 and xor2 can be provided by the internal node of the flip-flop without adding an additional inverter, thereby saving a certain area consumption.

Description of drawings

1 is a schematic diagram of the electrical principle of the trigger against single event transient effect described in Embodiment 1;

FIG. 2 is a schematic diagram of the electrical principle of the local clock management circuit described in Embodiment 4;

FIG. 3 is a schematic diagram of the electrical principle of the first pulse generating logic circuit 23 described in Embodiment 6;

Fig. 4 is a normal input signal and a waveform diagram formed on internal nodes node1 and node2 of the flip-flop according to the present invention;

Fig. 5 is the oscillogram that the SET disturbance pulse of L is formed on node node1 and node2 by the width that is captured by the flip-flop of the present invention;

Fig. 6 is the oscillogram formed on nodes node1 and node2 by the single event transient effect interference pulse not captured by the trigger of the present invention;

FIG. 7 is an output signal waveform diagram of the first pulse generating logic circuit 23 described in Embodiment 6;

FIG. 8 is a waveform diagram of an output signal of the local clock management circuit described in Embodiment 4. FIG.

detailed description

Specific Embodiments 1. This specific embodiment is described in conjunction with FIG. 1 . The flip-flop against single event transient effect described in this embodiment includes a first inverter 1 , a second inverter 2 , and a third inverter 3 , the fourth inverter 4, the fifth inverter 5, the exclusive OR gate xor1, the exclusive OR gate xor2, the NAND gate 6, the first pulse latch 7, the second pulse latch 8, and the third pulse latch register 9 and the fourth pulse latch 10,

The initial signal D is sent to the XOR gate xor1 and the first inverter 1 at the same time, and the initial signal D is sent to the third pulse latch 9 after being inverted by the first inverter 1, and the output of the third pulse latch 9 The signal is sent to the exclusive OR gate xor1 and the second inverter 2 at the same time, and the output signal P of the exclusive OR gate xor1 is inverted by the third inverter 3 and sent to the first pulse latch 7 and the second pulse latch at the same time 8, the output signal of the first pulse latch 7 and the output signal of the second pulse latch 8 are sent to the NAND gate 6, and the output signal check of the NAND gate 6 is inverted by the fourth inverter 4 sent to the XOR gate xor2, the output signal of the third pulse latch 9 is sent to the fourth pulse latch 10 after being inverted by the second inverter 2, and the output signal of the fourth pulse latch 10 is passed through the fifth The inverter 5 inverts and sends to the exclusive OR gate xor2, the output signal Q of the exclusive OR gate xor2 is the output signal of the flip-flop that resists the single event transient effect.

Embodiment 2. This embodiment is described in conjunction with FIG. 1. The difference between this embodiment and the flip-flop against single event transient effect described in Embodiment 1 is that the first pulse latch 7, the third pulse The circuit structure of the latch 9 and the fourth pulse latch 10 is the same, and the first pulse latch 7 includes a first CMOS transmission gate 11, a second CMOS transmission gate 12, a sixth inverter 13 and a seventh Inverter 14,

The signal input terminal of the first CMOS transmission gate 11 is used as the signal input terminal of the first pulse latch 7 to receive an external input signal, and the second CMOS transmission gate 12, the sixth inverter 13 and the seventh inverter 14 are sequentially connected to form Closed loop, the signal input terminal of the second CMOS transmission gate 12 receives the output signal of the first CMOS transmission gate 11 as the signal input terminal of the closed loop loop, and the signal output terminal of the sixth inverter 13 is used as the signal of the closed loop loop output terminal, and the output signal of the closed-loop loop is sent to the NAND gate 6, and the clock signal clk_g1 and the clock signal clk_g1_n are both sent to the clock signal input terminals of the first CMOS transmission gate 11 and the second CMOS transmission gate 12 for detecting The transparent level control of the first pulse latch 7 is sampled, and the clock signal clk_g1 and the clock signal clk_g1_n are inverted, that is, clk_g1=˜clk_g1_n.

Embodiment 3. This embodiment is described in conjunction with FIG. 1. The difference between this embodiment and the flip-flop against single event transient effect described in Embodiment 1 is that the second pulse latch 8 includes a third CMOS Transmission gate 15, fourth CMOS transmission gate 16, eighth inverter 17 and first NOR gate 18,

The signal input terminal of the third CMOS transmission gate 15 is used as the signal input terminal of the second pulse latch 8 to receive an external input signal, and the fourth CMOS transmission gate 16, the eighth inverter 17 and the first NOR gate 18 are sequentially connected to form Closed loop, the signal input end of the 4th CMOS transmission gate 16 receives the output signal of the 3rd CMOS transmission gate 15 as the signal input end of described closed loop loop, the signal input end of the first NOR gate 18 is as the signal of described closed loop loop output terminal, and the output signal of the closed-loop loop is sent to the NAND gate 6, and the clock signal clk_g2 and the clock signal clk_g2_n are both sent to the clock signal input terminals of the third CMOS transmission gate 15 and the fourth CMOS transmission gate 16 for detecting Sampling the transparent level control of the second pulse latch 8, and the clock signal clk_g2 and the clock signal clk_g2_n are inverted, that is, clk_g2=~clk_g2_n, the clock signal clk_re is sent to an input end of the first NOR gate 18 for A high-level reset control is provided for the second pulse latch 8 .

Specific Embodiment 4. This specific embodiment is described in conjunction with FIG. 2. The difference between this specific embodiment and the trigger against the single event transient effect described in specific embodiments 1, 2 or 3 is that it also includes a local clock management unit , the local clock management unit includes a ninth inverter 19, a second NOR gate 20, a first delay circuit 21, a second delay circuit 22, a first pulse generation logic circuit 23 and a second pulse generation logic circuit 24,

The clock signal clk is sent to the ninth inverter 19 and the first delay circuit 21 at the same time, the output signal of the clock signal clk after being inverted by the ninth inverter 19 is the clock signal clk_n, and the clock signal clk_n is sent to the second NOR gate 20. The first delay circuit 21 delays the clock signal clk and outputs the clock signal clk_1, and the clock signal clk_1 is sent to the second delay circuit 22 and the first pulse generation logic circuit 23 at the same time, and the first pulse generation logic circuit 23 generates the clock The signal clk_1 is subjected to pulse generation processing to output the clock signal clk_g1 and the clock signal clk_g1_n, the second delay circuit 22 delays the clock signal clk_1 and outputs the clock signal clk_2, and the clock signal clk_2 is simultaneously sent to the second NOR gate 20 and the second The pulse generation logic circuit 24, the second pulse generation logic circuit 24 performs pulse generation processing on the clock signal clk_2 to output the clock signal clk_g2 and the clock signal clk_g2_n, and the clock signal clk_n and the clock signal clk_2 are calculated by the second NOR gate 20 to output the clock signal clk_re, namely clk_re=clk_n⊕clk-2.

In this embodiment, both the first delay circuit 21 and the second delay circuit 22 are composed of inverter chains, which are used to provide clock delay, and together with the first pulse generation logic circuit 23 and the second pulse generation logic circuit 24, provide the first Different transparency levels required by pulse latch 7 , second pulse latch 8 , third pulse latch 9 and fourth pulse latch 10 .

In this embodiment, the clock signal clk and the clock signal clk_n are used to detect and sample the transparent level control of the third pulse latch 9 and the fourth pulse latch 10, and the clock signal clk and the clock signal clk_n are in a complementary relationship, namely clk=~clk_n.

Embodiment 5. This embodiment is described in conjunction with FIG. 3 . The difference between this embodiment and the flip-flop against single event transient effect described in Embodiment 4 is that the first pulse generating logic circuit 23 and the second pulse The circuit structure of the generation logic circuit 24 is the same, and the first pulse generation logic circuit 23 includes a PMOS transistor 25, an NMOS transistor 26, an AND gate 27, a tenth inverter 28 and an eleventh inverter 29,

The clock signal is sent to the AND gate 27 and the PMOS transistor 25 at the same time, the output signal of the PMOS transistor 25 is sent to the AND gate 27 and the NMOS transistor 26 at the same time, and the output signal of the AND gate 27 passes through the tenth inverter 28 and the eleventh inverter in turn The output signal of the NMOS transistor 26 is combined with the output signal of the NMOS transistor 26 after the inversion of the device 29 to output the clock signal clk_g2 and the clock signal clk_g2_n.

In this embodiment, both the first pulse generation logic circuit 23 and the second pulse generation logic circuit 24 are used to generate short pulses at the rising edge of the clock, and the short pulse width is determined by the AND gate 27 and the inverter chain, which can be appropriately increased or decreased The number of inverters is small to adjust the size of the short pulse width, and the waveform diagram of the output signal is shown in Figure 7.

As shown in Figure 4, it is a normal input signal and the waveform diagram formed on the internal nodes node1 and node2 of the flip-flop of the present invention, and Fig. 5 is a SET interference pulse whose width is L captured by the flip-flop of the present invention at the node Waveform diagram formed on node1 and node2. The two dotted lines in Fig. 4 and Fig. 5 respectively represent the sampling time points of the first pulse latch 7 and the second pulse latch 8, taking the rising edge of the clock as a reference, the first sampling time is t1, and the second sampling time The time is t2, requirements: t1-t2≥L and t1≥L; the output signal P represents the signal generated by the initial signal D and the signal on the node node1 via the XOR gate xor1, then at the two sampling points in Figure 3, the initial The logic levels of the signal D and the signal on the node node1 are 11 and 11 respectively, then P1=P2=0, indicating that the received signal is normal. In Figure 5, the logic levels of the initial signal D and the signal on the node node1 are 01 respectively , 01, then P1=P2=1, which means receiving the interference pulse signal.

When the input signal receives single-event transient pulse interference, but is not captured by the trigger at the clock edge, take the waveform in Figure 6 as an example, at this time, the logic levels of the initial signal D and the signal on node node1 are 10, 00 respectively , then P1=1, P2=0, similarly, when P1=0, P2=1, it also means that there is an interference pulse signal, but it is not captured by the trigger, so no soft error is caused.

Therefore, when P1=1 and P2=1, with check=P1&P2, you can use check to determine whether there is a single-event transient interference pulse and it is captured by the trigger, and then output the correct state through the XOR logic relationship.

FIG. 8 is a waveform diagram of each output signal in the local clock management circuit. The local clock management circuit serves as a shared unit to provide various global and semi-global signals required by the digital integrated circuit system and the flip-flop described in the present invention.

Wherein, clk_re provides high-level reset control for the second pulse latch 8, thereby providing periodic reset for the single event transient effect judgment signal check, to weaken the next single event transient effect after occurrence and judgment of a single event transient effect event A glitch caused by a check signal recovery delay when a clock cycle receives a normal signal.

In order to ensure the normal function of the flip-flop involved in the present invention, the pollution delay Tcd under the applied logic path needs to satisfy: Tcd>t2+t_pulse, wherein t_pulse is a short pulse width.

Claims (5)

1. the triggering device of anti-single particle transient state effect, it is characterized in that, it comprises the first phase inverter (1), the 2nd phase inverter (2), the 3rd phase inverter (3), the 4th phase inverter (4), the 5th phase inverter (5), the first different or door (xor1), the 2nd different or door (xor2), Sheffer stroke gate (6), the first pulse latches (7), the 2nd pulse latches (8), the 3rd pulse latches (9) and the 4th pulse latches (10)

Initialize signal D is sent to the first different or door (xor1) and the first phase inverter (1) simultaneously, initialize signal D is sent to the 3rd pulse latches (9) after the first phase inverter (1) is anti-phase, the output signal of the 3rd pulse latches (9) is sent to the first different or door (xor1) and the 2nd phase inverter (2) simultaneously, first output signal P that is different or door (xor1) is sent to the first pulse latches (7) and the 2nd pulse latches (8) after the 3rd phase inverter (3) is anti-phase simultaneously, the output signal of the first pulse latches (7) and the output signal of the 2nd pulse latches (8) are all sent to Sheffer stroke gate (6), the output signal check of Sheffer stroke gate (6) is sent to the 2nd different or door (xor2) after the 4th phase inverter (4) is anti-phase, the output signal of the 3rd pulse latches (9) is sent to the 4th pulse latches (10) after the 2nd phase inverter (2) is anti-phase, the output signal of the 4th pulse latches (10) is sent to the 2nd different or door (xor2) after the 5th phase inverter (5) is anti-phase, 2nd output signal Q that is different or door (xor2) is the output signal of the triggering device of anti-single particle transient state effect.

2. the triggering device of anti-single particle transient state effect according to claim 1, it is characterized in that, first pulse latches (7), the 3rd pulse latches (9) are identical with the circuit structure of the 4th pulse latches (10), described first pulse latches (7) comprises the first cmos transmission gate (11), the 2nd cmos transmission gate (12), hex inverter (13) and the 7th phase inverter (14)

The signal input terminus of the first cmos transmission gate (11) receives external input signal as the signal input terminus of the first pulse latches (7), 2nd cmos transmission gate (12), hex inverter (13) and the 7th phase inverter (14) connect and compose closed loop successively, the signal input terminus of the 2nd cmos transmission gate (12) receives the output signal of the first cmos transmission gate (11) as the signal input terminus of described closed loop, the signal output terminal of hex inverter (13) is as the signal output terminal of described closed loop, and the output signal of described closed loop is sent to Sheffer stroke gate (6), clocksignal clk_g1 and clocksignal clk_g1_n is all sent to the first cmos transmission gate (11) and the clock signal input terminal of the 2nd cmos transmission gate (12), for detecting the transparent Automatic level control of sampling the first pulse latches (7), and clocksignal clk_g1 and clocksignal clk_g1_n is anti-phase, i.e. clk_g1=��clk_g1_n.

3. the triggering device of anti-single particle transient state effect according to claim 1, it is characterized in that, 2nd pulse latches (8) comprises the 3rd cmos transmission gate (15), the 4th cmos transmission gate (16), the 8th phase inverter (17) and the first rejection gate (18)

The signal input terminus of the 3rd cmos transmission gate (15) receives external input signal as the signal input terminus of the 2nd pulse latches (8), 4th cmos transmission gate (16), 8th phase inverter (17) and the first rejection gate (18) connect and compose closed loop successively, the signal input terminus of the 4th cmos transmission gate (16) is as the output signal of signal input terminus reception the 3rd cmos transmission gate (15) of described closed loop, the signal input terminus of the first rejection gate (18) is as the signal output terminal of described closed loop, and the output signal of described closed loop is sent to Sheffer stroke gate (6), clocksignal clk_g2 and clocksignal clk_g2_n is all sent to the 3rd cmos transmission gate (15) and the clock signal input terminal of the 4th cmos transmission gate (16), for detecting the transparent Automatic level control of sampling the 2nd pulse latches (8), and clocksignal clk_g2 and clocksignal clk_g2_n is anti-phase, i.e. clk_g2=��clk_g2_n, clocksignal clk_re is sent to an input terminus of the first rejection gate (18), for controlling for the 2nd pulse latches (8) provides high level to reset.

4. the triggering device of anti-single particle transient state effect according to claim 1, it is characterized in that, it also comprises local clock Administrative Unit, described local clock Administrative Unit comprises the 9th phase inverter (19), the 2nd rejection gate (20), the first delay circuit (21), the 2nd delay circuit (22), the first pulse generate logical circuit (23) and the 2nd pulse generate logical circuit (24)

Clocksignal clk is sent to the 9th phase inverter (19) and the first delay circuit (21) simultaneously, the output signal of clocksignal clk after the 9th phase inverter (19) is anti-phase is clocksignal clk_n, clocksignal clk_n is sent to the 2nd rejection gate (20), clocksignal clk is carried out clock signal clk_1 after delay process by the first delay circuit (21), clocksignal clk_1 is sent to the 2nd delay circuit (22) and the first pulse generate logical circuit (23) simultaneously, clocksignal clk_1 is carried out the rear clock signal clk_g1 and clocksignal clk_g1_n of pulse generate process by the first pulse generate logical circuit (23), clocksignal clk_1 is carried out clock signal clk_2 after delay process by the 2nd delay circuit (22), clocksignal clk_2 is sent to the 2nd rejection gate (20) and the 2nd pulse generate logical circuit (24) simultaneously, clocksignal clk_2 is carried out the rear clock signal clk_g2 and clocksignal clk_g2_n of pulse generate process by the 2nd pulse generate logical circuit (24), clocksignal clk_n and clocksignal clk_2 is clock signal clk_re after the 2nd rejection gate (20) calculates, i.e. clk_re=clk_n clk_2.

5. the triggering device of anti-single particle transient state effect according to claim 4, it is characterized in that, first pulse generate logical circuit (23) is identical with the circuit structure of the 2nd pulse generate logical circuit (24), described first pulse generate logical circuit (23) comprises PMOS (25), NMOS tube (26) and door (27), the tenth phase inverter (28) and the 11 phase inverter (29)

Clocksignal is sent to and door (27) and PMOS (25) simultaneously, the output signal of PMOS (25) is sent to and door (27) and NMOS tube (26) simultaneously, with the output signal of door (27) successively through the tenth phase inverter (28) and the 11 phase inverter (29) anti-phase after converge and clock signal clk_g2 and clocksignal clk_g2_n with the output signal of NMOS tube (26).