UMCD-2007-0472 26667twf.doc/p 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體結構的製造方法以及靜態 隨機存取記憶體，且特別是有關於一種具有高介電常數; 電層的靜態隨機存取記憶體，以及具有高介電常數介電層 之半導體結構的製造方法。 a 【先前技術】 傳統半導體製程中，大多是使用氧化石夕(Si〇2)為閘介 電層，但隨著積體電路產業的快速發展，為了提高元件之 積集度(Integrity)並增加其驅動能力’必須將整個電路元件 大小的設計往尺寸縮小的方向前進。當閘極之線寬設計縮 短時，而閘介電層的厚度也必須隨之變薄，如此會造成直 接穿隨(direct tunneling)機率的增加，進而引起閘極漏電流 (leakage current)急遽的增加 0 為解決此問題，具有高介電常數(high-k)之介電層，成 了眾所矚目的閘介電層材料。但是，目前要將高介電常數 介電層整合入電晶體，仍然遭遇到一些技術性的困難。因 為，尚介電常數材料的使用會降低遷移率及元件可靠度。 另外，隨著閘介電層之厚度的變薄，硼原子穿隧(B penetration)與多晶矽閘極空乏(p〇ly depieti〇n)的現象更加 嚴重。其中，硼原子穿隧可藉由摻雜少量氮於氧化層中予 以緩=，但多晶矽閘極空乏的影響卻難以避免。再加上， 由於面介電常數介電層的使用會使元件的臨界電壓增加， 而使高介電常數介電層無法與多晶石夕閘極整合在一起。因 1364799 UMCD-2007-0472 26667twf.doc/p 此，有人提出以金屬閘極(metal gate)取代多晶矽的作法， 除了可以免除多晶矽閘極空乏外，亦可降低閘極寄生電阻。 然而，以-般具有高介電常數介電層與金屬開極的閉 極結構來說’目前習知的作法，是先在高介電常數介電層 上形成虛擬多糾閘極之後，才移除這—層虛擬多晶石夕間 極，然後才形成金屬閘極，這使得高介電常數介電層在移 除虛擬多晶矽閘極的過程之中，會受到損傷，而降低其原 有的南電阻性質。 ' 此外，這些具有高介電常數介電層的元件會於晶片上 其他元件的製程互相整合，還會使得各元件出現不同的問 題，例如，先形成的高介電常數介電層與金屬閘極，會遭 遇多次的高溫熱製程(high temperature thermal process)，而 改變膜層原有的性質，例如，削弱高介電常數介電層與金 屬閘極之間的界面品質，尤其是在p型電晶體之中，很容 易導致電晶體發生啟始電壓滾降(r〇u_〇ff)的情形，影響元 件的穩定度。或者是在靜態隨機存取記憶體的pN接面中， 額外製造出-層高介電常數介電層，大大地降低了靜態隨 機存取記憶體的效能。 〜 【發明内容】 有鑑於此，本發明的目的就是在提供一種半導體結構 的製造方法，在移除虛擬閘極之後，才形成高介電常數介 電層進而避免南溫熱製程造成膜層的品質下降。 ，發明的另一目的是提供一種靜態隨機存取記憶體， 不但能夠保有高介電常數介電層的優點，且不會於PN接 1364799 UMCD-2007-0472 26667twf.doc/p 面間額外設置有這一層高介電常數介電層。 本發明提出-種半導體結構的方法，先提供—芙 底，基底上已職有H晶軸 1 第-電晶體包括一第一虛擬間極，第二電晶：包:」、中二 =閘:著且C體與第二電晶體為不同導電型之電 =成第第m讀第二虛擬閘極而分 成-介電層、-高介電第常二然彳 ==形 層’至少填入第一開口與第二開二、且 a咕 中形成—第一型導體層盥一第-低雷卩日iC驷 層，第二低電阻導體層填滿第、。帛-低電阻導體 法，實:ΐ例中，上述之半導體結構的製造方 阻器包括—上番纟 冋件包括一閘極，電 橫跨基底中之一存層， 雜區。 丨同離結構與一第二型按 法，上述之半導體結構的製造方 併移除蘭極與導體層二？玉與第一虛擬閘極的同時，一 第二型導體層與第 8 UMCD-2007-0472 26667twf.doc/p 一低電阻導體層於形成的步驟中，同時填入原本形成有閘 極與導體層的位置。 在本發明之一實施例中，上述之半導體結構的製造方 法，其中於移除第一開口中之第一低電阻導體層與第二型 導體層的步驟中，一併移除靜態隨機存取記憶體中，第一 型摻雜區上方這一側之第一低電阻導體層與第二型導體 層’形成一第三開口。 在本發明之一實施例中，上述之半導體結構的製造方 法，其中第一型導體層與第二低電阻導體層於其形成步驟 中，一併填入第三開口中，且第二低電阻導體層填滿第三 開口。 在本發明之一實施例中，上述之半導體結構的製造方 法，其中移除第一虛擬閘極與第二虛擬閘極的方法包括一 濕式餘刻法或一乾式钱刻法。 在本發明之一實施例中，上述之半導體結構的製造方 法，其中濕式#刻法包括使用氫氧化銨或氫氧化四曱基銨。 在本發明之一實施例中，上述之半導體結構的製造方 法，其中第一電晶體為p型電晶體，第二電晶體為N型電 晶體。 在本發明之一實施例中，上述之半導體結構的製造方 法，其中第一型導體層為P型金屬層，第二型導體層為N 型金屬層。 在本發明之一實施例中，上述之半導體結構的製造方 法，其中移除第一開口中之第一低電阻導體層與第二型導 UMCD-2007-0472 26667twf.doc/p 體層的方法包括先於基底上形成一圖案化光阻居，至* 露出第一開口上方之第一低電阻導體層上^面， 以一乾式蝕刻法或一濕式蝕刻法至少移除第一開口 —唆 一低電阻導體層與第二型導體層。 幵 ^第 在本發明之-實施例中，上述之半導體結構的 法，其中濕式姓刻法包括使用含氫氧化錢、過氧化 酸或氫氯酸的去離子水。 在本發明之-實施例中，上述之半導體結構的製 法’更包括於移除第-虛朗極與第二虛擬閘極，方 進行以下步驟：於基底上形成—轉層，覆蓋住第—督先 體與第二電晶體。然後於基底上形成—層間介電層，^ 填滿第-導電型電晶體與第二導電型電晶體之間二少 接著移除部分|幕層直到暴露出第—虛擬閘極、。 閘極。 ’、處_ 本發明另提出-種靜態隨機存取記憶體，包括 層間介電層、高介電常數介電層、第一低電阻導體二:给 二型導體層、第-型導體層與第二低電阻導體層。：第 基底中設置有-第-型摻雜區、 結構’且第-型摻雜區與第二型摻雜區以隔離結3 隔。層間介電層設置於基紅，層間介電層中具有一開目^ 橫跨第-麵、隔離結顯第二麟_， + 基底。高介電錄介電層設置於開口巾，沿賴口内^ P幵1 口底部而設置。第-低電阻導體層設 區 與部分隔離結構上，填人開口中。第二型導體層設置= UMCD-2007-0472 26667twf.doc/p -低電阻導體層與高介電常數介電層u 設置於高介電常數介電層上，沿著開電阻i 2裸^的侧壁與高介電f數介電層裸露出之上表面而 =置°第二低電阻導體層則設置於第1導體層上 開口。 穴 體’ itr月=實施例中，上述之靜態隨機存取記憶 體’更包括-介電層，設置於高介電常數 間、南介電常數介電層與層間介電層之間。1、土- 體，U轭例中’上述之靜態隨機存取記憶 L雜:鶴區為⑼換雜區，第二型捧雜區為n 體，JL中^月實㈣中’上述之靜態隨機存取記憶 L屬:型導體層為?型金屬層，第二型導卿 體，ΐίΐ 屬中:上述之靜態隨機存取記憶 或釕。&金屬層的材質包括鶴、氮化鶴^、氮化鈦 體，其中中’^述之靜態隨機存取記憶 如、氮化叙ΐ 質包括氮化紐、氮化石夕组、碳化 —=銘欽合金、銘化欽或銘。 體，盆中Μ ^實施例中’上述之靜態隨機存取記情 氮切氮^數介電層的材質包括氧化纽 '欽酸^貝 給、氮氧切、氧錄、氧切 乳化錯氧化石夕錯、氧化給錯、氧化鈦、 1364799 UMCD-2007-0472 26667twf,doc/p 氧化鈽、氧倾' A化賴或氧化銘。 才彻製程步驟的調整，在移除虛朗極之後， = = 介電層，因而可以避免膜層受到損傷， 棱升同"-电㊉數介電層與第一型導體層、第二型導體异 ^間的界面品質。此外，靜態隨機存取記憶體的PN接i 間，也不會形成額外的高介電常數介電層。UMCD-2007-0472 26667twf.doc/p IX. Description of the Invention: [Technical Field] The present invention relates to a method of fabricating a semiconductor structure and a static random access memory, and more particularly to a high dielectric Electrical constant; static random access memory of an electrical layer; and method of fabricating a semiconductor structure having a high dielectric constant dielectric layer. a [Prior Art] In the traditional semiconductor process, most of the use of oxidized stone (Si〇2) as the gate dielectric layer, but with the rapid development of the integrated circuit industry, in order to improve the integration of components (Integrity) and increase Its drive capability 'must advance the design of the entire circuit component size in the direction of size reduction. When the gate width design of the gate is shortened, the thickness of the gate dielectric layer must also be thinned accordingly, which will increase the probability of direct tunneling, which in turn causes the leakage current of the gate to be imminent. Adding 0 To solve this problem, a dielectric layer with a high dielectric constant (high-k) has become a well-known gate dielectric material. However, there are still some technical difficulties in integrating a high dielectric constant dielectric layer into a transistor. Because the use of dielectric constant materials reduces mobility and component reliability. In addition, as the thickness of the gate dielectric layer becomes thinner, the phenomenon of B atom tunneling and polycrystalline germanium gate depletion is more serious. Among them, boron atom tunneling can be retarded by doping a small amount of nitrogen in the oxide layer, but the effect of polycrystalline germanium gate depletion is difficult to avoid. In addition, the use of a dielectric constant dielectric layer increases the critical voltage of the device, so that the high-k dielectric layer cannot be integrated with the polycrystalline silicon gate. Since 1364799 UMCD-2007-0472 26667twf.doc/p, it has been proposed to replace the polysilicon with a metal gate, in addition to eliminating the polysilicon gate depletion and reducing the parasitic resistance of the gate. However, in the case of a closed-cell structure having a high-k dielectric layer and a metal open-pole, it is a conventional practice to form a virtual multi-quenching gate on a high-k dielectric layer. Removing this layer of virtual polycrystalline slab poles, and then forming a metal gate, which causes the high-k dielectric layer to be damaged during the process of removing the virtual polysilicon gate, reducing its original The nature of the south resistor. In addition, these components with a high-k dielectric layer will integrate with each other on the other components of the wafer, and will cause different problems for each component, for example, a high-k dielectric layer and a metal gate that are formed first. Extremely, it will encounter many high temperature thermal processes, and change the original properties of the film, for example, weaken the interface quality between the high-k dielectric layer and the metal gate, especially in Among the p-type transistors, it is easy to cause the transistor to start rolling off (r〇u_〇ff), which affects the stability of the element. Alternatively, in the pN junction of the SRAM, an extra-layer high-k dielectric layer is additionally fabricated, which greatly reduces the performance of the static random access memory. SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a method for fabricating a semiconductor structure, in which a high-k dielectric layer is formed after removing a dummy gate, thereby avoiding a film formation caused by a south-temperature heat process. The quality is declining. Another object of the invention is to provide a static random access memory that not only retains the advantages of a high-k dielectric layer, but also does not set an additional PN connection 1364799 UMCD-2007-0472 26667 twf.doc/p There is this layer of high dielectric constant dielectric. The invention proposes a method for semiconductor structure, which first provides a Fu-bottom, the substrate has a H-axis 1 and the first transistor has a first dummy interpole, and the second transistor: package: ", middle two = gate : The C body and the second transistor are of different conductivity type = the mth read the second virtual gate and is divided into a dielectric layer, - a high dielectric first normal 彳 == a layer 'at least The first opening and the second opening are formed in the second opening, and the first type conductor layer is a first-low Thunder day iC layer, and the second low resistance conductor layer is filled with the first.帛-low-resistance conductor method, in the example, the above-mentioned manufacturing structure of the semiconductor structure includes a gate, a gate, and a memory layer across the substrate. The same structure and a second type of method, the above-mentioned semiconductor structure is manufactured and the blue and conductor layers are removed. Simultaneously with the first virtual gate, a second type of conductor layer and a low-resistance conductor layer of the eighth UMCD-2007-0472 26667 twf.doc/p are formed in the step of forming the gate and the conductor at the same time. The location of the layer. In an embodiment of the invention, the method for fabricating a semiconductor structure, wherein the step of removing the first low-resistance conductor layer and the second-type conductor layer in the first opening simultaneously removes static random access In the memory, the first low resistance conductor layer on the side above the first type doping region and the second type conductor layer ' form a third opening. In an embodiment of the invention, the method for fabricating a semiconductor structure, wherein the first type conductor layer and the second low resistance conductor layer are simultaneously filled in the third opening in the forming step, and the second low resistance The conductor layer fills the third opening. In an embodiment of the invention, the method of fabricating the semiconductor structure described above, wherein the method of removing the first dummy gate and the second dummy gate comprises a wet remnant method or a dry capital engraving method. In an embodiment of the invention, the method of fabricating the above semiconductor structure, wherein the wet etching comprises using ammonium hydroxide or tetradecyl ammonium hydroxide. In an embodiment of the invention, the method of fabricating the semiconductor structure described above, wherein the first transistor is a p-type transistor and the second transistor is an N-type transistor. In an embodiment of the invention, the method of fabricating the semiconductor structure described above, wherein the first type conductor layer is a P type metal layer, and the second type conductor layer is an N type metal layer. In an embodiment of the invention, the method for fabricating a semiconductor structure, wherein the method of removing the first low resistance conductor layer and the second type of UMCD-2007-0472 26667 twf.doc/p body layer in the first opening comprises Forming a patterned photo-resistance on the substrate to expose the first low-resistance conductor layer above the first opening, and removing at least the first opening by a dry etching method or a wet etching method. a low resistance conductor layer and a second type conductor layer. In the embodiment of the invention, the above-described method of semiconductor structure, wherein the wet type method comprises using deionized water containing hydrogen peroxide, peroxyacid or hydrochloric acid. In the embodiment of the present invention, the method for fabricating the semiconductor structure described above further includes removing the first-virtual pole and the second dummy gate, and performing the following steps: forming a layer on the substrate to cover the first layer. Supervise the precursor and the second transistor. Then, an interlayer dielectric layer is formed on the substrate, and between the first conductive type transistor and the second conductive type transistor, two portions are removed, and then the portion of the layer is removed until the first dummy gate is exposed. Gate. The present invention further proposes a static random access memory, comprising an interlayer dielectric layer, a high-k dielectric layer, and a first low-resistance conductor 2: a second-type conductor layer, a first-type conductor layer and The second low resistance conductor layer. The first substrate is provided with a --type doped region, a structure, and the first-type doped region and the second-type doped region are separated by an isolation junction 3. The interlayer dielectric layer is disposed on the base red, and the interlayer dielectric layer has an opening layer traversing the first surface, and the isolation layer exhibits the second lining, the + substrate. The high dielectric recording dielectric layer is disposed on the opening towel and is disposed along the bottom of the opening. The first low-resistance conductor layer and the partial isolation structure are filled in the opening. The second type conductor layer is set = UMCD-2007-0472 26667twf.doc/p - the low-resistance conductor layer and the high-k dielectric layer u are disposed on the high-k dielectric layer, along the open resistance i 2 bare^ The sidewall and the high dielectric f dielectric layer are exposed to the upper surface and the second low resistance conductor layer is disposed on the first conductor layer. In the embodiment, the above-described static random access memory ’ further includes a dielectric layer disposed between the high dielectric constant, the south dielectric constant dielectric layer and the interlayer dielectric layer. 1. Soil-body, U-yoke example 'The above-mentioned static random access memory L is: the crane area is (9) change zone, the second type is mixed zone n body, JL middle ^ month real (four) in the above static Random access memory L is: the type of conductor layer is a metal layer, the second type of guide body, ΐίΐ genus: the above static random access memory or 钌. The material of the metal layer includes the crane, the nitrided iron, and the titanium nitride body. Among them, the static random access memory such as nitriding, including nitriding, nitriding, carbonization-= Ming Qin alloy, Ming Hua Qin or Ming. Body, basin Μ ^ In the example, the above-mentioned static random access sensible nitrogen nitrite dielectric layer material includes oxidized nucleate, nitrous oxide, oxygen recording, oxygen emulsification and wrong oxidization Shi Xi wrong, oxidation error, titanium oxide, 1364799 UMCD-2007-0472 26667twf, doc / p yttrium oxide, oxygen tilt 'A chemical or oxidized Ming. Only after the adjustment of the process steps, after the removal of the sinus pole, = = dielectric layer, thus avoiding damage to the film layer, the edge is the same as the "electrical dielectric layer and the first type of conductor layer, the second The interface quality between the types of conductors. In addition, an additional high-k dielectric layer is not formed between the PN junctions of the SRAM.
為讓本發明之上述和其他目的、雜和優點能更明顯 ’下文特舉較佳實施例，並配合所附圖式，細說 明如下。 【實施方式】The above and other objects, advantages and advantages of the present invention will become more apparent <RTIgt; [Embodiment]
_圖1A-1至圖if-ι是繪示本發明一實施例之一種半導 體結構的製造流程剖面圖。圖1A_2至圖1F_2是對應於圖 1A-1至圖1F_i的步驟，繪示本發明一實施例之一種靜態 隨機存取記憶體之製造流程剖面圖。 凊參照圖1A-1，本發明提出一種半導體結構的製造流 私圖，先提供基底1〇〇，基底丨⑻例如是石夕基底絕緣層 上矽基底或是三五族半導體基底、二六族半導體基底。基 底100上已形成有第一電晶體110、第二電晶體120、高壓 元件130與電阻器14〇，這些元件例如是以隔離結構1〇5 而刀隔。隔離結構1〇5例如是淺溝渠隔離結構，如圖iA-i 所不’或是場氧化層等其他類型的隔離結構。 第一電晶體110由基底1〇〇起具有一層閘介電層H1 與虛擬閘極113，虛擬閘極113兩側為間隙壁117,虛擬閘 極113下方兩側之基底1〇〇中則設置有第一型源極/汲極區 12 UMCD-2007-0472 26667twfdoc/p 電層111的材質例如是氧切，虛擬閘極113 的材質例如是多晶石夕、摻雜多晶 = 層硬罩幕層115，如魏鶴、雜鋅、』 =夕化鈦等魏金屬層。虛擬_ u 中則設置有第一型源極/汲極119。 兩”之土底 第二電晶體120之結構與第 閘介電層⑵、虛擬閘極123、間隙壁 129。虛擬閘極123上方也可以設置有硬罩幕 祕t型源極/汲極119例如是摻雜了删、阳或銦之Ρ 斜二、：型摻雜區’第一電晶體110即為ρ型電晶體， =肪’第二型雜/祕129例如是摻雜有-、碎等Ν 型摻型源極/沒極，第二電晶體12〇_型電晶體。 问壓元件13G與第-電晶體UG、第二電晶體12〇的 、u冓相去不遠，同樣具有閘介電層⑶、虛擬臟133、間 隙土 137與源極/汲極丨39。其中，虛擬閘極133上方可以 是設置有硬罩幕層135。 至於電容器140由基底1〇〇起則具有電容絕緣層141 與上電極143。上電極143上方還可以設置有硬罩幕層 145。上電極m3兩側壁可以形成有間隙壁My。 在一實施例中’上述第一電晶體u〇、第二電晶體 12〇、高壓元件130與電阻器14〇例如是利用同樣的步驟一 起形成的。閘介電層1U、121、131與電容絕緣層141例 UMCD-2007-0472 26667twf.doc7p 如是相同的材質，而虛擬閘極113、123、133與上電極143 例如是相同的材質。 請參照圖1A-2,在一實施例中，基底1〇〇上除了已經 形成的第一電晶體110、第二電晶體120、高壓元件13〇 與電阻器140之外，在基底丨〇〇上，更可以形成有靜態隨 機存取記憶體170，此靜態隨機存取記憶體170例如是橫 跨基底100中之第一型摻雜區107、隔離結構105與第二 型摻雜區109。在一實施例中，第一型摻雜區1〇7例如是 摻雜了硼、BF2或銦之P型摻質的p型摻雜區，而第二型 摻雜區109則為摻雜有罐或神等n型摻質之n型摻雜區。 在此區域上之靜態隨機存取記憶體17〇由基底1〇〇起例如 依序是一層底介電層171、一層導體層173與一層硬罩幕 層175’導體層173兩侧則形成有間隙壁177。這些膜層例 如是與前述第-電晶體11G、第二電晶體12G、高壓^件 130與電阻器14〇應用相同的多個步驟 請參考上述問介電“丨、虛擬問極113、$ 3質 與間隙壁117之說明。 更皁桊滑115 -居請參關1A_1與圖1A』，在基底⑽上形成 上曰罩幕層151，覆蓋住第一電晶體11〇、第二 電阻器14〇與靜態隨機存取記憶二〇。罩 ?曰151的材質例如是氧化矽、氮化矽、氮氧化矽 其形成方法例如是化學氣相沈積法-。释 1364799 UMCD-2007-0472 26667twf.doc/p 上形成一層層間介電層153 ,並以罩幕層151為蝕刻終止 2，平坦化層間介電層153。層間介電層153的材質例如 疋氧化石夕、碟矽玻璃、硼磷矽玻璃或其他適合之介電材料， 其形成方法例如是化學氣相沈積法。平坦化層間介電層 153的方法例如是化學機械研磨法(CMp)。 繼而，請參照圖1B_1與圖ib_2，利用適當方法，如 回蝕刻法來移除部分層間介電層153、罩幕層151與硬罩 幕層115、125、135、145、175，而裸露出虛擬閘極113、 123、133、上電極143與導體層m。之後，移除裸露出 ，的虛擬閘極113、123、133與導體層173及其下方之閘 介電層111、121、131與底介電層171，形成開口 181、183、 185、187 ’並留下上電極143與電容絕緣層141。移除這 些膜層的方法例如是先在基底100上塗布一層正光阻，然 後以曝光顯影的方式，在基底獅上形成一層圖案化光阻 層15 4，覆蓋住電阻@ j 4 〇。然後利用乾式侧法或濕式钱 刻法移除裸露出來的虛擬閘極113、123、133與導體層 17 3。上述乾式蝕刻法例如是反應性離子蝕刻法，而濕式^ 刻法則可以使用氫氧化銨(ΝΗβΗ)或氫氧化四曱美 (TMAH)等的蝕刻液。 甲基知 再來，請參照圖1C-1與圖1C-2,移除圖案化光阻層 154，然後在基底1〇〇上依序形成一層介電層155 ^ 常數介電層-157、第二型導體層⑹與低電阻導體片 ST/、183、185、187之中，且低電阻導“⑹ 填涡别述多個開口。 15 1364799 UMCD-2007-0472 26667twf.doc/p 其中’介電層155⑽質例如是氧化梦，其行程方法 例如是化學氣相沈積法。高介電常數介電層157的材質例 ，是氧化组、鈦酸、氮化，、氮氧㈣、碳化石夕、碳 乳化石夕、氧化給、氧化石夕給（懸χ〇χ)、氮氧化石夕給 (謹）、氧化n(Z]：cg、氧切錯卿為）、氧化給結 (HfZrx〇y)、氧化鈦、氧化鈽、氧化鋼、氧化關、氧化紹， ，形成方法例如是化學氣㈣射或麟法㈣_細)。 弟二型導體層161的材質例如是功函數(work functi0_ 於4.0〜4.2eV之間的N型金屬，如氮化组氮化独碳 化姐:氮化減、綠合金、料金屬材料，其形成方法 例如是化學氣相沈積法或義法。低電阻導體層⑹的材 質例如是鎢、鋁、鋁鈦(TiA1)、磷化鈷鎢(c〇wp)等。 然後’請參照圖1D-1與圖1D_2,於低電阻導體層163 上形成-層圖案化光阻層165 (或是硬罩幕層），裸 口 181以及位於第一型源極姉119上方的低電阻 =體（請參照圖1ΙΜ)，同時裸露出第一型擦雜區 方沒半邊之低電阻導體層163 (請參照圖1D_2)。 者’移除開口 181中的低電阻導體層163與第二型導體 同時亦移除位於第一型推雜區1〇7上方這—側的 導體層163與第-型導體層⑹。移除低電阻導 . 以濕式蝕刻法來說，可以是由氫氧化録、過氧.介 I!!酸或鹽酸的去離子水配製適當比例的蝕刻液。而# 式_法射以是反應性離子酬法。 履而乾 UMCD-2007-0472 26667twf.doc/p 接下來’移除®案化光阻層165 (或是移除硬罩幕 層），然後依序形成一層第一型導體層167與另一層低恭 阻導體層169。第一型導體層167的材質例如是功函= (work function)介於4.9〜5 leV之間的p型金屬，如鶴、 =化鎮、叙(銻）、氮化鈦、釕(Ru)，其形成方法例如是化 子軋相沈積法或濺鍍法。低電阻導體層169的材質例如是 鎢、銘、I呂鈦(TiAl)、填化結鶴(c〇wp)等。 • 繼而，請參照圖1E-1與圖1E-2，進行平坦化製程， 移除層間介電層153以上的所有膜層。移除的方法例如是 化學機械研磨法’以賴介電層153為_終止層，將多 餘的低電阻導體層169、第—型導體層167、低電阻導體層 163、第二型導體層161 一併移除。 如此一來，便形成了第一型電晶體110，、第二型電晶 體120,、高壓元件130’（請參考目1E_〇與靜態隨機存取 記憶體170,（請參考圖脱）。其中，第一型電晶體ιι〇, 具有介電層155、高介電常數介電層157、第一型導體層 167低電阻導體^ 169、間隙壁117與低電阻導體層169 兩側基底_中之第—型源極級極119。第二型電晶體 12〇’則具有介電層155、高介電常數介電層157、第二型導 體層16卜低電阻導體们63、間隙壁127與低電阻導體層 163兩側基底1〇〇中之第二型源極/錄心高壓元件⑽曰, 具有介電層155、高介電常數介-電層1.57、第二型導體層 161低電阻導體層163、間隙壁137與低電阻導體層⑹ 兩側基底1〇〇中之源極/汲極139。 17 1364799 UMCD-2007-0472 26667twf.doc/p 靜態隨機存取記憶體170,則設置於基底100上，至少 由高介電常數介電層157、低電阻導體層163、第二型導體 層161、第一型導體層167與另一層低電阻導體層169所 組成。基底1〇〇上之層間介電層153中具有開口 187，此 開口 187橫跨第一型摻雜區1〇7、隔離結構1〇5與第二型 摻雜區109。而高介電常數介電層157便設置於開口 187 之中，沿著開口 187内壁與開口 187底部而設置。低電阻 導體層163則設置於第二型摻㈣1G9與部分隔離結構 1〇5_^，填入第二型摻雜區1〇9上方這半邊之開口 187中。 在一實施例中，低電阻導體層163的上表面與層間介電層 153之上表面約略等高。第二型導體層161設置於低電阻 導體層163與高介電常數介電们5?之間。至於第一型導 體層則位於第—型#雜區上方，設置於高介電常數介 電層15=上，沿著開口 187中低電阻導體層163裸露出的 側壁與冋介電常數介電層157裸露出的上表面而設置。另 一層低電阻導體層169則設置於第一型導體層167上，填 入開口 187之中。在一實施例中，低電阻導體層169的上 表面，低電阻導體層163的上表面例如是約略等高。 高介電常數介電層157與開口 187底部之基底100、 開口 187兩側之間隙壁177之間，還可以設置有一層介電 層155，提升高介電常數介電層157與基底100、間隙壁 177之間钓界面特性-。… 上第一型摻雜區1〇7、第二型摻雜區1〇9、介電層 155、问介電常數介電層157、第二型導體層⑹、低電阻 UMCD-2007-0472 26667twf.doc/p 導體層163、第一型導體層167、低電阻導體層169的材質 請參照上述製造過程中之說明，於此不贅述。 、 上述靜態隨機存取記憶體170’中，高介電常數介電層 157沿著開口 187内壁與底部而設置，並不會在第一型導 體層167與第二型導體層ι61之間（PN接面之間）設置有 多餘的高介電常數介電層’這樣-來，對於靜態隨^存取 5己憶體之彳采作效能也有助益。 u ;问；丨电吊歎；丨％層疋在移除虛擬閘極與靜 態隨機存取記憶體之導體層以後才形成的，因此，高介 t數介電層不容易受到損傷，且可避開多次的 程’而製作出膜層品質佳，具妹好高電阻特性介^ 常數介電層。Μ介電常數介電層與第-料體層或第」 ^導=之:的界面特性’也得以獲得提升，“高電: 體阿壓=件以及靜態隨機存取記憶體的電性表現。 區，若第一型源極級極119為ρ型摻雜 而後形成的第一型導體層169為p型導體声， =型=體，為P型電晶體，則高介電導= 與弟一型導體層167之間的界面品質 曰157 溫熱製程次數減少，而得以提高。如此 p型m的料電壓，進錢善電晶體的穩定度。'、 η。，、第二:二’在形成上述第-型電晶體 與靜態隨機存&（請參考圖叫) 以依序：=170 (凊參考圖1E_2)之後，還可 除層間介電層153鮮幕層丨5卜移除的方法例 1364799 UMCD-2007-0472 26667twf.d〇c/p 如疋濕式姓刻法。在一實施例中，若罩幕層15丨為底氧化 石夕層與頂氮化石夕層的雙層結構，則也可以是僅移除頂氮化 矽層，而留下底氧化矽層。然後，在基底1〇〇上形成一層 接觸窗蝕刻終止層 191 ( Contact Etching St〇p Lay=，1A-1 to if-I are cross-sectional views showing a manufacturing process of a semiconductor structure according to an embodiment of the present invention. 1A_2 to 1F-2 are cross-sectional views showing a manufacturing process of a static random access memory according to an embodiment of the present invention, corresponding to the steps of Figs. 1A-1 to 1F_i. Referring to FIG. 1A-1, the present invention provides a manufacturing flow diagram of a semiconductor structure. First, a substrate 1 is provided. The substrate 丨 (8) is, for example, a 矽 基底 base insulating layer or a tri-five semiconductor substrate, a hexa family. Semiconductor substrate. The first transistor 110, the second transistor 120, the high voltage element 130 and the resistor 14A have been formed on the substrate 100, and these elements are separated by, for example, the isolation structure 1〇5. The isolation structure 1〇5 is, for example, a shallow trench isolation structure, as shown in Fig. iA-i, or other types of isolation structures such as a field oxide layer. The first transistor 110 is lifted by the substrate 1 and has a gate dielectric layer H1 and a dummy gate 113. The virtual gate 113 has spacers 117 on both sides, and the substrate 1 is disposed on the lower sides of the dummy gate 113. There is a first source/drain region 12 UMCD-2007-0472 26667twfdoc/p The material of the electric layer 111 is, for example, oxygen cutting, and the material of the virtual gate 113 is, for example, polycrystalline, doped polycrystalline = layer hard mask Curtain layer 115, such as Weihe, hetero-zinc, 』 = Xihua titanium and other Wei metal layers. The first type source/drain 119 is provided in the virtual_u. The structure of the second transistor 120 of the two bottoms is different from the structure of the second dielectric transistor (2), the dummy gate 123, and the spacer 129. The dummy gate 123 may also be provided with a hard mask t-type source/drain 119. For example, it is doped with pentad, cation or indium. The second type: the doped region 'the first transistor 110 is a p-type transistor, and the second type 129 is doped with -, for example.碎 Ν 掺 掺 掺 / 没 , , , , , , , 第二 第二 问 问 问 问 问 问 问 问 问 问 问 问 问 问 问 问 问 问 问 问 问 问 问 问 问 问 问 问 问 问 问 问 问 问 问a gate dielectric layer (3), a dummy dirt 133, a gap soil 137, and a source/drain electrode 39. The dummy gate 133 may be provided with a hard mask layer 135. The capacitor 140 is lifted by the substrate 1 The capacitor insulating layer 141 and the upper electrode 143. The upper electrode 143 may further be provided with a hard mask layer 145. The sidewalls of the upper electrode m3 may be formed with a spacer My. In an embodiment, the first transistor u 〇 The two transistors 12A, the high voltage element 130 and the resistor 14 are formed, for example, by the same steps. The gate dielectric layers 1U, 121, 1 31 and the capacitor insulating layer 141 UMCD-2007-0472 26667 twf.doc7p are the same material, and the dummy gates 113, 123, 133 and the upper electrode 143 are, for example, the same material. Referring to FIG. 1A-2, an embodiment is shown. In addition to the first transistor 110, the second transistor 120, the high voltage component 13A and the resistor 140 that have been formed on the substrate, a static random access memory can be formed on the substrate. The body 170, the static random access memory 170 is, for example, a first type doped region 107, an isolation structure 105 and a second type doped region 109 in the substrate 100. In an embodiment, the first type doping The region 1〇7 is, for example, a p-type doping region doped with a P-type dopant of boron, BF2 or indium, and the second-type doping region 109 is an n-type doped with an n-type dopant such as a can or a god. A doped region. The SRAM 17 on this region is picked up by the substrate 1, for example, a bottom dielectric layer 171, a conductive layer 173, and a hard mask layer 175' conductor layer 173. The side is formed with a spacer 177. These layers are, for example, the aforementioned first transistor 11G, second transistor 12G, and high voltage member 130. A plurality of resistors 14〇 application refer to the same steps of the above-described dielectric asked by '|, Q virtual electrode 113, $ 3 illustrate the quality and the spacers 117. More saponin slip 115 - please refer to 1A_1 and FIG. 1A", form a top mask layer 151 on the substrate (10), covering the first transistor 11 〇, the second resistor 14 〇 and the static random access memory Hey. The material of the cover 151 is, for example, ruthenium oxide, tantalum nitride or ruthenium oxynitride. The formation method thereof is, for example, chemical vapor deposition. An interlayer dielectric layer 153 is formed on the 1364799 UMCD-2007-0472 26667twf.doc/p, and the interlayer dielectric layer 153 is planarized by using the mask layer 151 as an etch stop 2 . The material of the interlayer dielectric layer 153 is, for example, iridium oxide, rayon glass, borophosphon glass or other suitable dielectric material, and the formation method thereof is, for example, chemical vapor deposition. The method of planarizing the interlayer dielectric layer 153 is, for example, a chemical mechanical polishing method (CMp). Then, referring to FIG. 1B_1 and FIG. ib_2, a part of the interlayer dielectric layer 153, the mask layer 151 and the hard mask layer 115, 125, 135, 145, 175 are removed by a suitable method such as etch back. The dummy gates 113, 123, 133, the upper electrode 143 and the conductor layer m. Thereafter, the exposed dummy gates 113, 123, 133 and the conductor layer 173 and the gate dielectric layers 111, 121, 131 and the bottom dielectric layer 171 are removed to form openings 181, 183, 185, 187 ' The upper electrode 143 and the capacitor insulating layer 141 are left. The method of removing these layers is, for example, first coating a positive photoresist on the substrate 100, and then forming a patterned photoresist layer 14 on the base lion by exposure development to cover the resistance @ j 4 〇. The exposed dummy gates 113, 123, 133 and conductor layer 17 3 are then removed by dry side or wet etching. The dry etching method is, for example, a reactive ion etching method, and the wet etching method may use an etching solution such as ammonium hydroxide (???) or tetraammine (TMAH). Referring to FIG. 1C-1 and FIG. 1C-2, the patterned photoresist layer 154 is removed, and then a dielectric layer 155 ^ constant dielectric layer - 157 is sequentially formed on the substrate 1 、. The second type conductor layer (6) and the low resistance conductor piece ST/, 183, 185, 187, and the low resistance conductance "(6) fill the vortex to describe a plurality of openings. 15 1364799 UMCD-2007-0472 26667twf.doc/p where ' The dielectric layer 155 (10) is, for example, an oxidized dream, and the stroke method is, for example, a chemical vapor deposition method. Examples of the material of the high-k dielectric layer 157 are an oxidation group, a titanic acid, a nitride, a nitrogen oxide (tetra), and a carbon fossil. Xi, carbon emulsified stone eve, oxidation, oxidized stone eve (hanging), nitrogen oxynitride eve (satisfaction), oxidation n (Z]: cg, oxygen cut into the), oxidation to the knot (HfZrx 〇 y), titanium oxide, cerium oxide, oxidized steel, oxidized off, oxidized, and formed by, for example, chemical gas (four) shot or lining method (four) _ fine. The material of the second type conductor layer 161 is, for example, a work function (work) Functi0_ N-type metal between 4.0~4.2eV, such as nitrided nitrification, carbonization, nitridation, green alloy, metal material, its formation method Chemical vapor deposition method or method. The material of the low-resistance conductor layer (6) is, for example, tungsten, aluminum, aluminum-titanium (TiA1), cobalt-phosphorus tungsten (c〇wp), etc. Then, please refer to FIG. 1D-1 and FIG. A layer-patterned photoresist layer 165 (or a hard mask layer) is formed on the low-resistance conductor layer 163, and the bare port 181 and the low-resistance body located above the first-type source port 119 (refer to FIG. 1A) At the same time, the low-resistance conductor layer 163 having no half of the first type of impurity region is exposed (please refer to FIG. 1D_2). The low-resistance conductor layer 163 and the second-type conductor in the removal opening 181 are also removed at the same time. One type of the dummy region 1 〇7 above the side of the conductor layer 163 and the first type conductor layer (6). Remove the low resistance conduction. In the wet etching method, it can be recorded by hydrogen peroxide, peroxy. !! Acid or hydrochloric acid deionized water to prepare an appropriate proportion of etching solution. And #式_法射是反应离子酬法. 服干干UMCD-2007-0472 26667twf.doc/p Next 'Removal ® case The photoresist layer 165 is formed (or the hard mask layer is removed), and then a first type conductor layer 167 and another low resistance layer 169 are formed in sequence. The material of the bulk layer 167 is, for example, a p-type metal having a work function of 4.9 to 5 leV, such as a crane, a chemical town, a ruthenium, a titanium nitride, or a ruthenium (Ru). For example, it is a chemical roll deposition method or a sputtering method. The material of the low-resistance conductor layer 169 is, for example, tungsten, indium, TiAl, or crucible, etc. • Then, refer to the figure. 1E-1 and FIG. 1E-2, a planarization process is performed to remove all of the layers above the interlayer dielectric layer 153. The removal method is, for example, a chemical mechanical polishing method in which the dielectric layer 153 is a termination layer, and the excess low-resistance conductor layer 169, the first-type conductor layer 167, the low-resistance conductor layer 163, and the second-type conductor layer 161 are removed. Remove it together. As a result, the first type of transistor 110, the second type of transistor 120, and the high voltage element 130' are formed (refer to FIG. 1E_〇 and the static random access memory 170, (please refer to FIG. Wherein, the first type of transistor ιι 〇 has a dielectric layer 155, a high-k dielectric layer 157, a first-type conductor layer 167 low-resistance conductor 169, a spacer 117 and a low-resistance conductor layer 169 on both sides of the substrate _ The first type of source pole 119. The second type of transistor 12 〇' has a dielectric layer 155, a high-k dielectric layer 157, a second type conductor layer 16, a low-resistance conductor 63, a spacer 127 and the second type source/recording high voltage element (10) in the substrate 1 两侧 on both sides of the low resistance conductor layer 163, having a dielectric layer 155, a high dielectric constant dielectric layer 1.57, and a second type conductor layer 161 The low-resistance conductor layer 163, the spacer 137, and the source/drain 139 in the substrate 1 两侧 on both sides of the low-resistance conductor layer (6) 17 1364799 UMCD-2007-0472 26667 tw.doc/p SRAM 170, And disposed on the substrate 100, at least by the high-k dielectric layer 157, the low-resistance conductor layer 163, the second-type conductor layer 161, and the first The type conductor layer 167 is composed of another low-resistance conductor layer 169. The interlayer dielectric layer 153 on the substrate 1 has an opening 187 which spans the first-type doping region 1〇7 and the isolation structure 1〇. 5 and a second type doped region 109. The high-k dielectric layer 157 is disposed in the opening 187, along the inner wall of the opening 187 and the bottom of the opening 187. The low-resistance conductor layer 163 is disposed in the second type. The doped (4) 1G9 and the partial isolation structure 1〇5_^ are filled in the opening 187 above the half of the second doped region 1〇9. In an embodiment, the upper surface of the low resistance conductor layer 163 and the interlayer dielectric layer 153 The upper surface is approximately equal in height. The second type conductor layer 161 is disposed between the low resistance conductor layer 163 and the high dielectric constant dielectric 5 Å. The first type conductor layer is located above the first type On the high-k dielectric layer 15=, along the exposed sidewall of the low-resistance conductor layer 163 in the opening 187 and the exposed upper surface of the 冋 dielectric constant dielectric layer 157. Another low-resistance conductor layer 169 Then disposed on the first type conductor layer 167, filled in the opening 187. In an implementation The upper surface of the low-resistance conductor layer 169 and the upper surface of the low-resistance conductor layer 163 are, for example, approximately equal. The high-k dielectric layer 157 and the substrate 100 at the bottom of the opening 187, and the spacers 177 on both sides of the opening 187 A dielectric layer 155 may also be disposed to enhance the characteristics of the fishing interface between the high-k dielectric layer 157 and the substrate 100 and the spacer 177. The first type doped region 1〇7, the second type Doped region 1〇9, dielectric layer 155, dielectric constant dielectric layer 157, second type conductor layer (6), low resistance UMCD-2007-0472 26667 twf.doc/p conductor layer 163, first type conductor layer 167 For the material of the low-resistance conductor layer 169, refer to the description in the above manufacturing process, and details are not described herein. In the above static random access memory 170', the high-k dielectric layer 157 is disposed along the inner wall and the bottom of the opening 187, and is not between the first-type conductor layer 167 and the second-type conductor layer ι61 ( Between the PN junctions, there is an extra high-k dielectric layer 'like this', which is also useful for static performance with the 5 access memory. u; ask; 丨 吊 丨; 丨% layer 疋 after the removal of the virtual gate and the static random access memory conductor layer, therefore, the high dielectric t dielectric layer is not vulnerable to damage, and Avoiding multiple passes', the film quality is good, and the high-resistance characteristics of the sisters are constant dielectric layers. The interface properties of the dielectric constant dielectric layer and the first-body layer or the first layer are also improved. "High-voltage: body pressure = piece and the electrical performance of the static random access memory. If the first type source electrode 119 is p-type doped and the first type conductor layer 169 is formed as a p-type conductor sound, = type = body, and is a P-type transistor, then high dielectric conductance = with the younger one The interface quality between the type conductor layers 167 is reduced by the number of warming processes, so that the material voltage of the p-type m is stable to the crystal. ', η.,, second: two' Forming the above-mentioned first-type transistor and static random memory & (refer to the figure called) in order: = 170 (凊 refer to FIG. 1E_2), and the interlayer dielectric layer 153 can also be removed. Method Example 1364799 UMCD-2007-0472 26667twf.d〇c/p If the wetness type is engraved, in one embodiment, if the mask layer 15 is double layer of the bottom oxide layer and the top nitride layer The structure may also be to remove only the top tantalum nitride layer while leaving the bottom oxide layer. Then, a contact window etch stop layer 191 is formed on the substrate 1 ( Contact Etching St〇p Lay=,
CESL)。這一層蝕刻終止層191的材質例如是氮化矽，可 以用來改魏力’以增加電晶體的操作速f至於後續完 成半導體結構，例如製作接觸窗、介層窗、導線等等的方 法應為本領域之技術人員所週知，於此不贅述。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限縣發明，任何熟習此技藝者，在不脫離本發明之精神 和祀圍内’當可作些許之更動與潤飾，@此本發明之保護 範圍當視_之中請專職_界定者為準。 【圖式簡單說明】 圖1A-1至圖IF]是緣示本發明一實施例之一種半導 體結構的製造流程剖面圖。 圖1A-2至圖1F_2早剩·痛μCESL). The material of the etch stop layer 191 is, for example, tantalum nitride, which can be used to change the operating speed f of the transistor to complete the semiconductor structure, for example, to make contact windows, vias, wires, etc. It is well known to those skilled in the art and will not be described here. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and anyone skilled in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of protection of the present invention is determined by the full-time definition. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A-1 to Fig. IF are cross-sectional views showing a manufacturing process of a semiconductor structure according to an embodiment of the present invention. Figure 1A-2 to Figure 1F_2
一 2疋對應於圖1Α-1至圖1F-1的步驟， 繪不本發明-實施例之—種靜態隨機存取記憶體之製造流 【主要元件符號說明】 100 基底 105 隔離結構 107 第一型—摻雜區 109 第二型摻雜區 110 第一電晶體 20 1364799 UMCD-2007-0472 26667twf.doc/p 110’ ：第一型電晶體 111、121、131 :閘介電層 113、123、133 :虛擬閘極 115、125、135、145、175 :硬罩幕層 117、127、137、147、177 :間隙壁 119 :第一型源極/汲極 120 :第二電晶體 120’ ：第二型電晶體 129 :第二型源極/汲極 130 :高壓元件 130’ ：高壓元件 139 :源極/汲極 140 :電阻器 141 :電容絕緣層 143 :上電極 151 :罩幕層 153 :層間介電層 154 :圖案化光阻層 155 :介電層 157 :高介電常數介電層 161 :第二型導體層 163、_ 169 :低電阻導體層 165 :圖案化光阻層 167 :第一型導體層 21 1364799 UMCD-2007-0472 26667twf.doc/p1疋 corresponds to the steps of FIG. 1Α-1 to FIG. 1F-1, and the manufacturing flow of the static random access memory of the present invention is not illustrated. [Main component symbol description] 100 Substrate 105 isolation structure 107 First Type-doped region 109 second type doped region 110 first transistor 20 1364799 UMCD-2007-0472 26667twf.doc/p 110': first type transistor 111, 121, 131: gate dielectric layer 113, 123 , 133: virtual gate 115, 125, 135, 145, 175: hard mask layer 117, 127, 137, 147, 177: spacer 119: first type source/drain 120: second transistor 120' : second type transistor 129 : second type source/drain 130 : high voltage element 130 ′ : high voltage element 139 : source/drain 140 : resistor 141 : capacitor insulating layer 143 : upper electrode 151 : mask layer 153: interlayer dielectric layer 154: patterned photoresist layer 155: dielectric layer 157: high-k dielectric layer 161: second-type conductor layer 163, _169: low-resistance conductor layer 165: patterned photoresist layer 167: first type conductor layer 21 1364799 UMCD-2007-0472 26667twf.doc/p
170、170’ ：靜態隨機存取記憶體 171 :底介電層 173 :導體層 181、183、185、187 :開口 191 :接觸窗蝕刻終止層 22170, 170': SRAM 171: bottom dielectric layer 173: conductor layer 181, 183, 185, 187: opening 191: contact etch stop layer 22