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TW200943434A - Method for fabricating semiconductor structure and structure of static random access memory - Google Patents

Method for fabricating semiconductor structure and structure of static random access memory

Info

Publication number
TW200943434A
TW200943434A TW97112278A TW97112278A TW200943434A TW 200943434 A TW200943434 A TW 200943434A TW 97112278 A TW97112278 A TW 97112278A TW 97112278 A TW97112278 A TW 97112278A TW 200943434 A TW200943434 A TW 200943434A
Authority
TW
Taiwan
Prior art keywords
conductive layer
low resistance
random access
access memory
transistor
Prior art date
Application number
TW97112278A
Other languages
Chinese (zh)
Other versions
TWI364799B (en
Inventor
Chih-Hao Yu
Li-Wei Cheng
Che-Hua Hsu
Tian-Fu Chiang
Cheng-Hsien Chou
Chien-Ming Lai
Yi-Wen Chen
Chien-Ting Lin
Guang-Hwa Ma
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW97112278A priority Critical patent/TWI364799B/en
Publication of TW200943434A publication Critical patent/TW200943434A/en
Application granted granted Critical
Publication of TWI364799B publication Critical patent/TWI364799B/en

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Abstract

A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.
TW97112278A 2008-04-03 2008-04-03 Method for fabricating semiconductor structure and structure of static random access memory TWI364799B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW97112278A TWI364799B (en) 2008-04-03 2008-04-03 Method for fabricating semiconductor structure and structure of static random access memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW97112278A TWI364799B (en) 2008-04-03 2008-04-03 Method for fabricating semiconductor structure and structure of static random access memory

Publications (2)

Publication Number Publication Date
TW200943434A true TW200943434A (en) 2009-10-16
TWI364799B TWI364799B (en) 2012-05-21

Family

ID=44869010

Family Applications (1)

Application Number Title Priority Date Filing Date
TW97112278A TWI364799B (en) 2008-04-03 2008-04-03 Method for fabricating semiconductor structure and structure of static random access memory

Country Status (1)

Country Link
TW (1) TWI364799B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI898421B (en) * 2024-02-05 2025-09-21 瑞昱半導體股份有限公司 Filler cell, semiconductor device, and logic circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI898421B (en) * 2024-02-05 2025-09-21 瑞昱半導體股份有限公司 Filler cell, semiconductor device, and logic circuit

Also Published As

Publication number Publication date
TWI364799B (en) 2012-05-21

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