1357785 0707006/0707008 25859twf.doc/n 九、發明說明： 【發明所屬之技術領域】 • 本發明是有關於一種線路板的製造方法，且特別是有 • 關於一種線路板的線路結構的製造方法。 【先前技術】 近年來，心著電子技術的曰新月異，以及高科技電子 產業的相繼問世，使得更人性化、功能更佳的電子產品不 籲斷地推陳出新，並朝向輕、薄、短、小的趨勢邁進。在此 趨勢之下，由於線路板具有佈線細密、組裝緊湊及性能良 - 好等優點，因此線路板便成為承載多個電子元件以及使這 些電子元件彼此電性連接的主要媒介之—。 【發明内容】 本發明提供一種線路結構的製造方法，具有較高的製 - 程良率。 本發明提出一種線路結構的製造方法。首先，提供一 _ 線路載板。線路載板包括一介電層、—第—複合層及一第 一線路層。 一介電層具有一第一接合部與一圍繞第—接合部的第 二接合部，且第一接合部具有一第_表面以及一與第一表 面2對的第二表面。第一複合層與第—接合部的第一表面 =合，而第二接合部延伸至第一複合層的側面，且第二接 合部與第一複合層的側面接合。第/複合層包括一第一導 電層及一第二導電層，其中第二導電層位於第一導電層與 第一接合部之間。第一線路層配置於第一導電層上。、 5 1357785 0707006/0707008 25859twf.doc/n 接著，壓合線路載板至一第一介電片上，使第 層鑲嵌至第-介電片’並使第二接合部與第—介電片 ^。然後，移除第二接合部及部分與第二接合部相接合^ 第-介電片。之後，移除第二導電層及第—接合部。 在本發明之-實施例中，其中線路載板更包括 第二線路層。第二複合層與第-接合部的第： =接&。第二接合部延伸至第二複合層的側面，且第二 t部與第二複合層的側面接合。第二複 t ^接口狀間。此外，弟二線路層配置於第三導電層 其中，當壓合線路載板至第一介 路載板至-第二介電片上，使第二線路=至;壓t 部及部分與第二接合部相接合的第 ^除^接合 分與第二接合部相接合的第二介電片，以除部 電層與第-接合部時，更移除第四導電層。田夕示第-導 在本發明之-實_中，鎌第 解除第三導電層與第四導電層之介面的接2的方法包括 在本發明之-實施财，解除第三導μ 層之介面的接合力的方法包括以機械、化^=四導電 來使第三導電層與第四導電層之介面分離/的方式 在本發明之—實施例中，移除第二導電 解除第-導電層與第二導電層之介面的接合^去匕括 6 0707006/0707008 25859twf.doc/n 在本發明之一實施例中，解除第—導電層與第二導電 層之介面的接合力的方法包括以機械、化學或二二二 來使第一導電層與第二導電層之介面分離。/ 的方式 在本發明之一實施例中，介電層的材質包括熱塑型樹 脂或熱固型樹脂。 在本發明之-實施射，介電層的厚度介於 400/zm。 μ 在本發明之一實施例中，第〜導電層的厚度介於Μ m 〜10 μ m 〇 在本發明之-實施例中，第、導電層的材質包括紹、 銅、辞、鎳、錫或前述之組合。 在本發明之-實施例中，第三導電層的厚度介於k m〜10/zm之間。 在本發明之-實施例中，第二導電層的厚度介於^ m〜30/z m。 在本發明之-實施例中，第二導電層的材質包括銘、 銅、錄或前述之組合。 在本發明之一實施例中，第四導電層的厚度介於 m〜30" m之間。 在本發明之一實施例中，第〜線路層的材質包括銅、 録、鋅、錫、金或前述之組合。 本發明提出一種線路結構的製造方法。首先，提供一 線路載板。線路載板包括一複合層、—第一導電層及一第 一線路層。其中，複合層包括一第/金屬層及一第二金屬 0707006/0707008 25859twf.doc/n 層。第-導電層配置於第-金屬層上，而且第—線路層配 置於第-導電層上。接著，壓合線路載板至—第一介電片 使第—線路層鑲嵌至第—介電片。然後，以餘刻法 移除第—金屬層。 芦，實施例中，複合層更包括—第三金屬 ;上。;路==以;對於第一金屬層的表 二導電層配置於第三金屬層上，^與線路層笛第 d::';:r至第-介電片上時，更 二介電片。 罨片上，使第二線路層鑲嵌至第 屬。在本翻之—實施财金騎的㈣包括鈍金 屬。在本發明之—實施财，第三金屬層㈣質包括鈍金 锡、==之—實施例中，第—金屬層的材質包括鋅、 殊或别述之組合。 锡、鋅Λ此例中’第三金屬層的材質包括鋅、 果及月'』迷之組合。 在本發明之一膏施例中， ^ 0 “m〜弟一金屬層的厚度介於0.01 〜明之—實施例巾’第三金屬層的厚度介於0.01 J.uu // m。 在本發明之一實施例中，第二金屬層的材質包括銘、 0707006/0707008 25859twf.doc/n 銅、錄或前述之組合。 在本發明之一實施例中，第二金屬層的厚度介於4〇 μ m〜400 /z m。 在本發明之一實施例中，第一導電層的材質包括銅、 錄或金。 在本發明之一實施例中，弟^一導電層的材質包括銅、 鎳或金。 在本發明之一實施例中，第一導電層的厚度介於〗“ m 〜lOem。 在本發明之一實施例中，第二導電層的厚度介於丨 〜10 V m。 在本發明之一實施例中，第一線路層的材質包括銅、 鎳、鋅、錫、金或前述之組合。 綜上所述，本發明之一實施例之線路結構的製造方法 是採用一種介電層與第一複合層的側面接合的線路載板， 以確保在製程中第一複合層的兩導電層不會相互剝離。另 外，本發明之另一實施例之線路結構的製造方法是採用一 種由多層金屬層所組成的線路載板，並以蝕刻法來移除線 路載板，以提高線路結構的尺寸穩定性。 *為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉實施例，並配合所附圖式，作詳細說明如 下。 【實施方式】 圖1A〜圖1D為本發明一實施例之線路結構的製造方 0707006/0707008 25859twf.doc/n 法的拍流程圖。百先’請參照圖M _。線路载板100包括-介電；lw 線路载板 及-第-線路層⑽。介雷上二 弟一複合層120 禾琛峪層υυ ;丨電層110具有一第一 與一圍繞第一接合部112的第人口。 ⑴具有一第一表㈣二 第二表面（未!會示）。此外，介電層11〇的材質可 型樹脂、熱固型樹脂或是其他適合的介 ^ 的厚度例如是介於3以m〜㈣。㈣h層110 第-複合層uo與第一接合部112的第一表面心 =，而第二接合部114延伸至第一複合層12〇的側面 。而且’第二接合部114與第—複合層12()的側面122 。如此，可防止第-導電層12Ga與第二導電層12〇b 在之後的製程中不當分離。 二第一複合層120包括一第一導電層12〇a及一第二導 電層120b。第二導電層位於第一導電層·與第一 接合，112之間。在本實施例中，第一導電層12〇&的厚度 例如疋”於。此外，第二導電層12〇b的厚 度例如是介於5 〜30 μ m。第一線路層 130配置於第一 導電層120a上。 另外’第一導電層120a的材質例如是鋁、銅、辞' 錄、錫或前述之組合。而第二導電層l2〇b的材質主要為 結’其次為銅、鎳或前述之組合等具高機械強度之導電性 金屬材料。其中，第一導電層120a的材質與第二導電層 120b的材質不同。第一線路層13〇的材質主要為銅’也可 0707006/0707008 25859twf.doc/n 以是録、辞、錫、金等導電性金屬。第一線路層130的厚 度例如介於2/zm〜40//m之間。第一線路層13〇的線間 距（pitch )例如介於8 /z m〜80 " m之間。 第一導電層120a具有一表面122a，第二導電層12〇b 具有一表面122b，且第一導電層i2〇a與第二導電層12〇b 相接合之處有一介面124。在本實施例中，表面Q2a與表 面122b的表面粗糙度（Ra)例如是介於〇"m， 而十點平均粗糙度（Rz)例如是介於l.2jfzm〜8 〇ym。 此外，介面124的表面粗糙度（Ra)例如是介於 〜0.5/zm，而十點平均粗糙度（Rz)例如是介於〇8 /zm〜5.0Am。也就是說，表面122a與表面相較於 介面124而言，具有較粗糙的表面，而介面124相對為較 光滑的表面。由於表面122b為較粗糙面，因此，表面122b 可與介電層110良好接合。 接著，睛參照圖1B，壓合線路載板100至一第一介 電片200上’使第一線路層130鑲嵌至第-介電片200, 並使第二接合部114與第—介電片2⑻接合。第一介電片 200可為乂半固化樹脂片（卿吨pp)。此外由於表面 122a為較粗糙面，目此，表面m可與第一介 此外’再提供—線路載板隐，且線路載板舰可 二板1〇。相同。並且，可將線路載板100&壓合至第 的g — 相對於線路载板100的一面，使線路載板 、-層130鑲嵌至第一介電片200，並使第二 1357785 0707006/0707008 25859twf.doc/n 接合部114與第一介電片200接合。如此，將可製得一雙 層板。 . 然後，請參照圖1C，移除第二接合部114及部分與 • 第二接合部114相接合的第一介電片200。如此，可 一導電層120a與第二導電層12〇b易於分離。而且，由於 介面124為較光滑面，因此第一導電層12〇&與第二導電層 ㈣之間接合力較小，進而使得第—導電層咖 二 • 導電層麗更容易分離。同時，也可一併移除部分^第一 複合層120的邊緣與第一接合部112的邊緣。 - 之後’請參照圖1D，移除第二導電層120b及第一接 合部112，以形成-線路結構3〇〇。線路結才籌3〇〇可為一雙 層板。 在本實施例中，移除第二導電層12%的方法可以是 - 解除第一導電層120a與第二導電層120b之介面的接人 力。而且’解除第一導電層咖與第二導電層i勘之; _ _接合力的方法例如是以機械、化學或物理的方式來使 第-導電層i2〇a與第二導電層議之介面分離。製作完 成的線路結構3GG可依照需要來加n線路板。 圖2A〜圖2D為本發明另—實施例之線路結構的製造 方法的剖面流程圖。 基本上，本實施例與前述實施例製造方法類似，惟兩 差異之處在於本實施例之線路餘為雙面祕載板（即 f本^施例之線路載板不但具有第—複合層與第一線路 « ’遇具有第二複合層與第二線路層）。因此，本實施例 12 1357785 0707006/0707008 25859twf.doc/n 之線路載板不但可將第一線路層鑲嵌至第一介電片，還可 將第二線路層鑲嵌至-第二介電片。也就是說，本實施例 之線路載板可同時在兩個介電片上形成線路層。 首先’請參照圖2A，提供至少一線路載板4〇〇。線路 载板400與線路載板1〇〇 (請參照圖1A)相似，惟兩者差 異之處在於線路載板400更包括一第二複合層41〇鱼一第 二線路層420。 ' 如圖2A所示，第二複合層41〇與第-接合部112的 第二表面U2b接合。第二接合部114延伸至第:複合： :的，面」且第二接合部114與第二複合層41〇的側面 σ。弟—複合層41G包括—第三導電層41()&及—第四 =:拠’其中第四導電層4鳴位於第三導電層41〇a與 & °卩112之間。第二導電層410a的厚度例如是介於 5 = 之間。第四導電層働的厚度例如是介於 3 /z m〜30/z m 之間。 M 一 Ϊ外’第二線路層420配置於第三導電層410a上。 第一線路層420的材質主暴发, 金算㈣@、要為鋼，也可以是鎳、辞、錫、 幻至屬。第一線路層的厚度例如介於 :_之間。第二線路層42〇的線間 二 〜80μm之間。 μ u 電片參照圖2B，當壓合線路載板_至第一介 2〇〇 μ日：’更同時壓合線路载板400至一第二介電片 a ，使第二線，路層420鑲嵌至第介電 第二接合部-八泰 乐一”电月aoa，並使 搔口。P 114與第一介電片2〇〇a接合。圖料示多個 13 1357785 0707006/0707008 25859twf.doc/n 線路載板400 ’然並非用以限定本發明之線路载板_ 數量。舉例來說’線路載板400的數量也可以是只有一個'。 • 此外，再提供一線路载板4〇〇a與兩個線路载板1〇〇。 ‘ 線路載板400a可與線路载板400相同。並且，可於壓人 路載板400至第-介電片與第二介電片高'上^同 時，將線路載板400a壓合至第二介電片2〇〇a之相對於線 路載板400的一面，使線路載板4〇〇a的第一線路層 • 鑲嵌至第二介電片2⑻a，並使線路载板4〇〇a的第二接合 •部114與第二介電片2〇〇a接合。同時，可使線路載板4〇二 • 的第二線路層420鑲嵌至一第三介電片200b，並使線路载 板400a的第二接合部114與第三介電片200b接合。 ”此日守，還可使其中一線路載板100的第一線路層13〇 . 壓合至第一介電片200之相對於線路载板400的一面，使 . 線路載板100的第一線路層130鑲嵌至第一介電片2〇〇， 並使線路載板100的第二接合部114與第一介電片2〇〇接 • 合。同時’還可使其中另一線路載板100的第一線路層130 壓合至第二介電片200b之相對於線路載板4〇〇&的一面， 使線路載板100的第一線路層13〇鑲嵌至第三介電片 200b，並使線路載板1〇〇的第二接合部丨14與第三介電片 200b接合。如此，將可製得雙層板。 然後，请參照圖2C，當移除第二接合部114及部分 與第二接合部114相接合的第一介電片2〇〇時，更移除部 分與第二接合部114相接合的第二介電片2〇〇a與第三介電 片200b。同時，也可一併移除部分的第一複合層12〇與第 1357785 0707006/0707008 25859twf.doc/n 二複合層410的邊緣。 之後，請參照圖2D，當移除第二導電層12〇b與第一 接合部112時，更移除第四導電層4i〇b，以形成多個線路 . 結構500。於圖2D中，僅繪示一個線路結構500為代表。 此外，移除第四導電層410b的方法例如解除第三導 電層410a與第四導電層41〇b之介面的接合力。而解除第 三導電層410a與該第四導電層41〇b之介面的接合力的方 • 法例如是以機械、化學或物理的方式來使第三導電層410a 與第四導電層410b之介面分離。 承上所述，以線路載板4〇〇可同時製得至少兩層線路 層130、420。並且’若壓合由多個線路載板4〇〇、4〇如、 ⑽與多個介電片2GG、200a、2GGb交錯堆疊的結構時， 可同時形成多個線路層13〇、42()於這些介電片·、2〇〇a、 .2〇%上。因此，可提高生產效率，並同時降低生產成本。 圖3A〜圖3C為本發明又—實施例之線路結構的製造 # 方法的剖面流程圖。首先’請參照圖3A，提供一線路載板 _。線路載板_包括—複合層議、—第—導電層62〇 及一線路層630。複合層61〇包括一第一金屬層612 及-弟二金屬層614。第-導電層62〇配置於第一金屬層 612上並具有—表面622，而且第—線路層㈣配置於第一 電層620的表面622上。 第一金屬層612的材質例如是純金屬。此外，第一金 恳曰612的材質可為辞、锡、錄或前述之組合。第一金屬 層612的厚度例如是介於〇·〇1_〜5御瓜之間。第二 1357785 0707006/0707008 25859twf.doc/n 金屬層614的材質包括鋁、銅、鎳或前述之組合。第二金 屬層614的厚度介於4〇//m〜4〇〇#m之間。第一導電層 • 620的表面622的表面粗糙度（Ra)例如是介於〇.2以m〜 1.0从而十點平均粗糙度（Rz)例如是介於12#m〜8 〇 /zm。第一導電層620的材質包括銅、鎳、金或是其他適 合的導電材料。此外，第一導電層62〇的厚度例如是介於 1从m〜10# m之間。第一線路層63〇的材質主要為銅也 _ 可以是鎳、辞、錫、金等導電性金屬，而其厚.度例如介於 2/zm〜40#m之間。第一線路層63〇的線間距例如介於8 //m〜80/zm之間。 接著，請參照圖3B，壓合線路載板600至一第一介 電片700上，以使第一線路層63〇鑲嵌至第一介電片7⑻。 由於表面622為較粗輪面，因此表面622可與第一介電片 .700良好接合。另外，第一介電片700可為半固化樹脂片。 此外，再提供一線路載板600a，且線路載板6〇〇a可與線 • 路载板600相同。並且，可將線路載板600a壓合至第一介 電^ 700之相對於線路载板600的一面，使線路載板6〇〇a 2第一線路層630鑲嵌至第一介電片7〇〇。如此，將可制 得一雙層板。 衣 、，然後，請參照圖3C，以蝕刻法移除第二金屬層614， 以形成一線路結構800。在本實施例中，以蝕刻法移除第 —金屬層614，可具有較高的製程良率。此外，線路結構 8〇〇可為一雙層板。製作完成的線路結構8〇〇可依照需 1加工成為線路板。 16 1357785 0707006/0707008 25859twf.doc/n 的製造 圖4A〜圖4C為本發明再一實施例之線路結構 方法的剖面流程圖。 基本上，本實施例與前述實施例製造方法類似，惟 者差異之處在於本實施例之線路載板為雙面線路栽板^ 與-具有第-金屬層與第二金屬層的複合層，層1357785 0707006/0707008 25859twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a method of manufacturing a wiring board, and particularly to a method of manufacturing a wiring structure of a wiring board. [Prior Art] In recent years, with the rapid development of electronic technology and the advent of high-tech electronics industry, electronic products with more humanization and better functions have been unrelentingly introduced, and are light, thin and short. The small trend is moving forward. Under this trend, the circuit board has the advantages of fine wiring, compact assembly, and good performance, so that the circuit board becomes the main medium for carrying a plurality of electronic components and electrically connecting the electronic components to each other. SUMMARY OF THE INVENTION The present invention provides a method of fabricating a line structure having a high process yield. The invention provides a method of manufacturing a line structure. First, provide a _ line carrier. The line carrier includes a dielectric layer, a first composite layer and a first circuit layer. A dielectric layer has a first joint and a second joint surrounding the first joint, and the first joint has a first surface and a second surface opposite the first surface 2. The first composite layer is joined to the first surface of the first joint portion, and the second joint portion extends to the side of the first composite layer, and the second joint portion is joined to the side surface of the first composite layer. The first/composite layer includes a first conductive layer and a second conductive layer, wherein the second conductive layer is located between the first conductive layer and the first joint. The first circuit layer is disposed on the first conductive layer. 5 1357785 0707006/0707008 25859twf.doc/n Next, press the line carrier to a first dielectric sheet, so that the first layer is inlaid to the first dielectric sheet 'and the second junction portion and the first dielectric sheet ^ . Then, the second bonding portion and the portion are removed from the second bonding portion. Thereafter, the second conductive layer and the first bonding portion are removed. In an embodiment of the invention, wherein the line carrier further comprises a second circuit layer. The second composite layer and the first portion of the first joint portion: = connected & The second joint extends to the side of the second composite layer and the second t portion is joined to the side of the second composite layer. The second complex t ^ interface. In addition, the second circuit layer is disposed in the third conductive layer, when the line carrier is pressed to the first dielectric carrier to the second dielectric sheet, so that the second line = to; the pressure t portion and the portion and the second The second dielectric sheet joined to the second bonding portion by the bonding portion of the bonding portion to remove the fourth conductive layer when the electrical layer and the first bonding portion are removed. In the present invention, the method for releasing the interface between the third conductive layer and the fourth conductive layer is included in the present invention, and the third conductive layer is released. The method of bonding the interface includes mechanically separating the third conductive layer from the interface of the fourth conductive layer. In the embodiment of the present invention, removing the second conductive release-conducting The bonding between the layer and the interface of the second conductive layer includes a method of removing the bonding force between the interface of the first conductive layer and the second conductive layer. In one embodiment of the present invention, the method for releasing the bonding force between the interface of the first conductive layer and the second conductive layer includes The interface between the first conductive layer and the second conductive layer is separated by mechanical, chemical or two-two. Mode of the Invention In one embodiment of the invention, the material of the dielectric layer comprises a thermoplastic resin or a thermosetting resin. In the practice of the invention, the thickness of the dielectric layer is between 400/zm. In one embodiment of the present invention, the thickness of the first conductive layer is between Μm and 10 μm. In the embodiment of the present invention, the material of the conductive layer includes Shao, copper, rhodium, nickel, and tin. Or a combination of the foregoing. In an embodiment of the invention, the thickness of the third conductive layer is between k m and 10/zm. In an embodiment of the invention, the thickness of the second conductive layer is between ^m and 30/zm. In the embodiment of the invention, the material of the second conductive layer comprises Ming, Copper, Record or a combination of the foregoing. In an embodiment of the invention, the thickness of the fourth conductive layer is between m and 30 " m. In an embodiment of the invention, the material of the first circuit layer comprises copper, copper, tin, gold or a combination thereof. The invention provides a method of manufacturing a line structure. First, a line carrier is provided. The line carrier includes a composite layer, a first conductive layer and a first circuit layer. Wherein, the composite layer comprises a metal/metal layer and a second metal layer 0707006/0707008 25859twf.doc/n. The first conductive layer is disposed on the first metal layer, and the first circuit layer is disposed on the first conductive layer. Next, the line carrier is pressed to the first dielectric sheet to insulate the first circuit layer to the first dielectric layer. Then, the first metal layer is removed by a residual method. Reed, in the embodiment, the composite layer further comprises a third metal; ; road == to; for the first metal layer of the second conductive layer is disposed on the third metal layer, and the circuit layer flute d:: ';: r to the first dielectric sheet, the second dielectric sheet . On the cymbal, the second circuit layer is inlaid to the first genus. In this case, the implementation of the financial ride (four) includes blunt metal. In the embodiment of the present invention, the third metal layer (four) material includes blunt gold tin, == - in the embodiment, the material of the first metal layer includes zinc, special or a combination thereof. Tin, zinc bismuth In this case, the material of the third metal layer includes a combination of zinc, fruit and moon. In one embodiment of the present invention, the thickness of the ^0 "m~di-metal layer is between 0.01 and - the thickness of the third metal layer of the embodiment towel is 0.01 J.uu // m. In the present invention In one embodiment, the material of the second metal layer comprises Ming, 0707006/0707008 25859twf.doc/n copper, recorded or a combination thereof. In one embodiment of the invention, the thickness of the second metal layer is between 4〇 In one embodiment of the invention, the material of the first conductive layer comprises copper, gold or gold. In an embodiment of the invention, the material of the conductive layer comprises copper, nickel or In one embodiment of the invention, the thickness of the first conductive layer is between "m" and lOem. In one embodiment of the invention, the second conductive layer has a thickness of between 丨 10 10 V m. In an embodiment of the invention, the material of the first circuit layer comprises copper, nickel, zinc, tin, gold or a combination thereof. In summary, the method for fabricating a line structure according to an embodiment of the present invention uses a line carrier plate with a dielectric layer bonded to the side of the first composite layer to ensure that the two conductive layers of the first composite layer are not in the process. Will be stripped from each other. Further, the wiring structure of another embodiment of the present invention is manufactured by using a wiring carrier composed of a plurality of metal layers, and etching the wiring carrier to improve the dimensional stability of the wiring structure. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the invention. [Embodiment] Figs. 1A to 1D are flowcharts showing a method of manufacturing a line structure 0707006/0707008 25859twf.doc/n according to an embodiment of the present invention. Please refer to the figure M _. The line carrier 100 includes - dielectric; lw line carrier and - first-circuit layer (10). The second layer of the second layer is a composite layer 120 and a layer of the first layer and a first portion of the first joint portion 112. (1) has a first table (four) two second surface (not! shown). Further, the dielectric layer 11 is made of a resin, a thermosetting resin or the like, for example, having a thickness of, for example, 3 m to (4). (4) The h-layer 110 the first-composite layer uo and the first surface of the first joint portion 112 are =, and the second joint portion 114 extends to the side of the first composite layer 12''. Further, the second joint portion 114 and the side surface 122 of the first composite layer 12 (). Thus, the first conductive layer 12Ga and the second conductive layer 12b can be prevented from being improperly separated in the subsequent process. The second composite layer 120 includes a first conductive layer 12A and a second conductive layer 120b. The second conductive layer is between the first conductive layer and the first bond 112. In this embodiment, the thickness of the first conductive layer 12〇& is, for example, 。". Further, the thickness of the second conductive layer 12b is, for example, 5 to 30 μm. The first circuit layer 130 is disposed at the Further, the material of the first conductive layer 120a is, for example, aluminum, copper, smear, tin or a combination thereof. The material of the second conductive layer 12b is mainly a junction, followed by copper and nickel. Or a conductive metal material having high mechanical strength, such as a combination of the foregoing, wherein the material of the first conductive layer 120a is different from the material of the second conductive layer 120b. The material of the first circuit layer 13 is mainly copper '0707006/ 0707008 25859twf.doc/n is a conductive metal such as a recording, a word, tin, gold, etc. The thickness of the first wiring layer 130 is, for example, between 2/zm and 40//m. The line spacing of the first wiring layer 13〇 (pitch ) is, for example, between 8 /zm and 80 " m. The first conductive layer 120a has a surface 122a, the second conductive layer 12b has a surface 122b, and the first conductive layer i2〇a and the second The conductive layer 12〇b is joined to have an interface 124. In this embodiment, the surface of the surface Q2a and the surface 122b The roughness (Ra) is, for example, between 〇"m, and the ten-point average roughness (Rz) is, for example, between 1.2 μfzm and 8 〇 ym. Further, the surface roughness (Ra) of the interface 124 is, for example, ~0.5/zm, and the ten point average roughness (Rz) is, for example, between 〇8 /zm~5.0Am. That is, the surface 122a and the surface have a rougher surface than the interface 124, and the interface 124 is relatively smooth surface. Since the surface 122b is a rough surface, the surface 122b can be well joined to the dielectric layer 110. Next, referring to FIG. 1B, the line carrier 100 is bonded to a first dielectric sheet 200. The first wiring layer 130 is mounted on the first dielectric layer 200, and the second bonding portion 114 is bonded to the first dielectric sheet 2 (8). The first dielectric sheet 200 may be a semi-cured resin sheet (Qing ton pp In addition, since the surface 122a is a rough surface, the surface m can be 're-provided with the first medium--the line carrier is hidden, and the line carrier can be the same as the second board. The board 100& is pressed to the first g - with respect to one side of the line carrier 100, so that the line carrier, the layer 130 is inlaid to the first interface The sheet 200 is brought into engagement with the first dielectric sheet 200 by the second 1357785 0707006/0707008 25859twf.doc/n joint portion 114. Thus, a two-layer board can be produced. Then, referring to FIG. 1C, the first The second bonding portion 114 and the first dielectric sheet 200 partially joined to the second bonding portion 114. Thus, the conductive layer 120a and the second conductive layer 12b can be easily separated. Moreover, since the interface 124 is a smoother surface, the bonding force between the first conductive layer 12〇& and the second conductive layer (4) is smaller, thereby making the first conductive layer and the conductive layer easier to separate. At the same time, the edge of the portion of the first composite layer 120 and the edge of the first joint portion 112 may be removed together. - Thereafter - Referring to Fig. 1D, the second conductive layer 120b and the first joint portion 112 are removed to form a - line structure 3A. The line knot can only be a double layer. In this embodiment, the method of removing the second conductive layer 12% may be - releasing the interface of the interface between the first conductive layer 120a and the second conductive layer 120b. Moreover, the method of removing the first conductive layer and the second conductive layer is performed; for example, the method of bonding the first conductive layer i2〇a and the second conductive layer is mechanically, chemically or physically. Separation. The finished circuit structure 3GG can be added with n circuit boards as needed. 2A to 2D are cross-sectional flowcharts showing a method of manufacturing a line structure according to another embodiment of the present invention. Basically, this embodiment is similar to the manufacturing method of the foregoing embodiment, except that the difference between the two is that the line of the embodiment is a double-sided secret carrier (ie, the circuit carrier of the embodiment has not only the first composite layer and The first line « 'has a second composite layer and a second circuit layer). Therefore, the line carrier of the embodiment 12 1357785 0707006/0707008 25859twf.doc/n can not only embed the first circuit layer to the first dielectric layer, but also the second circuit layer to the second dielectric sheet. That is, the line carrier of the present embodiment can simultaneously form a wiring layer on two dielectric sheets. First, please refer to FIG. 2A to provide at least one line carrier 4〇〇. The line carrier 400 is similar to the line carrier 1 (please refer to FIG. 1A), except that the line carrier 400 further includes a second composite layer 41 squid-second circuit layer 420. As shown in Fig. 2A, the second composite layer 41 is joined to the second surface U2b of the first joint portion 112. The second joint portion 114 extends to the first surface of the second composite portion 114 and the side surface σ of the second composite layer 41〇. The composite layer 41G includes a third conductive layer 41()& and - a fourth =: 拠' wherein the fourth conductive layer 4 is located between the third conductive layers 41a and < The thickness of the second conductive layer 410a is, for example, between 5 =. The thickness of the fourth conductive layer 例如 is, for example, between 3 /z m and 30/z m . The second wiring layer 420 is disposed on the third conductive layer 410a. The material of the first circuit layer 420 is mainly outbreak, the gold calculation (four) @, the steel, or the nickel, the word, the tin, the genus to the genus. The thickness of the first circuit layer is, for example, between:_. The line of the second circuit layer 42 is between two and 80 μm. μ u The electric film refers to FIG. 2B, when the splicing line carrier _ to the first 2 〇〇 μ day: 'more simultaneously presses the line carrier 400 to a second dielectric sheet a, so that the second line, the road layer 420 is inlaid to the second dielectric joint of the second dielectric - eight taylor "one month aoa, and the mouth. P 114 is engaged with the first dielectric sheet 2 〇〇 a. The figure shows a plurality of 13 1357785 0707006/0707008 25859twf The .doc/n line carrier 400 is not intended to limit the number of line carriers of the present invention. For example, 'the number of line carriers 400 may be only one'. • In addition, a line carrier 4 is provided. 〇〇a is connected to two line carriers 1'. The line carrier 400a can be the same as the line carrier 400. Moreover, it can be used to press the road carrier 400 to the first and the second and the second dielectric. Simultaneously, the line carrier 400a is pressed to the side of the second dielectric sheet 2A relative to the line carrier 400, so that the first circuit layer of the line carrier 4A is embedded in the second layer. The electric piece 2 (8) a, and the second joint portion 114 of the line carrier 4A is engaged with the second dielectric sheet 2A. At the same time, the second line of the line carrier 4 can be made The layer 420 is inlaid to a third dielectric sheet 200b, and the second bonding portion 114 of the line carrier 400a is bonded to the third dielectric sheet 200b. "This day, the first of the line carrier 100 can also be made. The circuit layer 13 is press-bonded to one side of the first dielectric sheet 200 with respect to the line carrier 400 such that the first wiring layer 130 of the line carrier 100 is inlaid to the first dielectric sheet 2, and the line is The second bonding portion 114 of the carrier 100 is coupled to the first dielectric sheet 2. At the same time, the first circuit layer 130 of the other line carrier 100 may be pressed to the side of the second dielectric sheet 200b relative to the line carrier 4 & the first line of the line carrier 100 The layer 13 is inlaid into the third dielectric sheet 200b, and the second bonding portion 14 of the line carrier 1 is bonded to the third dielectric sheet 200b. In this way, a double layer panel can be produced. Then, referring to FIG. 2C, when the second bonding portion 114 and the first dielectric sheet 2 部分 that is partially engaged with the second bonding portion 114 are removed, the portion where the removal portion is joined to the second bonding portion 114 is further removed. Two dielectric sheets 2A and a third dielectric sheet 200b. At the same time, part of the first composite layer 12〇 and the edge of the 1357785 0707006/0707008 25859twf.doc/n two composite layer 410 may also be removed. Thereafter, referring to FIG. 2D, when the second conductive layer 12〇b and the first bonding portion 112 are removed, the fourth conductive layer 4i〇b is further removed to form a plurality of lines. In FIG. 2D, only one line structure 500 is shown. Further, the method of removing the fourth conductive layer 410b is, for example, releasing the bonding force of the interface between the third conductive layer 410a and the fourth conductive layer 41b. The method of releasing the bonding force between the third conductive layer 410a and the interface of the fourth conductive layer 41b is, for example, mechanically, chemically or physically interfacing the third conductive layer 410a with the fourth conductive layer 410b. Separation. As described above, at least two wiring layers 130, 420 can be simultaneously produced by the wiring carrier 4 . And if a structure in which a plurality of line carriers 4, 4, (10) and a plurality of dielectric sheets 2GG, 200a, 2GGb are alternately stacked, a plurality of wiring layers 13〇, 42() can be simultaneously formed. On these dielectric sheets, 2〇〇a, .2〇%. Therefore, production efficiency can be improved while reducing production costs. 3A to 3C are cross-sectional flowcharts showing the method of manufacturing the line structure of still another embodiment of the present invention. First, please refer to FIG. 3A to provide a line carrier _. The line carrier _ includes a composite layer, a first conductive layer 62 〇 and a wiring layer 630. The composite layer 61 includes a first metal layer 612 and a second metal layer 614. The first conductive layer 62 is disposed on the first metal layer 612 and has a surface 622, and the first circuit layer (4) is disposed on the surface 622 of the first electrical layer 620. The material of the first metal layer 612 is, for example, a pure metal. In addition, the material of the first metal 612 may be a combination of words, tin, recording or the foregoing. The thickness of the first metal layer 612 is, for example, between 〇·〇1_~5 melons. Second 1357785 0707006/0707008 25859twf.doc/n The material of the metal layer 614 includes aluminum, copper, nickel or a combination of the foregoing. The thickness of the second metal layer 614 is between 4 〇//m 〜4 〇〇 #m. The surface roughness (Ra) of the surface 622 of the first conductive layer 620 is, for example, between 〇.2 and m to 1.0 so that the ten-point average roughness (Rz) is, for example, between 12#m and 8 〇/zm. The material of the first conductive layer 620 includes copper, nickel, gold or other suitable conductive materials. Further, the thickness of the first conductive layer 62 is, for example, between 1 and m 10 10 m. The material of the first wiring layer 63 is mainly copper or _ may be a conductive metal such as nickel, rhodium, tin or gold, and the thickness thereof is, for example, between 2/zm and 40#m. The line pitch of the first line layer 63 is, for example, between 8 //m and 80/zm. Next, referring to FIG. 3B, the line carrier 600 is pressed onto a first dielectric sheet 700 to cause the first wiring layer 63 to be embedded in the first dielectric sheet 7 (8). Since the surface 622 is a thicker tread, the surface 622 can be well engaged with the first dielectric sheet .700. In addition, the first dielectric sheet 700 may be a semi-cured resin sheet. Further, a line carrier 600a is provided, and the line carrier 6a can be identical to the line carrier 600. Moreover, the line carrier 600a can be pressed to the side of the first dielectric 700 relative to the line carrier 600, so that the line carrier 6A2 2 is disposed in the first dielectric layer 630. Hey. Thus, a double layer plate can be produced. Then, referring to FIG. 3C, the second metal layer 614 is removed by etching to form a wiring structure 800. In the present embodiment, the first metal layer 614 is removed by etching to have a higher process yield. In addition, the line structure 8〇〇 can be a double layer board. The completed circuit structure 8 can be processed into a circuit board according to the requirements. 16 1357785 0707006/0707008 Manufacturing of 25859 twf.doc/n FIGS. 4A to 4C are cross-sectional flowcharts showing a circuit structure method according to still another embodiment of the present invention. Basically, this embodiment is similar to the manufacturing method of the foregoing embodiment, except that the line carrier of the embodiment is a double-sided circuit board and a composite layer having a first metal layer and a second metal layer. Floor
線路層、第二導電層且複合層更具有一第三金屬層）。因 此，本實施例之線路載板不但可將第一線路層鑲嵌至第一 介電片，還可將第二線路層鑲嵌至一第二介電片。也就是 說，本實施例之線路載板可同時在兩個介電片上形成 層。 、The circuit layer, the second conductive layer and the composite layer further have a third metal layer). Therefore, the circuit carrier of the embodiment can not only embed the first circuit layer into the first dielectric layer, but also embed the second circuit layer into a second dielectric layer. That is, the line carrier of this embodiment can simultaneously form a layer on two dielectric sheets. ,
首先，請參照圖4A，提供至少一線路载板900。線路 載板900與線路载板6〇〇 (請參照圖3A)相似，惟兩者差 異之處在於線路载板9〇〇更包括一第二導電層91〇與—第 二線路$ 920，且複合層61〇a更包括一第三金屬層。 其中，第三金屬層616配置於第二金屬層614相對於第一 金屬層612的表面614a上。第二導電層91〇配置於第三金 屬層616上，而第二線路層92〇配置於第二導電層91〇上。 於本實施例中，第二導電層91〇的材質例如是銅、鎳、 金或是其他適合的導電材料。第二導電層91〇的厚度例如 是介於1/zm〜l〇wm之間。此外，第三金屬層616的材 質可以是鈍金屬。第三金屬層616的材質包括鋅、錫、鎳 或前述之組合。第三金屬層616的厚度例如是介於〇 〇1从 m〜5.00//m之間。第二線路層920的材質主要為銅，也 17 1357785 0707006/0707008 25859twf.doc/n 可以疋^、鋅、錫、金等導電性金屬，而其厚First, referring to FIG. 4A, at least one line carrier 900 is provided. The line carrier 900 is similar to the line carrier 6 (refer to FIG. 3A), except that the difference between the two is that the line carrier 9 further includes a second conductive layer 91 〇 and a second line $ 920, and The composite layer 61A further includes a third metal layer. The third metal layer 616 is disposed on the surface 614a of the second metal layer 612 with respect to the first metal layer 612. The second conductive layer 91 is disposed on the third metal layer 616, and the second wiring layer 92 is disposed on the second conductive layer 91. In this embodiment, the material of the second conductive layer 91 is, for example, copper, nickel, gold or other suitable conductive material. The thickness of the second conductive layer 91 is, for example, between 1/zm and l〇wm. Further, the material of the third metal layer 616 may be a blunt metal. The material of the third metal layer 616 includes zinc, tin, nickel or a combination of the foregoing. The thickness of the third metal layer 616 is, for example, between 〜1 and 5.00/m. The material of the second circuit layer 920 is mainly copper, and also 17 1357785 0707006/0707008 25859twf.doc/n can be 疋 ^, zinc, tin, gold and other conductive metals, and its thickness
2/zm〜40/zm之間。第二繞敗层μ A 一0㈣之間。 的線間距例如介於8 ，著’請參照圖4Β ’當壓合線路載板至第 電片700上時，更同時壓合線路载板_至―第二」 700a上，使第一線路層92〇鑲嵌至第二 4B 9〇〇 , «,Μ ，_的數量。•例來說，線路载板_的數量 疋只有一個。 Λ 此外，再提供-線路載板9〇〇a與兩個線路载板_ 且線路載板9GGa可與線路載板相同。並且 二 線路載板9GGM-介電片與第二介電片屬 將線路載板_a壓合至第二介電片狐之相對 ζ’ 板900的-面，使線路载板_a的第—線路層咖镶^ 第二介電片7GGa。同時，可使線路载板_a 二^ 層920鑲嵌至一第三介電片7〇〇b。 一綠路 此時，還可使其中-線路載板_的第一線路声 壓合至第一介電片700之相對於線路载板9〇〇的一面， 線路載板600的第一線路層630鑲嵌至第一介電片7㈨。 同時，還可使其中另-線路載板_的第一線路層63〇斤 合至第三介電片700b之相對於線路载板9〇〇a的—面^ 線路載板600的第一線路層630鑲嵌至第三介電片7㈨匕 如此，將可製得一雙層板。 之後，請參照圖4C，以蝕刻法移除第二金屬層ο*， 18 1357785 0707006/0707008 25859twf.doc/n 以形成多個線路結構丨_ ^於圖4C中，鱗示 結構1GGG為代表。在本實施财，以侧法雜第二金屬 層614 ’可具有較高的製程良率。此外，線路結構1罐可 為了雙層板。製作完成的線路結構1_可依照需要來加工 成為線路板。 承上所述，以線路載板9〇〇可同時製得至少兩層線路 層630、920。並且，若壓合由多個線路载板_、刪及、 _ 1多個介電片期、7〇〇a、7_交錯堆疊的結構時， 可同犄幵/成夕個線路層63〇、920於這些介電片7⑼、7〇〇a、 700b=目此，可提高生產效率，並同時降低生產成本。 口心綜上所述，本發明之一實施例之線路結構的製造方法 疋採，種介電層與複合層的側面接合的線路載板，故可 2複合層的兩導電層於後續製程中因酸钱等製程因素的 ^而=或損壞。此外’線路餘可為雙面線路載板。 若I&由多個線路載板與多個介電片交錯堆疊的結 可同時形成多個線路層於這些介電片上。因此，可 提南生產效率，並同時降低生產成本。 γ用·^外，本發明之另一實施例之線路結構的製造方法是 種由多層金屬層所組成的線路載板，並利用蝕刻法 :::線路载板’以提高線路結構的尺寸穩定性。此外， 柘盥夕板可為雙面線路載板。因此，若壓合由多個線路載 二個介電片交錯堆疊的結構時’可同成多 生產成^電片上。因此，可提高生產效率，並同時降低 19 1357785 0707006/0707008 25859twf.d〇c/n 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明，任何所屬領域中具有通常知識者，在不脫離本發 明之精神和範圍内，當可作些許之更動與潤飾，因此本發 明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1A〜圖1D為本發明一實施例之線路結構的製造方 法的剖面流程圖。 圖2A〜圖2D為本發明另一實施例之線路結構的製造 方法的剖面流程圖。 圖3A〜圖3C為本發明又一實施例之線路結構的製造 方法的剖面流程圖。 圖4A〜圖4C為本發明再一實施例之線路結構的製造 方法的剖面流程圖。 【主要元件符號說明】 100、100a、400、400a、600、600a、900、9〇〇a :線 路栽板 110 :介電層 112 :第一接合部 112a :第一表面 112b :第二表面 114 :第二接合部 122a、122b、614a、622 :表面 120 :第一複合層 120a、620 :第一導電層 20 1357785 0707006/0707008 25859twf.doc/n 120b、910 :第二導電層 122 :側面 124 :介面 130、630 :第一線路層 200、700 :第一介電片 200a、700a :第二介電片 200b、700b :第三介電片 300、500、800、1000 :線路結構 410 :第二複合層 410a :第三導電層 410b :第四導電層 420、920 :第二線路層 610、610a :複合層 612 :第一金屬層 614 :第二金屬層 616 :第二金屬層 21Between 2/zm~40/zm. The second winding layer is between μ A and 0 (four). The line spacing is, for example, between 8, and 'please refer to FIG. 4Β' when the line carrier board is pressed onto the first power sheet 700, and the line carrier board _ to the second board 700a is pressed at the same time to make the first circuit layer. 92〇 inlaid to the second 4B 9〇〇, the number of «, Μ, _. • For example, there is only one number of line carriers _. Λ In addition, a line carrier 9〇〇a and two line carriers _ are provided and the line carrier 9GGa can be the same as the line carrier. And the second line carrier 9GGM-dielectric sheet and the second dielectric sheet are pressed to the line carrier _a to the opposite side of the second dielectric sheet fox's board 900, so that the line carrier board _a - Line layer coffee set ^ Second dielectric sheet 7GGa. At the same time, the line carrier _a layer 920 can be mounted to a third dielectric sheet 7〇〇b. At this time, the first line of the line carrier board can be acoustically coupled to the side of the first dielectric sheet 700 opposite to the line carrier board 9 , and the first line layer of the line carrier board 600 630 is inlaid to the first dielectric sheet 7 (nine). At the same time, the first circuit layer 63 of the other line carrier board _ can be clamped to the first line of the third dielectric sheet 700b with respect to the line carrier board 600 of the line carrier board 9A. Layer 630 is inlaid into third dielectric sheet 7 (9). Thus, a double layer panel can be produced. Thereafter, referring to FIG. 4C, the second metal layer ο*, 18 1357785 0707006/0707008 25859 twf.doc/n is removed by etching to form a plurality of wiring structures ^_^ in FIG. 4C, and the scale structure 1GGG is represented. In this implementation, the side-by-side second metal layer 614' may have a higher process yield. In addition, the line structure 1 can be a double layer board. The completed circuit structure 1_ can be processed into a circuit board as needed. As described above, at least two wiring layers 630, 920 can be simultaneously produced by the line carrier 9 。. Moreover, if the structure is laminated by a plurality of line carriers, a plurality of dielectric sheets, and a plurality of dielectric sheets, 7〇〇a, 7_ are stacked, the same can be used. 920 on these dielectric sheets 7 (9), 7〇〇a, 700b = this can improve production efficiency while reducing production costs. In summary, the manufacturing method of the circuit structure according to an embodiment of the present invention adopts a circuit carrier in which the dielectric layer and the side of the composite layer are joined, so that the two conductive layers of the composite layer can be used in subsequent processes. Due to process factors such as acid money, it is = or damaged. In addition, the line can be a double-sided line carrier. If I& a stack of a plurality of line carriers interleaved with a plurality of dielectric sheets, a plurality of wiring layers can be simultaneously formed on the dielectric sheets. Therefore, it is possible to increase production efficiency and at the same time reduce production costs. In addition to γ, the manufacturing method of the line structure of another embodiment of the present invention is a circuit carrier consisting of a plurality of metal layers, and an etching method::: a line carrier board is used to improve the dimensional stability of the line structure. Sex. In addition, the 柘盥 板 board can be a double-sided line carrier. Therefore, if the structure in which a plurality of dielectric sheets are alternately stacked by a plurality of wirings is pressed, it can be produced in the same manner. Therefore, the production efficiency can be improved, and at the same time, 19 1357785 0707006/0707008 25859 twf.d〇c/n. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any person having ordinary knowledge in the art, The scope of protection of the present invention is defined by the scope of the appended claims, unless otherwise claimed. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1D are cross-sectional flowcharts showing a method of manufacturing a line structure according to an embodiment of the present invention. 2A to 2D are cross-sectional flowcharts showing a method of fabricating a line structure according to another embodiment of the present invention. 3A to 3C are cross-sectional flowcharts showing a method of fabricating a line structure according to still another embodiment of the present invention. 4A to 4C are cross-sectional flowcharts showing a method of fabricating a line structure according to still another embodiment of the present invention. [Main component symbol description] 100, 100a, 400, 400a, 600, 600a, 900, 9〇〇a: circuit board 110: dielectric layer 112: first bonding portion 112a: first surface 112b: second surface 114 : second joint portion 122a, 122b, 614a, 622: surface 120: first composite layer 120a, 620: first conductive layer 20 1357785 0707006/0707008 25859twf.doc / n 120b, 910: second conductive layer 122: side 124 Interfaces 130, 630: first circuit layers 200, 700: first dielectric sheets 200a, 700a: second dielectric sheets 200b, 700b: third dielectric sheets 300, 500, 800, 1000: line structure 410: Two composite layers 410a: third conductive layer 410b: fourth conductive layers 420, 920: second wiring layers 610, 610a: composite layer 612: first metal layer 614: second metal layer 616: second metal layer 21